Abstract: Circuits, integrated circuits, and methods are disclosed for bimodal disable circuits. In one such example method, a counter is maintained, with the counter indicating a logic level at which an output signal will be disabled during at least a portion of one of a plurality of disable cycles. The logic level indicated by the counter is transitioned. An input signal is provided as the output signal responsive to the enable signal indicating that the output signal is to be enabled, and the output signal is disabled at the logic level indicated by the counter responsive to the enable signal indicating that the output signal is to be disabled.

Abstract: Circuits, integrated circuits, and methods are disclosed for bimodal disable circuits. In one such example method, a counter is maintained, with the counter indicating a logic level at which an output signal will be disabled during at least a portion of one of a plurality of disable cycles. The logic level indicated by the counter is transitioned. An input signal is provided as the output signal responsive to the enable signal indicating that the output signal is to be enabled, and the output signal is disabled at the logic level indicated by the counter responsive to the enable signal indicating that the output signal is to be disabled.

Abstract: The present invention discloses a vMOS based multi-valued counter unit. The counter unit includes a vMOS source follower and at least a control gate connected the vMOS source follower. The control gate includes a first dual-value D flip-flop, a second dual-value D flip-flop, an AND gate, and an OR gate. The present invention utilizes the vMOS to replace the complicated threshold value operations of the multi-value logic. The current invention implements the true multi-value logic and a multi-base multi-value counter by increasing the number of the dual-value D flip-flop, and connecting the dual-value D flip-flop to the input control gate of the vMOS follower. The present invention applies the asynchronous carry-over concept to implement the multi-digit multi-value counter, and it also has been verified by the simulation of P Simulation Program with Integrated Circuit Emphasis (SPICE).

Abstract: The present invention discloses a neuron MOS based multi-valued counter unit. The counter unit includes a neuron MOS source follower and at least a control gate connected the neuron MOS source follower. The control gate includes a first dual-value D flip-flop, a second dual-value D flip-flop, an AND gate, and an OR gate. The present invention utilizes the neuron MOS to replace the complicated threshold value operations of the multi-value logic. The current invention implements the true multi-value logic and a multi-base multi-value counter by increasing the number of the dual-value D flip-flop, and connecting the dual-value D flip-flop to the input control gate of the neuron MOS follower. Comparing to the conventional multi-value counter, the present invention reduces the necessary components in constructing the counter, and it also reduces the cost and power consumption.

Abstract: A circuit provides a programmable phase shift feature, where the phase shift is programmably selectable by a user. This circuitry may be incorporated in a programmable logic device (PLD) or field programmable gate array (FPGA) to provide additional programmability features. The programmable phase shift circuitry may be implemented within a phase locked loop (PLL) or delay locked loop (DLL) circuit. In an implementation, the programmable phase shift circuitry is implemented using two programmable counters.

Abstract: In a digital shift register comprising a series of substantially identical bistable circuits, a reference voltage required for the bistable circuits is generated by coupling a common node to the outputs of the bistable circuits via resistors, in such a way that the reference voltage is the means of the output voltages of the bistable circuits. Further, a method is described for the advanced presentation of information to the bistable circuits of the shift register via the reference circuit, so that the bistable circuits are changed over faster and the maximum clock frequency of the shift register is increased. By incorporating a gate circuit ahead of the shift register, a programmable frequency divider may thus be provided.

Abstract: An integrable semiconductor circuit for a multi-stage frequency divider having a number of master-slave flip-flop cells constructed in current mode logic forming the individual divider stages which are connected in series to a supply voltage and which are accordingly at different levels of the supply voltage has an input stage to which an input signal at an input frequency, and the inverse thereof, are supplied. The input stage is in the form of a differential amplifier having two identical transistors which are connected to a constant current source. The differential amplifier forms the first divider stage, that is, the first master-slave flip-flop, in combination with a first network including a number of transistors and load resistors. The further divided stages do not require an input circuit, therefore each subsequent stage includes only a network corresponding to the network of the first stage.

Abstract: Diode load emitter coupled logic circuits is described that utilizes forward biased diodes in the load circuits. The load circuits may be comprised of a single diode or two or more diodes connected in series. If a single diode is used in the load circuits, the slope factor of the diode must be greater than or equal to the slope factor of switching transistors in the logic circuit. External bias circuitry provides a bias current which can be varied for varying the frequency of operation of the logic circuit. High speeds at low power dissipations can be obtained since the switching transistors in the logic circuits do not switch completely on and off.

Abstract: Integrable frequency divider circuit, including a preamplifier in the form of a differential amplifier having a signal input for receiving signals to be processed, a reference input and two outputs, a frequency divider having divider stages including a first divider stage, each being in the form of identical series-connected flip-flop cells, the first divider stage having two inputs each being connected to a respective one of the two outputs of the differential amplifier for receiving the signals to be processed, an operational amplifier having an output directly connected to the reference input of the differential amplifier and having two inputs, two resistors each being connected between a respective one of the inputs of the operational amplifier and a respective one of the outputs of the differential amplifier, a capacitor connected between the inputs of the operational amplifier, and another capacitor connected between the output of the operational amplifier and reference potential.

Abstract: A binary counter consists of some unit stages having a first pair of coincident gates composed of a first and a second coincident gates, a first input terminal of each being cross-coupled with the other's output terminal, and a second pair of coincident gates composed of a third and a fourth coincident gates, a first input terminal of each being cross-coupled with the other's output terminal.

Abstract: An integrated injection logic circuit includes a plurality of integrated injection logic gates each having a PNP transistor for injector and NPN transistor for signal inversion, and an injector common line to which the respective injector PNP transistors are commonly connected. A test pad for electric probing is provided at least one location of the injector common line.