Abstract: A delay line of individually selectable delay elements can operate as an oscillator in an open loop mode to track process variation or drive a clock signal that varies with temperatures and voltages in the system. The delay line oscillator can also operate in a closed loop mode to match a frequency given by a tuner ratio and a reference clock. The delay line can also be used for measuring clock jitter or duty cycle.

Abstract: The counter of the present invention includes an input unit, a sampling unit and a determiner unit. The input unit receives a plurality of control signal including a mode selection signal, a clock signal and a reset signal. The sampling unit receives output signals of the input unit based on the clock signal and reset signal. The sampling unit has a plurality of latches and generating a plurality of first output signals and the adjacent latch of the plurality of latches are coupled to each other. The determiner unit is coupled to the sampling unit to receive the plurality of first output signals and is coupled to the input unit to receive an output signal based on the mode selection signal. The determiner unit outputs a plurality of count signals indicative of a count value, which is incremented or decremented based on the mode selection signal.

Abstract: A high speed CMOS binary up/down counter having a 200 MHZ clock rate comprises a 4-bit counting section that may be concatenated in multiple 4-bit sections. The counter performs in an up-count mode or a down-count mode in accordance with the state of a mode select signal. Each stage of the 4-bit counting section comprises a propagate/kill/generate gate for determining the status of a carry signal to a next stage, except the last stage of a 4-bit section, which does not require such a gate because it is coupled to a carry-forward generator along with the outputs from the other preceeding stages in the section. Each 4-bit section performs the counting function through a successive process of modulo-two sums of a lower order carry and the current state of a counter stage without the need for cumbersome gating structures.

Abstract: A pipeline binary updown counter is comprised of simple stages that may be readily replicated. Each stage is defined by the Boolean logic equationA.sub.n (t)=A.sub.n (t-1).sym.[(U.multidot.P.sub.n)+(D.multidot.Q.sub.n)]where A.sub.n (t) denotes the value of the nth bit at time t. The input to the counter has three values represented by two binary signals U and D such that if both are zero, the input is zero, if U=0 and D=1, the input is -1 and if U=1 and D=0, the input is +1. P.sub.n represents a product of A.sub.k 's for 1.ltoreq.k.ltoreq.-1, while Q.sub.n represents the product of A's for 1.ltoreq.k.ltoreq.n-1, where A.sub.k is the complement of A.sub.k and P.sub.n and Q.sub.n are expressed as the following two equationsP.sub.n =A.sub.n-1 A.sub.n-2 . . . A.sub.1Q.sub.n =A.sub.n-1 A.sub.n-2 . . . A.sub.1which can be written in recursion form asP.sub.n =P.sub.n-1 .multidot.A.sub.n-1Q.sub.n =Q.sub.n-1 .multidot.A.sub.n-1with the initial values P.sub.1 =1 and Q.sub.1 =1.

Abstract: A multi-digit counter circuit performs both successive data production function and non-successive data production. Successive data is produced by an increment or decrement operation according to a first carry (borrow) signal. Non-successive data is produced by a control circuit which applies a second carry (borrow) signal independently of the first carry (borrow) signal to an arbitrary selected digit or digits. The arbitrary digit is designated according to the distance between the preceding data and the following data to be produced.

Abstract: A counter cell for counting either up or down by one or two includes a multiplexer section, an increment/decrement section, and a carry section. The multiplexer section is responsive to control signals and input carry signals for generating a count signal which determines the counting by one or two. The increment/decrement section is responsive to count signal and an increment strobe signal for generating an incremented output signal and a decremented output signal. The carry section is responsive to the increment/decrement section and the input carry signals for generating a carryout-by-one signal and a carryout-by-two signal. A number of these counter cells are arrayed to form an N-bit counter.

Abstract: An M-bit binary counter is disclosed having M sequentially ascending binary value stages, the first stage being the lowest significant bit. In accordance with the invention, each stage above the least significant bit stage has a subsequent value decoder which has the function of determining the effect of lower order carry bits on higher order stages with a minimum of signal delay. The decoder includes the feature of using natural threshold FET devices in a transfer gate configuration to perform logical AND functions so as to minimize gate delays in decoding a carry condition for higher order stages. A selective up-counting or down-counting function is also disclosed.

Abstract: PASS transistors are used to reduce the layout complexity of logic circuits by using PASS transistors connected to pass a first and second input function to an output node in response to selected control signals, thereby to generate a selected output function on the output node. The PASS transistor comprises a transistor capable of passing an input function in response to a control signal applied to the transistor thereby to generate an output function related to the input function. In general, the input function comprises less than all of a set of input variables and the control function comprises one or more of the remainder of the set of input variables.

Abstract: A binary up/down counter stage particularly suitable for CMOS implementation. The counter stage includes an exclusive OR gate having a first input for receiving a toggle signal, a flip-flop having a data input coupled to the output of the exclusive OR gate and Q and Q outputs, the Q output of which provides the stage output and a feedback to the second input of the exclusive OR gate, and a multiplexer having first and second inputs coupled to the Q and Q of the flip-flop respectively, the output of the multiplexer being logically ANDED with a toggle-in signal to provide a toggle-out signal for a further counter stage in cascade.

Abstract: A binary counter consists of a plurality of unit stages each having a bistable circuit, a buffer circuit for generating an output corresponding to an output state of the bistable circuit, a switching circuit for supplying an output of the buffer circuit to the bistable circuit, and a coincidence gate for supplying a clock signal to the next unit stage in accordance with the predetermined output state of the bistable circuit.

Abstract: A circuit for incrementing or decrementing a binary number is described. An M bit binary number is applied to M dynamic latch circuits. The latch output signals are applied to M logic units each comprising an exclusive OR, an exclusive NOR and one transistor. The transistors of the respective logic units are connected serially, with the transistor of the logic unit operating on the LSB of the binary number being further connected to a carry in or count signal. The exclusive OR is responsive to the carry in signal and the latched signal to increment/decrement or pass through the respective bit of the binary number. The exclusive NOR is responsive to an Up/Down signal and the latched signal for controlling the conduction state of the respective transistor thereby providing a carry in signal to the input of the next adjacent logic unit operating on the next more significant bit of the binary number.

Abstract: A first variant using conventional ratio-type two-phase design with nonoverlapping clock signals consists of a first inverter (I1), a complex gate (KG), a first transfer transistor (T1), a second inverter (I2), and a third inverter (I3) connected in series with respect to the signal flow. The complex gate (KG) consists of two NORed AND elements (U1, U2). The output of the second inverter (I2) is the count-up output (VA), and that of the third inverter (I3) is the count-down output (RA). The count-up output (VA) is coupled through a second transfer transistor (T3), controlled by the second clock signal (F2), to the first input of the first AND element (U1), whose second input is connected to the output of the first inverter (I1).