Abstract: A pulse density modulation circuit has a counter which produces a most significant bit through a least significant bit output based on a clock input. The circuit also has a comparator with two sets of most significant bit through least significant bit inputs that produces an output based on a comparison of the two sets of inputs. The first set of comparator most significant bit through least significant bit inputs receives respectively a most significant bit through a least significant bit of an input reference signal. The second set of comparator most significant bit through least significant bit inputs receives the counter most significant bit through least significant bit output in a non-sequential bit order. The non-sequential bit order can be a bit reversed order wherein the counter most significant bit through least significant bit output are respectively connected to the comparator least significant bit through most significant bit input.

Abstract: A counter circuit includes Johnson-type counters of m stages, each counter including a plurality of flip-flops connected in a cascade connection, each flip-flop receiving a clock signal at a respective clock input end. In the constitution, signals at respective output ends of flip-flops in a (k-1)-th stage counter are simultaneously input to respective clock input ends of flip-flops in each counter of a k-th stage and more. As a result, it is possible to obtain a signal having an arbitrary ratio of frequency division with high speed, while relatively simplifying the circuit constitution.

Abstract: A counter device having a jumping function includes a counter circuit for counting clock pulses, a circuit for setting a jump starting count, a circuit for setting the number of bits to be jumped, a detecting circuit for detecting equality/unequality between a count of the counter circuit and the jump starting count as set, and a circuit for modifying the count of the counter circuit by the number of bits to be jumped in response to equality detection by the detecting circuit. The modifying circuit varies the count in the same direction as a direction of variation of the count provided by the counter circuit. This construction realizes a counting function which jumps a desired count or counts from a selected count.

Abstract: The present invention provides a MRP generator comprising m MRP generating circuits connected in parallel which are operated at a 1/m clock speed and have a predetermined time relation to each other, wherein the MRP generating circuits are operated on the multiplex basis. The operating speed is improved.

Abstract: An apparatus for the detecting of metal parts (12) which move relative to a metal sensitive sensor arrangement has at least two part sensors which transmit an electrical pulse to an electronic evaluation circuit for a particular approach by a metal part (12). Several part sensors are connected spatially in series with one another so that a specific metal part (12) causes the part sensors to respond in sequence. The electronic evaluation circuit (13) then transmits a signal when and only when it detects the pulse sequence which arises through sequential response of the part sensors.

Abstract: A circuit for time stamping event signals, e.g. zero-crossings, using coarse and fine timers. The fine timer is a circuit section which subdivides a period from a phase-locked ring-oscillator into 2N subparts. An event signal is timed by latching a digital representation of a particular subpart. The digital representation of the subpart is an N-bit dual thermometer code which uniquely identifies each subpart with each adjacent subpart differing by only one bit. The subparts are made finer in time quantization than the propagation delay of one active element in the ring oscillator by the use of linear combiner elements. The dual thermometer code, encoded post-latching into a binary code, forms the "fine" timing part of a binary word representation of the event time. The event also latches the count states of a pair of lead-lag counters in a master-slave configuration counting ring oscillator periods. These counters change states respectively before and after the dual thermometer code turn-overs.

Abstract: Two cascaded eight-bit maskable counters (62) and (64) provide a sixteen-bit output, for instance, to a digital-to-analog converter (10). Each of the counters (62) and (64) is a maskable counter that is operable to mask off a programmable number of the least significant bits therein. The next adjacent bit thereto comprises a virtual least significant bit. During the counting operation, the count is initiated at the virtual least significant bit such that the virtual least significant bit is clocked for each counting cycle. An initial value is first loaded into the counter (62) and (64) on a data bus (74). Thereafter, masked data is loaded into the counters (62) and (64) on the same data bus (74) to define the ones of the least significant bits that are masked off. In such a manner, the overall resolution of the counter can be varied without varying the clock rate to the counter.

Abstract: For one of memory divisions that is selected at a time as a selected division N(m) in a memory for use in putting a sound processing device in operation of generating a three-dimensional image of an acoustic field, a difference signal is produced to represent a clock count minus a delay count n(m) specific to the selected division and to have more and less significant bits. For use as an address signal supplied to the memory, a part of the more significant bits is changed to a like part of a memory space address specific to the selected division. As usual, the less significant bits are used to indicate read aR(i(m)) and write W(i(m)) pointers which are spaced in the selected division by the delay count. The part may be specified to be wide and narrow when the selected division is narrow and wide. Alternatively, the part may have a predetermined bit width.

Abstract: A code generation control device is disclosed, which is provided with circuits indicated in following items (a) to (d) in order to set initial information for generating codes in a plurality of PNGs:(a) a strobe pulse generating section, which outputs a strobe pulse, every time the initial information is set in one PNG;(b) a counting section, which counts the output of (a) on the basis of the number of PNGs, in which the initial information is set;(c) a decoder section, which decodes the count value of (b) and chip-selects one of the plurality of PNGs; and(d) a control section, which outputs a strobe pulse to each of the PNGs and a code chip number counting section on the basis of a code switching control signal at that time on the basis of a signal outputted by (b), when the count value reaches a predetermined number of PNGs, in which the initial information is set, and the strobe pulse outputted by (a).

Abstract: A matrix of multiplexed synchronous binary counters for an integrated circuit comprising a sequence of m counter cells (CC1, CCm) each provided with an individual data input link (Din.1, Din.m) and an individual data output link (Dout.1, Dout.m), and controlled by means of common links comprising a clock link (Clk) for synchronization, a load link (LOAD), and n select links (LS1 to LSn). Each counter cell (CC) includes n memory cells (CM1 CMn), each organized around a unique memory element (B1 to Bn) which is individually selectable by means of the select links (LS1 to LSn), which cells are connected in parallel between the individual data input link (Din) and the individual data output link (Dout) of the said counter cell (CC), and share a common loop memory element (BR) having its data input connected to the individual data ouput link of the counter cell under consideration (CC) via an incrementation circuit.

Abstract: A clock generating circuit for use in a signal processing circuit to enable it to be synchronized with other circuits in response to a reset signal uses a multi-state circuit which is cyclically stepped through its states by a clock drive signal and a decoder responsive to the state of the multi-state circuit to produce the required clock pulses. The reset signal is used to stop the multi-state circuit at a particular state and hold it there for a period of time enabling other similar clock pulse generating circuits to reach the same state and be held there. At the end of the period of time the multi-state circuits resume their cyclic stepping with all the circuits in synchronism.

Abstract: A serial clock generating circuit for generating a serial clock in phase with a clock included in a received serial data on the basis of an input clock having a frequency N times of a serial data transfer rate of the received serial data, comprises an edge detector for detecting a level transition of the received serial data so as to generate a level transition detection signal, and a counter for counting the input clock. A first comparison register is provided for comparing a count value of the counter with a first programmable predetermined value at each one counting operation of the counter, so as to generate a first coincidence signal when the count value of the counter is coincident with the first programmable predetermined value.

Abstract: The temporal signal generated has a periodic configuration defined by an arrangement of seed patterns resulting from a branching construction employing n successive applications of m pattern type laws each defined by a specific arrangement of p pattern types. This construction amounts to defining a periodic signal configuration as a component "an" of the nth term Un with several components (an, bn) of a recurrent sequence defined at the level of its components by a particular recurrent composition law, the initial term UO having for its components the seed patterns (aO, bO). The temporal signals known by the name "fractal" result from a branching construction of this kind.

Abstract: An electronic pulse counter includes a given number of shift registers each having a different number of memory elements, an input, an output and a clocking line. Each of the shift registers is countercoupled by a negation between the input and the output thereof. A pulse counter input is formed by interconnection of the clocking lines of all of the shift registers. Pulse counter outputs are formed by the outputs of the shift registers.

Abstract: Error rates above a given threshold are detected by initiating a counter to count a group of n bits on each occurrence of an error bit. The counters are inspected on each occurrence of an error to see whether the counter initiated x error bits earlier is still counting. If the counter is still counting the error rate is above a threshold of x error bits in a group of n bits in a serial stream.

Abstract: This invention relates to an improved signal reader for reading signals from transponders placed on moveable objects such as ship containers, automobiles or railroad cars. The reader sends out a continuous signal, which is modified by the information contained in the transponder attached to the moveable object. Multiple antennas, each of which receive separate signals, may be multiplexed at the reader. The improved circuit of the invention provides quick recognition of the receipt of a valid signal from a transponder or, in the alternative, the absence of such a valid signal.

Abstract: A method and apparatus for testing operation of an n-bit counter with carry inputs in an electronic system. The n-bit counter is divided into a high section and a low section. An external carry is forced to the lowest significant bit of the high section. All states of both sections of the counter are clocked, each state of each of the sections being clocked simultaneously with a corresponding state of the other of the sections. The natural carry is selected so that, at the next clock cycle, when the low section is set at the highest count, the highest significant bit of the low section is carried to the lowest significant bit of the high section.

Abstract: A control circuit such as a microcomputer sets only the starting address of the memory in which initial information for generating a maximum length recurring sequence is stored and the number of chips of the maximum length recurring sequence and the initial information for generating a maximum length recurring sequence is set from the memory in the maximum length recurring sequence generator by a hardware. The hardware for accessing the memory is constructed by a counter working with a high speed clock. The number of chips of the maximum length recurring sequence set by the external control circuit is counted by a counter working with a high speed clock.

Abstract: A glitchless terminal count indication digital counter having a clock signal as an input thereto is disclosed and comprises a state logic means comprised of a plurality of DQ flip-flops for providing a digital count with the clock signal being sent to an input thereof, a next state decode means, a next terminal count decode means for providing an indication at its output that the digital output count will reach a terminal count at the next clock cycle, and a terminal count logic means for obtaining the indication from the next terminal count decode means and providing therefrom at the next clock cycle a glitchless terminal count indication. The next state decode means has inputs and outputs, with the digital count being an input thereto, and the state logic means and the next terminal count decode means being coupled to the output thereof.

Abstract: An m sequence generator according to this invention has a built-in flipflop circuit, whose input is the output of an exclusive OR gate for adding two m sequence inputs modulo 2 and which outputs a GOLD code synchronized with the rise or the fall of a clock signal and can generate selectively the m sequence or the GOLD code.

Abstract: An electronic signal synchronization apparatus useful with radars and other electronic systems requiring synchronizing signals provides, for a range of N pulses, M sets of synchronizing signals which occur at M different range event pulse counts. The signal synchronization apparatus comprises a microprocessor and a synchronizer, the latter including a range pulse counter, a range memory, an event counter and an event memory. The range memory, preferably a RAM, is connected for outputting an event count enabling signal each time the range counter reaches an event pulse count. The event counter increments one count each time a count enabling signal is received from the range memory. At each event count, the event memory outputs the corresponding set of synchronizing signals. At the Nth range pulse count, the event memory provides an END OF RANGE signal which resets the range and event counters to thereby enable the counters to repeat the counting as many times as is necessary.

Abstract: A meter for remote inspection having a wheel assembly which enables a counting number indicating the amount of consumption of a measuring object, such as electric energy, or city water or the like to be remotely inspected in a remote inspection center equipped with computer systems. The wheel assembly comprises a plurality of wheels representing respective decimal columns, a series of pinion wheels for transmitting a driving torque, detecting means for detecting the binary-coded signal of a counting number including four photo-sensor portions, and fixed disk means for mounting the detecting means. A predetermined one of side surfaces of some wheels is composed of ten zones which are uniformly divided and selectively colored by two kinds of colors to provide the binary-coded signal of each order of decimals of the counting number.

Abstract: Apparatus is disclosed for reversing the bit order of a portion of a digital word. The apparatus contains a shifter, connected to the input through a bit reversing means, and selector means which forms an output word by selecting appropriate bits either directly from the input word or from the output of the shifter.

Abstract: A circuit arrangement for adding, storing and reproducing electric counting pulses, is suggested, which preferably serves as an electronic kilometer counter of a motor vehicle with a distance transmitter (10). The circuit arrangement comprises an overwritable nonvolatile storage (16) which is divided into a series of storage registers (19) in which the counting pulses are stored by a one-unit shift code. When erroneous information occurs in any storage cell, the error of the indicated storage contents amounts to a maximum of .+-.1. This is achieved in that the control circuit (13), beginning with the first register (14), writes each new counting pulse into the next register (13, 12 . . . ) and, after reaching the last register (0), increases the contents of the first register and then the following respective registers by one unit with the next counting pulses. Such a circuit arrangement is to be used as a kilometer counter, operating time counter, quantity or piece counter, and the like.

Abstract: A look ahead terminal counter and a method for generating a terminal count output signal are disclosed. The counter comprises a plurality of counter registers connected to counter enable circuitry for sequencing the registers at a predetermined counter rate. Terminal count enable circuitry is connected to the counter circuitry, e.g. at the input ports of the counter registers, and is operative to generate a terminal count enable signal when those input ports are at a predetermined state. The terminal count enable signal and clock signal are communicated to an output register operative to generate a terminal count output signal when a clock signal is received during the simultaneous presence of the terminal count enable signal.

Abstract: In a counting circuit having non-volatile electrically erasable memory elements and a plurality of similar counters each representing one place of the count, respective memory elements of suitable capacity are associated with the counters. Low value counters can be connected cyclically to each other via their counting inputs and transfer outputs. Their association with the other places of a count is changed as a function of the count of the highest-value place. In this way, the result is obtained, without additional expense for memory, that the individual memory elements are erased equally frequently during the life of the counting circuit.

Abstract: A multi-mode counter network and a method of testing the operation of the multi-mode counter network are disclosed. The multi-mode counter network comprises a counter circuit formed of a plurality of counter registers and a multiplexer circuit formed of a plurality of multiplexers wherein said multiplexers are connected to and associated with one of the registers and are operative to selectively vary the input signal communicated to the associated register such that the registers operate in one of a plurality of operational modes. By controlling the selection of the input signal communicated to the registers the network may be alternately configured to perform traditional counting functions or may be configured to provide a serial signal path for communicating a test pattern through the registers and multiplexers to test the operation of the multiplexers and registers. The test pattern is communicated through the circuit, bypassing counter enabling circuitry, and thus independent of the network counter rate.

Abstract: A semiconductor device comprising first and second transistors connected in series with one another to pass a primary current upon receipt of a control signal at the gate of the second transistor. The first transistor is coupled to receive a base current from a secondary power source. A third transistor is coupled to have a primary current path to shunt the base current away from the first transistor upon conduction of the third transistor. A capacitor is connected between the base of the third transistor and the base of the first transistor so that, at the moment the second transistor ceases conduction in response to the control signal, a voltage gradient is generated between the base of the first transistor and the base of the third transistor, causing the current from the secondary power source to charge the capacitor and thus render the third transistor conductive, thereby shunting the base current from the secondary power source away from the base of the first transistor.

Abstract: A semiconductor device comprising first and second transistors connected in series with one another to provide a path for a primary current upon receipt of a control signal at the gate of the second transistor. The first transistor is coupled to receive a base current from a secondary power source. A third transistor is coupled to have a current path which shunts the base current of the first transistor upon conduction of the third transistor. A zener diode is connected between the base of the third transistor and the common junction of the first and second transistors and is arranged to provide base current to the third transistor thereby causing the third transistor to be conductive upon turn-OFF of the second transistor, and as a consequence quickly turning OFF the first transistor.

Abstract: A counter cell for counting either up or down by one or two includes a multiplexer section, an increment/decrement section, and a carry section. The multiplexer section is responsive to control signals and input carry signals for generating a count signal which determines the counting by one or two. The increment/decrement section is responsive to count signal and an increment strobe signal for generating an incremented output signal and a decremented output signal. The carry section is responsive to the increment/decrement section and the input carry signals for generating a carryout-by-one signal and a carryout-by-two signal. A number of these counter cells are arrayed to form an N-bit counter.

Abstract: An improved, high-speed frequency divider circuit (32) is presented. The frequency divider circuit (32) is comprised of three D-type flip-flops (34, 36 38). The three flip-flops (34, 36, 38) are clocked synchronously for higher speed of operation. The design of the frequency divider circuit (32) embodies a sagacious state assignment to minimize the number of bits that change state on any given state transition, thus reducing the possibility of faulty circuit operation.

Abstract: The majority circuit has an (n+1)/2-notation counter circuit comprising a plurality of cascade-connected binary counters. An odd number of n-bit serial data are counted by the counter circuit, and an output of the binary counter of the last stage is taken out as a majority output of the majority circuit.

Abstract: A counter/divider apparatus employing an array of counters arranged in parallel. Each counter repeatedly counts through a sequence of a number of clock pulses. The number is different for each counter and the numbers are relatively prime numbers. The outputs of the counters are applied to a detector that recognizes a preset combination of output signals which is present after a predetermined number of clock pulses have been received. The detector then produces an output pulse which clears all the counters to their initial states, and the cycle is repeated. The apparatus thus divides the input clock pulses by the aforementioned predetermined number.

Abstract: A programmable counter system of the swallow operation type using binary counters is disclosed. The counter comprises a prescaler for frequency dividing an input signal by a frequency division factor "2.sup.n -1" or "2.sup.n ", upper and lower order bit counters for counting down an output signal from the prescaler, a flip-flop for selecting either the frequency division factor "2.sup.n -1" or "2.sup.n " according to the logical level of the output signal of the counter A or B, and inverters for level inverting programming data and applying them to the lower order bit counter A, thereby setting a division number of the counter A to a complement of the binary code of the programming data.

Abstract: The counting circuit described issues a numerical information which is a non-linear function of the number of pulses applied to its input.The circuit comprises dividers which divide by integers K.sub.i the pulses applied to their inputs. A first selector connects the output of one of the dividers to the input of a counter in response to a first signal. The content of the counter is compared with numbers k.sub.i by comparators. The output of one of the comparators is connected to a control circuit by a second selector controlled by a second signal issued by the control circuit in response to a comparison signal.

Abstract: An apparatus, method and system for identifying, recording, and marking transactions such as, but not limited to, individual business agreements or specific events such as occurring in the commercialization of goods or services. An apparatus comprising a non-numeric memory system, one or more numeric memory registers, a marking means, a means to initialize the alphabetic memory system and numeric registers and means to increment the various alphabetic memory system and numeric registers so as to uniquely identify consecutive events or transactions. The invention has the operability to move the series print position of the non-numeric memory system and the one or more numeric memory registers at various times during the usage of the invention, thereby economizing on the number of characters required to identify a predetermined number of events or transactions.

Abstract: This invention concerns counters.More specifically, it relates to a non-volatile counting decade, comprising five flipflops, the outputs of which represent the decimal contents of the decade in the Johnson code. In this code, no flipflop changes its state more than twice in the course of a counting cycle from 0 to 10. The state of the counter is safeguarded on every incrementation, in separate safeguard circuits for each flipflop, formed of MNOS or floating-base transistors. However, any flipflop output state is safeguarded only if its state has changed after incrementation, this being detected by a logic circuit, which selects the safeguard signal for each flipflop.By means of an extremely simple combinative circuit, this invention thereby greatly reduces the number of writing cycles to be performed by the MNOS or floating-base transistors, which cannot withstand an excessive number of writing cycles.

Abstract: A pulse generator circuit provides output pulses that vary in frequency in accordance with a digital input word. An external source frequency produces a predetermined number of pulses over a fixed time interval with the pulse generator circuit selecting the desired number of pulses from those in this interval to provide at its output. Any number of the pulses between zero and the total number in the interval may be selected. To assure their distribution over the interval, the pulses are arranged to occur in sets with the pulses of a given set occurring in the middle of the pulses of another set in order to prevent the bunching of selected pulses into any part of the interval. The sum of the pulses in the combined sets then provides in accordance with the digital input word the desired frequency which ranges up to and includes the source frequency.

Abstract: A plurality of identical circuit board identification generators are individually located on an associated plurality of circuit boards in a computer system, each generator providing a unique identification for each associated circuit board. Identification numbers are automatically and sequentially generated by the generators upon the initial system turn on or upon a resetting of the system. The generators comprise a counter and logic circuitry for enabling the counters. The counters are initially disabled and pre-set to a maximum count. The first counter is then enabled and counts from the maximum to zero, and delivers an enable signal to the logic circuitry in the next circuit board to enable that counter. The enable signals propagate from board to board until the last board commences its count, at which time all counters are disabled. In this manner, N circuit boards will be identified as boards "O" through "N-1.

Abstract: Hashing of a key data signal is accomplished by utilizing a pseudo random number signal generator for generating a randomized signal in response to the key data signals and an output register for serially receiving the generated pseudo-random signal and for providing segments of the serially-received signal at its output. A counting circuit responsive to a preselected number of shift signals provides an output valid signal when the preselected number of shift signals has occurred and further shifts the pseudo-random number signal generator an amount corresponding to the preselected number of shift signals. The method of the present invention utilizes the steps of presetting the pseudo-random number generator and the counting circuit to an initialized state. The counting circuit is then loaded with a predetermined count whereupon key data is entered into the pseudo-random number generator so as to randomize the key data.

Abstract: This disclosure relates to a timing circuit for a digital display, which circuit includes a series of counters, each having four stages such that each counter will drive the next stage only when it has progressed from zero to seven. By reading out the state of each stage of the respective counters, selected counts can be decoded from only two of the respective stage readouts.