Abstract: A computer-implemented method for of constrained carries on speculative counters includes providing one or more speculative counters having an upper portion of most significant bits partially embedded in a random-access memory (RAM) array, and a pre-counter portion external to the RAM array having a plurality of least significant bits. The one or more speculative counters are configured to count a plurality of events of interest during a processor core instruction execution. A carry output from the pre-counter portion to the RAM array is suppressed for a duration of a speculative event period.

Abstract: A counter configured to perform counting at both edges of an input clock to output an additional value or a subtraction value for a previous count value and a next count value includes a first latch circuit that latches the input clock, a second latch circuit that latches an output from the first latch circuit, a holding section that holds data of the 0th bit of a count value, and a correction section that performs count correction on data of the first and subsequent bits of the count value on the basis of an output of the second latch circuit.

Abstract: A counter in a non-volatile memory including at least two sub-counters, each counting with a different modulo, an increment of the counter being transferred on a single one of the sub-counters and the sub-counters being incremented sequentially.

Abstract: A counter in a non-volatile memory including at least two sub-counters, each counting with a different modulo, an increment of the counter being transferred on a single one of the sub-counters and the sub-counters being incremented sequentially.

Abstract: A counter in a non-volatile memory including at least two sub-counters, each counting with a different modulo, an increment of the counter being transferred on a single one of the sub-counters and the sub-counters being incremented sequentially.

Abstract: According to one embodiment, S (S is an integer equal to or larger than two) number of sub counters each count S number of clocks of different frequencies, and a clock switching unit is provided for each sub counter and starts a counting operation of a sub counter of a next stage after finishing a counting operation in a sub counter of a local stage.

Abstract: A method for maintaining flow control in a buffer memory coupled to a storage controller is provided. The storage controller includes, first and second counters that are used to monitor when data is read from a buffer memory and when data is transferred from the buffer memory to the host. The method includes, incrementing first and second counter values when data is placed in the buffer memory; decrementing a first counter value when data is read from the buffer memory; and decrementing the second counter value when data is sent to a host. The method further includes, pausing a first channel logic between a transport module and a storage disk when there is no data in the buffer memory; and pausing a second channel logic between a disk and the buffer if there is no space in the buffer memory.

Abstract: A system including wireless tags that transmit information from fixed locations to nearby wireless tag readers possessed by moving persons also includes a wireless tag status inference apparatus to which the wireless tag readers send identifying information received from the wireless tags. The wireless tag status inference apparatus logs the information received from the wireless tag readers, and compares the logged information with a stored list of installed wireless tags to identify suspected inoperable wireless tags. Wireless tags requiring replacement or repair can thereby be identified promptly and inexpensively, without the need to dispatch personnel on periodic inspection tours of all areas in which the wireless tags are installed.

Abstract: A system for monitoring a large number of simultaneous events implements a hybrid counter array device having a first counter portion comprising counter devices, each counter device for receiving signals representing occurrences of events from an event source and providing a first count value corresponding to a lower order bits of the hybrid counter array. A second counter portion comprises a memory array device having addressable memory locations in correspondence with the counter devices, each addressable memory location for storing a second count value representing higher order bits. A control device monitors each of the counter devices and initiates updating a value of a corresponding second count value stored at the corresponding addressable memory location. The system includes interrupt pre-indication for providing fast interrupt trigger to a processor device when a count value related to an event equals a threshold value.

Abstract: Design techniques for a low-power asynchronous counter. In an exemplary embodiment, the clock inputs and signal outputs of a plurality of flip-flops are serially concatenated to implement an asynchronous counting mechanism. The signal outputs of the plurality of flip-flops are sampled by successively delayed versions of a reference signal. Further design techniques for generating successively delayed versions of the reference signal are disclosed. In an exemplary embodiment, the asynchronous counting techniques may be utilized in a high-speed counter for a digital-phase locked loop (DPLL).

Abstract: A hybrid counter array device for counting events with interrupt indication includes a first counter portion comprising N counter devices, each for counting signals representing event occurrences and providing a first count value representing lower order bits. An overflow bit device associated with each respective counter device is additionally set in response to an overflow condition. The hybrid counter array includes a second counter portion comprising a memory array device having N addressable memory locations in correspondence with the N counter devices, each addressable memory location for storing a second count value representing higher order bits. An operatively coupled control device monitors each associated overflow bit device and initiates incrementing a second count value stored at a corresponding memory location in response to a respective overflow bit being set.

Abstract: A system that includes a controller for enabling an enumeration operation. The enumeration operation is performed by a controller (110) and logic elements (120) in a system, such that each logic element in the system assigns itself a unique identifier. Each logic element can then be controlled by another source or have a means to communicate with other logic elements in the system. The unique identifier enables greater system flexibility, thereby reducing cost and improving efficiency.

Abstract: A hybrid counter array device for counting events. The hybrid counter array includes a first counter portion comprising N counter devices, each counter device for receiving signals representing occurrences of events from an event source and providing a first count value corresponding to a lower order bits of the hybrid counter array. The hybrid counter array includes a second counter portion comprising a memory array device having N addressable memory locations in correspondence with the N counter devices, each addressable memory location for storing a second count value representing higher order bits of the hybrid counter array. A control device monitors each of the N counter devices of the first counter portion and initiates updating a value of a corresponding second count value stored at the corresponding addressable memory location in the second counter portion. Thus, a combination of the first and second count values provide an instantaneous measure of number of events received.

Abstract: A hybrid counter array device for counting events. The hybrid counter array includes a first counter portion comprising N counter devices, each counter device for receiving signals representing occurrences of events from an event source and providing a first count value corresponding to a lower order bits of the hybrid counter array. The hybrid counter array includes a second counter portion comprising a memory array device having N addressable memory locations in correspondence with the N counter devices, each addressable memory location for storing a second count value representing higher order bits of the hybrid counter array. A control device monitors each of the N counter devices of the first counter portion and initiates updating a value of a corresponding second count value stored at the corresponding addressable memory location in the second counter portion. Thus, a combination of the first and second count values provide an instantaneous measure of number of events received.

Abstract: A system for monitoring a large number of simultaneous events implements a hybrid counter array device having a first counter portion comprising counter devices, each counter device for receiving signals representing occurrences of events from an event source and providing a first count value corresponding to a lower order bits of the hybrid counter array. A second counter portion comprises a memory array device having addressable memory locations in correspondence with the counter devices, each addressable memory location for storing a second count value representing higher order bits. A control device monitors each of the counter devices and initiates updating a value of a corresponding second count value stored at the corresponding addressable memory location. The system includes interrupt pre-indication for providing fast interrupt trigger to a processor device when a count value related to an event equals a threshold value.

Abstract: A hybrid counter array device for counting events with interrupt indication includes a first counter portion comprising N counter devices, each for counting signals representing event occurrences and providing a first count value representing lower order bits. An overflow bit device associated with each respective counter device is additionally set in response to an overflow condition. The hybrid counter array includes a second counter portion comprising a memory array device having N addressable memory locations in correspondence with the N counter devices, each addressable memory location for storing a second count value representing higher order bits. An operatively coupled control device monitors each associated overflow bit device and initiates incrementing a second count value stored at a corresponding memory location in response to a respective overflow bit being set.

Abstract: In a method for operating a PLL frequency synthesis circuit, the circuit is in an active state and synthesizes a first output frequency during a first data transmission period. The circuit is likewise active and synthesizes a second, different output frequency during a later, second data transmission period. The PLL frequency synthesis circuit is first reprogrammed to an intermediate frequency, and is controlled from there to the second output frequency, in an intermediate time period.

Abstract: A system and method for performing counting operations for a plurality of components is disclosed. A memory stores a plurality of counts from different components. The memory is coupled to a counter and the plurality of counts are accessible to the adder for adding addends to the plurality of counts. A count engine controls the adding of the addends to the plurality of counts.

Abstract: An apparatus comprises an edge detector, a memory and a pulse-input engine. The edge detector is configured to receive an input signal and a counter signal. The edge detector is further configured to send a set of time values based on the input signal and the counter signal. Each time value from the set of time values is uniquely associated with a detected edge transition from the input signal. The memory is coupled to the edge detector. The memory is configured to receive from the edge detector the set of time values. The memory is configured to store the set of time values. The pulse-input engine is coupled to the memory. The pulse-input engine is configured to measure a set of pulse-to-pulse delays based on the set of the time values stored in the memory.

Abstract: A measurement system and method for determining a revolution rate of a rotating gear is described. Such a rotating gear can be, for example, a turbine or compressor. The described measurement system and method, for example, can perform highly accurate measurements and can be a fault tolerant system providing high reliability. In one embodiment, an apparatus comprises an edge detector, a memory and a pulse-input engine. The edge detector is configured to receive an input signal and a counter signal. The edge detector is further configured to send a set of time values based on the input signal and the counter signal. The pulse-input engine is configured to measure a set of pulse-to-pulse delays based on the set of time values stored in the memory.

Abstract: In a counter readout control apparatus comprising a plurality of counters, in which an upper-order counter performs a counting operation upon receiving a carry from a lower-order counter, this apparatus further comprising, a first means for resetting each flag storing memory in which a carry of each counter, with an exception of an uppermost-order counter, is stored (Step S21), a second means for sequentially reading out the plurality of counters from an upper-order counter to a lower-order counter (Step S22 to S25), a third means for, after reading each counter value by means of the second means, testing as to whether the carry is set or not in the flag storing memory (Step S26 to S29), and a fourth means for, in the case in which the carry is set in the flag storing memory, resetting the flag storing memory having the carry (Step S27A, S28A, S29A) and performing a re-read operation only of counters having an order higher than an order of a counter which has been changed due to a reception of the carry (Step

Abstract: Method and device to update a data count in a data transfer operation in which a data counter generates an intermediate count value in accordance with a first amount of data to be transferred to a storage media; and an augmenter augments the intermediate count value by a specified count value in accordance with data to be transferred to the storage media in addition to the first amount of data, wherein the updated count value is loaded into the data counter such that the intermediate count value becomes equal to the updated count value during the data transfer operation.

Abstract: The present invention is embodied in a system and method for using cascaded counters with a programmable branch and one or more event clocks that together provide the capability to generate clock pulses at high speed. Further, the programmable counter of the present invention is capable of generating a precise number of clock pulses within a very wide range of numbers.

Abstract: A method and apparatus monitor the performance of a DDS loop connecting an information transmitter to an information receiver. The information transmitter is typically at a customer premises while the receiver is typically an OCU at the receiving local office. The DDS loop uses an alternate mark inversion communications protocol and the monitoring method and apparatus feature circuitry for determining a current imbalance on the DDS loop. The numbers of positive and negative pulses on the line are individually counted and if the count of the two counters used deviates either positively or negatively from each other by specified amounts, an error event is declared. If the error events meet a statistical timing criterion, a channel error is declared and appropriate steps are undertaken to prevent signals coming from the channel from interfering with other signals available at the local office.

Abstract: A counter circuit includes Johnson-type counters of m stages, each counter including a plurality of flip-flops connected in a cascade connection, each flip-flop receiving a clock signal at a respective clock input end. In the constitution, signals at respective output ends of flip-flops in a (k-1)-th stage counter are simultaneously input to respective clock input ends of flip-flops in each counter of a k-th stage and more. As a result, it is possible to obtain a signal having an arbitrary ratio of frequency division with high speed, while relatively simplifying the circuit constitution.

Abstract: A method and a system for counting irregularly shaped articles that are being moved along a path into and out of a machine. A microprocessor is responsive to three external devices with the first device being located at the input stage of the machine and detecting the leading and the trailing edges of the articles being moved into the machine and respectively generating start and stop events to the microprocessor. The second device is a distance sensing means used to determine the length of each of the articles being moved. The third device detects the movement of the articles in their formed state, such as a box, out of the machine. The microprocessor in response to the first occurring start event initiates the counting of the incremental changes from the distance sensing means and terminates the counting in response to the first occurring stop event.

Abstract: A device for selectively recording charges for copies made on a copying machine by way of two or more accounting means connected at the same time via the device to the copying machine, comprising means for coupling the device to the copying machine, a plurality of connection points each one of which is connectable separately to a different accounting means and control means which selectively activates one of the accounting means for recording of the charges and the method of accomplishing the recording of such charges.

Abstract: A dual-edge frequency counter and method for minimizing the effects of duty cycle modulation. In its simplest form, a dual-edge counter (50) includes a first counter (52) that accumulates reference clock pulses between successive rising edges of an input signal. An input signal is also applied to an inverter (54), which inverts the square wave signal prior to applying it to a second counter (56) that also accumulates reference clock cycles between successive rising edges of the inverted sensor signal. A summation junction (60) totals the accumulated counts from the first and second counters so that they can be averaged by a divider (62), which divides the total count by two. The technique is also employed in connection with a frequency counter that includes an integer counter (72) for totaling the number of cycles of the sensor signal occurring during a sample time defined by successive gate signals.

Abstract: A counter comprising n one-bit cells receiving a clock signal (CK0) having a frequency f to be counted and a read transfer order (TO). The lower rank p cells operate at the frequency f and the n-p higher rank cells at a frequency f/2.sup.p. The lower rank p cells (51-53) directly receive the clock signal (CK0) at frequency f and, if necessary, the transfer order (TO) synchronized in correspondence with CK0. The higher rank n-p cells receive as a clock signal at frequency f/2.sup.p, a signal (CK1) delayed by at least two periods of said clock signal CK0 and at the most by (2p-2) pulses CK0 with respect to the counting signal of the highest rank cell among the lower rank p cells.

Abstract: An electronic equipment has a central processing unit (CPU), a first memory accessable by the CPU, a first setting circuit for holding a signal representative of a rated access time of the first memory and a removable auxiliary memory which includes a second memory accessable by the CPU and a second setting circuit for holding a signal representative of a rated access time of the second memory.

Abstract: A unique timing system is provided which allows for a user to program timing events with variable periods and edges from a fixed frequency clock, and having resolution greater than that of the fixed reference frequency. Delay elements, which are inherently expensive, inaccurate, and require repeated calibration, are minimized.

Abstract: Constant-percent break interval pulse correctors insure that the break interval of a dial pulse subsists for a substantially constant percentage of the total pulse interval; i.e., break interval plus make interval. The constant-percent break interval pulse correction of the first pulse in a string of pulses is realized by employing an up/down counter which is controlled to count up at a first clock rate for a first predetermined interval from the beginning of the dial pulse, then to count down at a second clock rate for a second interval from the end of the first interval to the beginning of a subsequent dial pulse and then to count down at a third clock rate until a predetermined count is reached, e.g., zero. The second clock rate is the difference between the third and first clock rates. In one embodiment, proper correction of the last dial pulse in a string of dial pulses is realized by employing a plurality of such up/down counters.

Abstract: An adder circuit is described for producing signals representative of the sum of large numbers of block-synchronized digital signals each of which may have any value within the range of quantizing levels represented. The adder circuit includes one or more binary counters coupled to count bits of the input signal having a particular significance. Counting takes place during an active interval such as a television field interval, and the counters are reset after each counting interval. The counter outputs are latched either before or after processing by addition of other counter outputs. The latched signal represents the sum of the values of the words in one sync block.

Abstract: An n stage array of gas discharge chambers is divided into m groups of y stages each. Priming arrangements are provided whereby serial readout of the stages in each group can be accomplished simultaneously thereby increasing the speed of readout.

Abstract: A method of sampling accurately the instantaneous content of a high speed counter without interrupting the counting process is provided. The method is applicable even when the higher order digits of the counter are constructed by slower switching circuits configured in either a synchronous or ripple-through arrangement. The switching and carry propagation times of these higher order counters need not be shorter than the time between successive events being counted. Sampling of the contents may be made repeatedly in the interim without affecting the totality of the final count.

Abstract: A system for converting the frequency of a pulse train to a binary number includes an output counter which converts the pulse train to the binary number. Sampling time periods are applied as pulses to a comparator through another counter. The number of desired sampling periods is set into the comparator. The comparator enables the counter during the sampling time periods and inhibits the output counter on the termination of the total sampling time periods. The output of the output counter, therefore, is a binary representation of the frequency of the incoming pulse train during the total sampling time period.

Abstract: A majority vote circuit determines when the majority of a group of signaling channels is properly conveying a common message in conjunction with a status signal individual to each channel. Respective status and message signals from each channel are scanned in pairs and in sequence. The number of valid message and status signals are accumulated in separate counters. A comparison circuit triggered by the completion of a scanning sequence matches counter outputs stage by stage to determine whether or not the count level in the message signal counter exceeds by one-half the count level in the status signal counter as an indication that a majority of a variable majority of the working channels conveys the same message signal.

Abstract: A system for reading out the contents of multiple counters onto a common bus comprising a plurality of synchronous binary counters arranged in a ring with each counter having N corresponding stages each having an output terminal on which appears the contents of the stage, an input terminal, and a clock pulse input terminal, with each stage responsive to a clock pulse supplied to its clock input terminal to transfer the signal logic level on its input terminal to its output terminal and with the output terminals of the stages of a given counter comprising the common bus. Also provided is a clock pulse source for supplying clock pulses to all of the clock input terminals and a switching signal source for generating a switching pulse. A switch associated with each stage is responsive to the switching pulse to connect the output terminal of each stage to the input terminal of the corresponding stage of the next adjacent counter in the ring of counters.

Abstract: 1. Apparatus for producing multiple combinations of parallel output binary signals for controlling an anti-jam or other form of telegraphy system comprising four parallel feedback shift registers, a pair of serial to parallel converters, each having an input terminal, means for combining the output signals of said shift registers for producing two separate serial signals, means for coupling one of said serial signals to the input terminal of one of said converters, means for coupling the other of said serial signals to said input terminal of the other of said converters and means for changing the output signal of one of said converters when said separate signals are identical for a predetermined number of binary digits, said feedback shift registers having pluralities of separate stages and a feedback mixer having input terminals connected to the last and certain other three of said stages, and an output terminal connected to the first of said stages.

Abstract: A logical circuit which is capable of serving not only as a shift register but also as counter, comprises a cascade-connection of flip-flops of the same number as the number of bits required. The flip-flops have an input connected to a logical gate group composed of gates which are opened and closed by a shift signal and a count signal. The logical circuit does not require that a flip-flop be included for each shift register part and counter part for each bit, but only requires one flip-flop to perform both the count and shift function. The logical circuit is capable of performing an independent operation of a shift register, an independent operation of a counter and a compound operation of inputting data in a serial fashion for initialization and outputting counted data in a serial fashion.