Abstract: A first device provides a repetitive count of time. A second device indicates in each successive count of time by the first device during the processing apparatus operation whether the processing apparatus has processed data for at least a first particular percentage of time in each such successive time count. A third device indicates in each successive count of time by the first device during the processing apparatus operation whether the processing apparatus has processed data for at least a second particular percentage of time in each such successive time count where the second particular time percentage is less than the first particular time percentage. A power supply provides power to the processing apparatus during the time that the apparatus is processing data.

Abstract: A coincidence signal is output when coincidence of a timer counter with the set value of a comparison register is detected by a coincidence detecting circuit and the coincidence signal is input to the external CPU as an interruption signal to execute a CPU to start an interruption routine. In the interruption routine, a reverse enable flag is set, a flag indicating permission to reverse an output signal when the value of a key counter is larger than the value of a buzzer counter and a reverse enable flag is set, a flag indicating prohibition of reversing the output signal when the value of the key counter is smaller than that of the buzzer counter.

Abstract: A counting system with a dynamic maximum count includes a counter, match logic, and a maximum count controller. The counter has a present count register, a clock (or event indicator) event input, and a reset input. The maximum count controller can be programmed with an adjustable maximum count stored in a maximum count register. The match logic includes a count-wide AND gate fed by NAND gates. Each NAND gate has an inverted input coupled to a respective bit position of the present count register and an uninverted input coupled to a respective bit position of the maximum count register. The function of the match logic is to indicate a match whenever the present count has a 1 at every bit position that the maximum count has a 1, irrespective of the present count values at bit positions at which the maximum count has 0s. Thus, imperfect matches are provided for. The values of the imperfect matches always exceed the values of perfect matches, so they are not usually encountered.

Abstract: An apparatus for detecting the abnormality of a clock in a microcomputer used for a motor vehicle includes a reference clock generator for generating a reference clock signal required for operation of the microcomputer, a pulse signal generator for generating a pulse signal of a constant period based on an instruction signal from the microcomputer, a comparator for comparing the pulse signal from the pulse signal generator and the reference clock signal from the reference clock generator and producing a comparison signal based on the result of comparison, and a determining circuit for determining, based on the comparison signal from the comparator, whether or not the reference clock signal is normal. An indicator is enabled only when the reference clock signal is in the abnormal state. The abnormality of the reference clock can be detected without requiring a separate oscillator used for generating an additional clock signal for comparison with the reference clock signal.

Abstract: A method and apparatus for synchronizing clock signals on first and second logic blocks connected via an asynchronous bus, wherein the second logic block includes a clock signal generator. The method comprises causing the clock signal on the first logic block to increment a first count; causing the clock signal on the second logic block to increment a second count; comparing the first and second counts; and adjusting the clock signal on the second logic block in response to the result of the comparison to synchronize the two clock signals, wherein the transfer of information between the logic blocks is carried out via the asynchronous bus.

Abstract: A clock divider circuit and a system using the same. The clock divider circuit has a clock input coupled to receive an input clock signal having an input clock frequency. Clock division logic generates an output clock signal having a fifty percent duty cycle and an output clock frequency which is an odd fraction of the input clock frequency. The clock division logic generates both the rising and the falling clock edges of the output clock signal from the input clock signal. The system disclosed includes a processor operating at a first frequency and a memory circuit coupled to exchange data with the processor. The processor includes a clock division circuit coupled to receive a first clock signal and to generate a second clock signal at a second frequency which is an odd fraction of the first frequency. The processor also includes an input/output buffer coupled to exchange data with the memory circuit.

Abstract: A method of accumulating and maintaining the accumulated data comprises steps of maintaining an intermediate count in a first memory device (12), reading a plurality of count values from a second memory device (14), determining a greatest count value of a subset of the plurality of count values which satisfy at least one criterion, and determining an updated count based upon the intermediate count and the greatest count value. The at least one criterion includes a criterion that the greatest count value differs from a second greatest count value of the subset of the plurality of count values by at most a predetermined difference greater than one. A system and a device to perform the method are detailed.

Abstract: A programmable clock circuit generates a real time clock value, which is incremented in response to a real time clock increment signal. The real time clock increment signal is generated after a selected number of ticks of a system clock signal, with the number of ticks being determined by whether it is operating in a normal mode or an error compensation mode. In the normal mode, the real time clock increment signal is generated after a selected number of ticks of the system clock signal, which results in an increasing cumulative timing error. In the error compensation mode, the real time clock increment signal will be generated after a number of ticks of the system clock signal selected so as to reduce this cumulative error. The programmable clock circuit keeps track of the cumulative error in the real time clock signal while operating in the normal mode.

Abstract: A low cost and easily implemented apparatus and method for synchronizing serially connected clock circuits is ideally suited to audio applications. The circuit takes data from a bitstream clock source and from the local source and counts the number of pulses received from each. A desired clock count is calculated based as a multiple of the ratio of the bitstream clock source frequency to the local clock signal frequency. Based on the samples received from the bitstream clock relative to the local clock at a later point in time, samples are either repeated or dropped to correct any error in the bitstream signal.

Abstract: A detector circuit for detecting abnormalities in the oscillation frequency of a clock signal, includes a counter and a comparator. The counter is supplied with a reference clock signal, and counts the number of pulses of the reference clock signal to output a signal indicative of the count value. In response to the clock signal, the counter clears the count value. The comparator compares the count value of the counter with a specified value stored in its register, and generates a detection signal indicating whether the frequency of the clock signal is within expected limits, based on the comparison result.

Abstract: A method and apparatus monitor the performance of a DDS loop connecting an information transmitter to an information receiver. The information transmitter is typically at a customer premises while the receiver is typically an OCU at the receiving local office. The DDS loop uses an alternate mark inversion communications protocol and the monitoring method and apparatus feature circuitry for determining a current imbalance on the DDS loop. The numbers of positive and negative pulses on the line are individually counted and if the count of the two counters used deviates either positively or negatively from each other by specified amounts, an error event is declared. If the error events meet a statistical timing criterion, a channel error is declared and appropriate steps are undertaken to prevent signals coming from the channel from interfering with other signals available at the local office.

Abstract: A frequency converter is provided of which a frequency-dividing ratio is arbitrarily altered and retained after a power is turned off. The frequency converter has a programmable counter which outputs a signal having a desired frequency, a non-volatile memory for storing data for setting the frequency-dividing ratio and a control unit for controlling a writing operation of data stored into the non-volatile memory. The programmable counter, the non-volatile memory and the control unit are accommodated in a single package. The frequency converter may comprise a resonator and an oscillating circuit within the package so that the frequency converter can be treated as a single frequency generator such as a quartz-crystal oscillator.

Abstract: A DS3 level access, monitor and test system including a digital comparator for a telephone network. A high speed bit-for-bit compare is interfaced to a protect path to provide 1:1 fault protection in the system of the present invention. Full time performance monitoring on DS1 and DS3 signals is performed by a shared resource. The system of the present invention provides an integrated approach to synchronization measurement and relative synchronization.

Abstract: A signal disconnection detection apparatus includes a first counter, a first comparator, and a detector. The first counter is reset by a pulse signal received every predetermined period of a clock signal, and counts a clock signal transmitted together with data. The first comparator compares a count value of the first counter with a set value larger than the number of clock signals included in one period of the pulse signal, and stops an operation of the first counter when the count value of the first counter exceeds the set value. The detector detects that the count value of the first counter does not continuously change within a predetermined period of time to output a signal disconnection detection signal of at least one of the clock signal and the pulse signal.

Abstract: A control circuit is provided which enables the main CPU 23 to access a memory space of the sub CPU 1 by means of the test mode control register 4 which can be controlled via the main CPU bus 10. Also a control circuit is provided to branch into a break routine by comparing the value of the program counter 5 of the sub CPU 1 and the value set in the break vector register 7. Further, a control circuit which enables it to reset the sub CPU 1, to branch according to a test vector and to make break branch under the control of the main CPU 23 is provided, thereby making it easy to incorporate the sub CPU 1 on-chip in the conventional single CPU constitution. Thus testing environment and debugging environment for the sub CPU 1 is provided in the microcomputer having a plurality of CPUs on a single chip without connecting the exclusive test terminal of the sub CPU 1 or the sub CPU bus 28 with the outside.

Abstract: A sector pulse generating apparatus for multiple zone recording includes only first and second counters. The first counter counts reference clock pulses and outputs a present position signal. The second counter is incremented in response to a increment signal and outputs a next sector number signal. A first register stores the sector length of a zone in which a head is located. A multiplier outputs a next sector position signal representative of a multiplication of the next sector number and the sector length. A first comparator compares the magnitude of the present position and the next sector position. When the present position and the next sector position match, a sector pulse generating device generates a sector pulse and a first increment device outputs the increment signal.

Abstract: A low cost and easily implemented apparatus and method for synchronizing serially connected clock circuits is ideally suited to audio applications. The circuit takes data from a bitstream clock source and from the local source and counts the number of pulses received from each. A desired clock count is calculated based as a multiple of the ratio of the bitstream clock source frequency to the local clock signal frequency. Based on the samples received from the bitstream clock relative to the local clock at a late point in time, samples are either repeated or dropped to correct any error in the bitstream signal.

Abstract: A pulse counter circuit has an invertor which inverts a pulse signal input thereto to form an inverted signal. One of the pulse signal and the inverted signal is selected in response to a selecting signal, and the selected signal is delivered as an output signal. Changeover of a signal to be selected between the pulse signal and the inverted signal is effected at timing of a change in level of the pulse signal. A counter counts pulses of the output signal. A pulse signal changeover circuit selects one of a pulse signal and an inverted signal obtained by inverting the pulse signal, in response to a selecting signal, and the selected signal is delivered as an output signal. The pulse signal is masked by being held at a predetermined level within a predetermined time period, and the inverted signal is masked by being held at the predetermined level within the predetermined time period.

Abstract: Difference flag logic suitable for use in a FIFO memory is modified to quickly generate FIFO flag status through the use of programmable, resettable counters which eliminate the need for subtractor circuitry. A comparator is used to compare a value from a read counter with a value from a write counter. The subtractor function is replaced by offsetting the read count from the write count by a value equal to the desired FIFO flag value. Offset of the read count from the write count is accomplished by utilizing counters which provide programmable resettability. Use of programmable, resettable counters allows FIFO flag values to be chosen and implemented very easily. For instance, it is possible for a user to change from an almost full FIFO flag to a half full FIFO flag without changing any hardware at all. The counters are simply programmed and reset accordingly.

Abstract: An input clock delay circuit includes an up counter for estimating the approximate number of internal clock cycles that occur during one cycle of the input clock signal and another up counter for determining the portion of each cycle of the input clock signal that is high. A clock manipulation circuit receives each counter's value, and may be set to perform a fixed transform on the input clock signal, such as clock delay/advance, duty cycle shifting, and frequency multiplication/division. The clock manipulation circuit output values are loaded into two down counters that are also clocked by the internal clock. On the rising edge of the input clock signal, the first down counter starts decrementing until the counter reaches zero, indicating that the desired delay interval has passed, at which point the delayed output clock signal is taken high. The second down counter then starts decrementing for an interval that is equal to the desired duty cycle of the output clock signal.

Abstract: A pulse width discriminating circuit comprises an edge detecting circuit receiving an input signal for generating a detection signal when the input signal rises up, first to third counters each cleared by the detection signal and counting a different count clock, a capture register responding to the detection signal to store a count value of the first counter, an arithmetic operation circuit for multiplying the stored value in the capture register with a predetermined constant number, and a compare register storing the result of the multiplication operation performed in the arithmetic operation circuit. First to third comparators are provided each comparing the stored value of the compare register with a count value of a corresponding one counter of the first to third counters for generating a coincidence signal, and each of a plurality of latch circuits responds to the coincidence signal of a corresponding comparator of the first to third comparators to latch a level of the input signal.

Abstract: In an apparatus for testing a counter circuit, a test pattern is used to drive the counter circuit to obtain an output pattern. The output pattern is compared with an expected pattern in synchronization with the test pattern, thereby determining whether or not the counter circuit is normal. A phase between the output pattern and the expected pattern is initially adjusted by the testing apparatus.

Abstract: An apparatus for detecting frequency of an input signal by counting the pulses of a reference signal of a predetermined frequency within one cycle of the input signal is disclosed. The apparatus includes a first and a second latch for latching the number of pulses of the reference signal for two consecutive periods of the input signal. In response to the reference signal, a comparator is used to compare the output value of the first and the second latch. When they are different, a flip-flop generates an interrupt signal to a microprocessor. The microprocessor reads the updated number of pulses and generates an updated frequency value based on the updated number of pulses and the predetermined frequency of the reference signal.

Abstract: A counter system having associated counter error detection circuitry that utilizes the current parity, the previous parity, and a predicted parity for evaluating counter operation is described. In successive count cycles, a predicted parity is utilized, during the next subsequent count cycle is stored in flip-flop as the current parity, and in the next subsequent count cycle is stored a second flip-flop as a previous parity. Circuit are described for performing parity check and parity prediction functions. The previous parity, current parity and predicted parity will not be alike for any binary counter that operates properly. Circuity is described that holds and compares the parity of the Count, the current parity, and the previous parity, during each counter advance cycle and to provide an error signal when the counter is detected to be stuck.

Abstract: A plurality of processes share a single set of non-resettable counters which are sampled periodically. Each process maintains a list of counter relationships unique to its own process and compares at each sample time the current sampled counter values with a selected function of previously received counter values for each relationship in its list and establishes a counter reset value which is a selected function of the current sampled value when the previously selected function is satisfied.

Abstract: A comparator is provided in the counter circuit to compare the counted value of clocks by a counter with the value of a register in which a target changing value of a comparison register which sets a value to be compared with the counted value of the counter is set. The value of the register is set in the comparison register when the counted value of the counter does not reach the set value of the register, whereas the value of the register is not set in the comparison register if the counted value does not reach the set value of the register, but the value of the comparison register is turned changeable at the desired timing while the counted value of the counter is being compared with the set value of the comparison register.

Abstract: A controller for asynchronous configurable FIFO (first-in-first-out) memory includes, in addition to two binary counters for the read pointer and write pointer, two Gray code counters for determining whether the FIFO is full or empty by a comparison of the read pointer and write pointer values expressed in Gray code. The Gray code counters avoid the problem of asynchronicity of read and write signals. The Gray code counters determine if the FIFO is full or empty depending on whether the pointer values match (indicating empty) or differ in accordance with particular Gray code patterns (indicating full). The Gray code counters each have an extra bit which allows determination of the full or empty condition from a straightforward comparison of the read pointer and write pointer values, while the Gray code eliminates the problem of multiple bit transition providing an incorrect indication of the pointer location.

Abstract: A programmable clock divider in which a system reference clock signal is divided by a programmed integer value. A storage register stores a value equal to the desired divisor minus two. A stored value of zero results in a divide by two. The stored value is loaded into a compare register and a counter is implemented to count reference clock signals. The compare register value and the counter value are compared by a comparator logic circuit. When the two values are equal, a flip-flop is toggled to switch the prescale clock value output. The flip-flop control logic includes circuitry for ensuring that odd divides exhibit an output clock frequency having a 50/50 duty cycle by controlling the flip-flop toggle to coincide with system clock edges. The flip-flop control logic also controls the timing for loading and resetting the compare and counter logic, respectively.

Abstract: A data coincidence detecting circuit including a register for receiving n-bit data, a counter for counting up until 2.sup.n to compare the n-bit data with it, a comparator for comparing the outputs of the register and the outputs of the counter, respectively to generate a coincidence detecting signal, a mask portion connected to the output of the comparator for masking the period from a time point when the n-bit data is input to a time point when the input of data ends, and a logic circuit for logically adding the output of the mask portion and the output of the comparator to output the result.

Abstract: A synthesized jitter generator employing a novel digital architecture is provided. The apparatus provides period synthesis and controlled sinusoidal and non-sinusoidal jitter modulation functions of a square wave provided at its output. The architecture consists of a coupling of an N+M bit digital accumulator and an N bit synchronous counter to an N bit magnitude compare circuit. The output of the magnitude compare strobes the accumulator when the two inputs are equal in magnitude causing the accumulator to increment synchronously. The output of the magnitude compare is also a digital waveform whose average period is precisely defined by the input word to the accumulator.

Abstract: A built in self test circuit for testing a phase lock loop (11). The built in self test circuitry comprises a pulse circuit (13), an And gate (19), a counter circuit (23), and an output multiplexer (24). The phase lock loop (11) receives a reference signal and generates an output signal. The pulse circuit (13) receives the reference signal and generates a pulse having a duration some multiple of the output signal of the phase lock loop. The And gate (19) receives the pulse output by pulse circuit (13) and the output signal of the phase lock loop (11) generating a string of pulses having the frequency of the output signal of the phase lock loop (11) for the duration of the pulse output by the pulse circuit (13). The counter circuit (23) receives the string of pulses and generates a count of the pulses. The count is compared to an expected count to determine the accuracy of the phase lock loop (11).

Abstract: A data compressor generates codewords representative of the location and length of a string match between an input data stream and a CAM array vocabulary table. A data decompressor looks up the codewords for a string match in its vocabulary table. The CAM array is arranged in a serpentine configuration to reduce track layout. A column priority encoder reverses the priority of alternate rows to maintain the logical flow through the CAM array. The CAM array uses a flipflop with a common control circuit to transfer data through the flipflop. When the data compressor is reset, the CAM array may locate matches in the unused portion which are interpreted as the reset character. A barrel shifter in the data compressor converts variable length codewords into fixed length for transmission. A barrel shifter in the data decompressor converts fixed length codewords back into variable length for decoding into the vocabulary table.

Abstract: A circuit for calculating a DC value for use in a code conversion apparatus of a recording and reproducing system includes a first storing element, second storing element, parallel to serial convertor, selecting circuit and a DC value calculating circuit.

Abstract: A programmable clock divider in which a system reference clock signal is divided by a programmed integer value. A storage register stores a value equal to the desired divisor minus two. A stored value of zero results in a divide by two. The stored value is loaded into a compare register and a counter is implemented to count reference clock signals. The compare register value and the counter value are compared by a comparator logic circuit. When the two values are equal, a flip-flop is toggled to switch the prescale clock value output, The flip-flop control logic includes circuitry for ensuring that odd divides exhibit an output clock frequency having a 50/50 duty cycle by controlling the flip-flop toggle to coincide with system clock edges. The flip-flop control logic also controls the timing for loading and resetting the compare and counter logic, respectively.

Abstract: The invention provides a pulse generating circuit including a single timer or counter which conducts both a event base count and a subsequent time base count according to clock signals about the event and time base counts, any one of which is selected by a selector. A pulse signal is generated from a RS flip-flop circuit. When the time base count follows the event base count, during the event base count, the output signal from the flip-flop is a 0 signal. During the time base count, the output signal from the flip-flop is a 1 signal. The event base count defines a delay of a pulse generated from RS flip-flop circuit and the time base count defines a width of the pulse.

Abstract: A break address detecting circuit sets a breakpoint in debugging a program for microprocessor, a signal processor, or the like. A first register holds a stop address ADstp. A first counter is initialized by a reset signal and counts up clock pulses in synchronism with a clock signal indicative of an instruction execution cycle. A selector selects a program address when the program is debugged, or selects output data from the first counter in step-by-step operation. A first comparator outputs a comparison result signal CR which is of an active level when output data from the selector and output data from the first register agree with each other. A second counter is initialized by the reset signal and counts up the comparison result signal each time the comparison result signal is of an active level. A second register holds a stop count CVstp. A second comparator outputs a break signal of an active level when output data from the second counter and output data from the second register agree with each other.

Abstract: A single chip microcomputer includes two kinds of timer circuits which receive a common clock signal. One of the timer circuits generates a first timer signal, and the other generates a second timer signal. When the first timer signal is being reset, the second timer signal is inactive.

Abstract: A phase lock loop monitors a first digital signal and generates a second digital signal operating substantially at frequency and in-phase with the first digital signal. A programmable divider latches a program integer for providing a latch integer, compares the latch integer to a constant integer, and generates a flag signal having a first state when the latch integer mismatches the constant integer and a second state when the latch integer matches the constant integer. The latch integer is decremented when the flag signal has the first state. The flag signal is delayed in response to first and second clock signals for providing the second digital signal having a frequency determined by the program integer. The first and second digital signals are applied to a lock detection circuit for providing a lock detection signal.

Abstract: A method and circuitry are provided for modularized single transition counting. A count signal is provided on a count line (436). A single transition count is modified in response to the count signal. The single transition count has a plurality of bits (418, 416) provided by at least one first module (404) and at least one second module (406). The first (404) and second (406) modules are alternately coupled in series to an input module (402) so that one (404) of the first and second modules has an input (460a, 466a) coupled to an output (420, 468) of the input module (402) and so that each additional one (406) of the first and second modules has an input (482a, 488a) coupled to an output (472a, 478a) of an associated one (404) of the second and first modules, respectively.

Abstract: A timer circuit is disclosed which includes a counter counting a clock signal, a register temporarily storing data, and a comparator comparing a count value of the counter with the data stored in the register and producing a signal when the count value of the counter reaches the value represented by the data stored in the register. Further provided in the timer circuit are detection circuit detecting the value of the data stored in the register and producing a detection signal when the register is written with data indicative of a value that is equal to an initial value of the counter and a circuit responding to the detection circuit to cause the register to change the value of the data stored therein to another value that is different from the initial value of the counter.

Abstract: A counter device having a jumping function includes a counter circuit for counting clock pulses, a circuit for setting a jump starting count, a circuit for setting the number of bits to be jumped, a detecting circuit for detecting equality/unequality between a count of the counter circuit and the Jump starting count as set, and a circuit for modifying the count of the counter circuit by the number of bits to be jumped in response to equality detection by the detecting circuit. The modifying circuit varies the count in the same direction as a direction of variation of the count provided by the counter circuit. This construction realizes a counting function which jumps a desired count or counts from a selected count.

Abstract: A pulse density modulation circuit has a counter which produces a most significant bit through a least significant bit output based on a clock input. The circuit also has a comparator with two sets of most significant bit through least significant bit inputs that produces an output based on a comparison of the two sets of inputs. The first set of comparator most significant bit through least significant bit inputs receives respectively a most significant bit through a least significant bit of an input reference signal. The second set of comparator most significant bit through least significant bit inputs receives the counter most significant bit through least significant bit output in a non-sequential bit order. The non-sequential bit order can be a bit reversed order wherein the counter most significant bit through least significant bit output are respectively connected to the comparator least significant bit through most significant bit input.

Abstract: An IC according to the present invention contains a counter, which includes a plurality of incomplete coincidence detection circuits each associated with a different one of a corresponding number of flip-flops storing respective bit data of an aimed value, each incomplete coincidence detection circuit including a first logic element for receiving a Q or Q output of said associated flip-flop and a one-bit output from a bit location of the counter corresponding to the different flip-flop, and a second logic element for receiving an output of the first logic element and the other of the Q and Q output of the different flip-flop to provide a coincidence detection signal, the detection circuit being adapted to detect a coincidence of the aimed value with the count value when all of the incomplete coincidence detection circuits output the coincidence detection signals.

Abstract: The apparatus detects a difference of frequency between a first signal having a first frequency and a second signal having a second frequency, the first and second signals being digital signals. A phase shifter shifts the first signal such that the first signal and the shifted first signal are sufficiently out of phase to keep the rising and falling edges of the two signals from occurring at the same time thereby avoiding subsequent simultaneous triggering conditions and jitter conditions between the first and second signal. A first gate samples the second signal by the shifted first signal to output a first sampled signal. A second gate samples the second signal by the first signal to output a second sampled signal. A sample gate samples the first sampled signal and the second sampled signal to generate a difference signal, the difference signal containing a difference value of the frequency difference between the first and second signal.

Abstract: To sense the presence of written data on an optical disk, the readback signal from the disk is detected, and the intervals between detected signal events are measured. That signal event occurring at an expected time delta after the preceding signal event indicates a valid data signal time delta. Those signal events occurring at an unexpected time delta after the preceding signal event indicates the readback signal to be noise. If the count of valid signal time deltas minus the unexpected time deltas attributed to noise accumulates rapidly along a given track within a given sector of the optical disk that sector is determined to be written. Provision is made for counting signal events in accordance with the specific run-length limited in use.

Abstract: A circuit configuration includes k linking cells each generating one of k output states from two of k input states. Each of the linking cells have two counters. Each of the counters have a serial data input, a serial data output, and a serial counting width input. The counters increase a counter state loaded through the data input and represent the respectively assigned input state by a value input through the counting width input. Comparators are each connected to the data outputs of two of the counters for serially comparing the two counter states with one another. Multiplexers are each connected to the data outputs of two of the counters for outputting one of the two counter states as an output state under the control of the comparator.

Abstract: A counter device having a jumping function includes a counter circuit for counting clock pulses, a circuit for setting a jump starting count, a circuit for setting the number of bits to be jumped, a detecting circuit for detecting equality/unequality between a count of the counter circuit and the jump starting count as set, and a circuit for modifying the count of the counter circuit by the number of bits to be jumped in response to equality detection by the detecting circuit. The modifying circuit varies the count in the same direction as a direction of variation of the count provided by the counter circuit. This construction realizes a counting function which jumps a desired count or counts from a selected count.

Abstract: A circuit arrangement for adapting the bit rates of two signals to each other and which comprises an elastic store (6). The useful data of a first frame-structured signal are written into this store (6) by means of a write address counter (7) and read out again by means of a read address counter (8). A phase comparator (16) is used for comparing the counts of these counters (7,8). In order to largely avoid jitter in the signal that has been read, a balancing counter (14) is provided which, on average, is stopped as often as the write address counter (7) is, but runs more smoothly than the write address counter. The means for controlling the operation of the balancing counter (14) comprise comparator circuits (12E, 12F, 12G) by means of which the operation of the frame counter (12) is monitored, an up/down counter (19) as well as various gates (11, 13, 17, 18).

Abstract: An arbitrary waveform generator is capable of producing pulse or continuous aveform signals. It utilizes an EPROM that sends out selected stored digital signals under control of a microprocessor and auxiliary equipment comprised of a clock and an address sequencer. A digital-to-analog converter receives the digital signals from the EPROM and converts them to analog signals.

Abstract: A PWM output device using time-multiplexing to create multiple time-bases from a common time-base counter and thereby supporting multiple PWM output signals capable of having different periods and duty cycles. A circulating timer shifts to provide various fundamental time-bases to each PWM module, which sets and resets its PWM output upon a proper state determined by a looping state counter. When the state counter reaches 0, it causes the circulating counter to increment and the state counter to reload. As the circulating counter shifts, it generates a plurality of values to be used as the fundamental timebases for the PWM modules. Each PWM module comprises a time-base match unit, a duty cycle control unit, and an output control unit. The time-base match unit in each individual PWM module determines when the time base produced by the circulating counter is valid by comparing its preset valid state value with the state value from the state counter.