Abstract: The present disclosure provides an image data processing device, an image data processing method and a display device. The image data processing device includes: a plurality of writing controllers corresponding to a plurality of image blocks into which an input image is divided, and each configured to obtain input data of one image block in each input image, determine a frame address of the input data stored in a memory, and transmit the input data to the memory in accordance with the determined frame address; and a plurality of reading controllers, each reading controller corresponding to one image block into which an output image is divided, and configured to determine a frame address of the output data of one image block in ach output image in the memory, and read output data from the memory in accordance with the determined frame address.

Abstract: A signal processing apparatus includes a storage processing part that performs storage processing on data represented in a second representation format, wherein, when a value of the data is positive or zero, the second representation format is identical to a representation format of two's complement, while, when the value of the data is negative, the second representation format is a representation format in which all bits other than a most significant bit indicating a sign in a two's complement representation of the data are inverted, and an operation processing part that performs operation processing on at least any one of data represented in the two's complement representation or data obtained by applying compensation processing to data represented in the second representation format.

Abstract: A data processor including: a reference signal generator to generate a reference signal, used to convert a level of an analog processing signal into digital data; a comparator to compare the processing signal with the reference signal; and a count period controller to perform a real number count operation or a complement number count operation, on the basis of the comparison result of the comparator. The count period controller independently controls the real number count operation and the complement number count operation of the counter on the basis of a predetermined criterion.

Abstract: An arithmetic counter circuit for high performance CMOS image sensors includes a plurality of flip-flops of a plurality of counter stages and a plurality of multiplexers of the plurality of counter stages being coupled to the plurality of flip-flops. Each of the plurality of multiplexers coupled to receive control signals including at least one of a toggle signal, a keep signal, a shift enable signal, or a mode signal. The control signals select the output of each of the plurality of multiplexers. Each of the plurality of flip-flops is coupled to be in one of a toggle state, a keep state, a reset state or a set state based on inputs received from the plurality of multiplexers. Other embodiments are described.

Abstract: An asynchronous counter that is capable of switching count mode includes flip-flops, and three-input single-output tri-value switches respectively provided between the adjacent pairs of the flip-flops. The tri-value switches switch among three values, namely, non-inverting outputs and inverting outputs of the flip-flops and a power supply level. Each of the tri-value switches switch among the three input signals according to two-bit control signals, and input a selected signal to a clock terminal of a subsequent flip-flop. When count mode is switched according to the control signals, a count value immediately before the mode switching is set as an initial value, and counting after the mode switching is started from the initial value.

Abstract: A method of communicating a data word via a bus includes driving the data word onto the bus in whichever one of a true polarity form and a complement polarity form that requires fewer bus lines to change state relative to a present state of each bus line, and providing an indicator signal to the bus to indicate which polarity form of the data word is driven onto the bus. The data word and the indicator signal may be received from the bus, and the polarity form of the data word is conditionally inverted in response to the indicator signal. A noise reduction system includes, for one embodiment, a sending circuit which compares each bit of a data word to be next communicated onto the bus against a corresponding bit of the present data word on the bus. If more than half the bits differ, then the next data word is inverted to form a complement next data word.

Abstract: A method is disclosed for reducing the power consumption of an electronic system, such as a wireless or cellular telephone, that has a memory and a device for accessing the memory. The method includes the steps of (a)during a first part of a memory access cycle, applying an address over a bus; (b) during a second part of the memory access cycle, transferring data to or from the memory over at least a portion of the bus; and (c) prior to the step of transferring, selectively inverting or not inverting the data so as to minimize a number of bus signal lines that are required to change state between the first part and the second part of the memory access cycle. In a preferred embodiment of the invention the bus is a multiplexed address/data bus. The method also generates a control signal that is transmitted to the bus for informing a receiving device that the data (or address) being transferred over the multiplexed address/data bus should be inverted before use.

Abstract: An asynchronous counter includes a plurality of flip-flops, cascade connected to one another, the plurality of flip-flops serially receiving successive pulse trains having varying numbers of pulses per pulse train. Switching circuitry, coupled to the plurality of flip-flops, inverts the state of each flip-flop between a first set of pulse trains and a second set of pulse trains (or first and second consecutive pulse trains) so that the counter computes a difference between the number of pulses in the first set of pulse trains and the number of pulses in the second set of pulse trains (or a difference between the number of pulses of the first pulse train and the number of the second pulse train). Initialization circuitry, coupled to the plurality of flip-flops, initializes all of the flip-flops at each predetermined even number of pulse trains.

Abstract: A controller for a first in first out (FIFO) memory comprises detector logic for detecting any difference between the number of addresses in the memory into which data is written and the number of addresses in the memory from which data is read. Comparator logic connected to the detector logic generates a request data transfer signal in response to said difference becoming greater than or equal to a threshold. Threshold select logic connected to the comparator logic is responsive to data having first and second portions being written to the memory. The threshold select logic sets the threshold to a first value when the first portion is being written and sets the threshold to a second value, greater than the first value, when the second portion is being written.

Abstract: A counter device having a jumping function includes a counter circuit for counting clock pulses, a circuit for setting a jump starting count, a circuit for setting the number of bits to be jumped, a detecting circuit for detecting equality/unequality between a count of the counter circuit and the jump starting count as set, and a circuit for modifying the count of the counter circuit by the number of bits to be jumped in response to equality detection by the detecting circuit. The modifying circuit varies the count in the same direction as a direction of variation of the count provided by the counter circuit. This construction realizes a counting function which jumps a desired count or counts from a selected count.

Abstract: A digital signal processor comprises a code converter which converts an integer coded in a Binary Two's Complement (BTC) code to an integer coded in a Sign Magnitude Binary (SMB) code and/or a code converter which converts the SMB code to the BTC code. An integer coded in the BTC code and stored in an m-bits register is converted to an integer coded in the SMB code and input to an n-bits register, by an EXCLUSIVE OR processing of the bits with the sign bits and by supplementing a logic "1" in the less significant bit next to the least significant bit of the result of the exclusive OR operation. An integer coded in the SMB code and stored in an n-bits register is converted to an integer coded in the BTC code and input to an m-bits register, by an EXCLUSIVE OR processing of m-1 bits of magnitude bits with a sign bit. The code converters have a relatively simple construction, will not output an incorrect result, and are most suitable for processing AC signals.

Abstract: An updown counter up-counts binary data stored in respective flip-flops in an up-count mode, and down-counts the binary data stored in the respective flip-flops in a down-count mode. When a command for an up-count mode is applied by an up/down control signal, the binary data stored in the respective flip-flops is converted into a complement on two after converting it into a complement on one. When a command for a down-count mode is applied by an up/down control signal, the binary data stored in the respective flip-flops is converted into a complement on one after converting it into a complement on two. The converted data is used to rewrite the data stored in the respective flip-flops.

Abstract: A threshold detection logic circuit of simple and economical design is disclosed that indicates when the difference in the number of first operations to be counted and the number of second operations to be counted is either greater than or equal to a threshold value, or less than or equal to a threshold value. The threshold detection logic circuit employs the use of an overflow bit of a counter, which has a counting range of 2.sup.N+1 for a threshold range of 2.sup.N, in order to generate a threshold interrupt signal. In addition, the disclosed threshold detection logic circuit permits the threshold value to be programmed to any desired value.

Abstract: An apparatus and method for detecting the period of a frequency signal having a period greater than a minimum period and within a period range. A clock frequency is generated such that when multiplied by the predetermined range the product is less than 2.sup.N and when multiplied by the minimum period of the product is less than 2.sup.N+M. The resulting clock frequency is multiplied by the minimum period to generate an offset number. A counter is preset with the offset number in response to a detected edge transition of the frequency signal. The counter counts at the clock frequency from a complement of the offset number to a final count at a subsequent edge transition. The final count is contained within the first N bits and is related to the period of the frequency signal.

Abstract: Apparatus is disclosed for reversing the bit order of a portion of a digital word. The apparatus contains a shifter, connected to the input through a bit reversing means, and selector means which forms an output word by selecting appropriate bits either directly from the input word or from the output of the shifter.

Abstract: A high speed, low power, multi-bit, single edge triggered, wraparound binary counter is provided which is resettable and loadable from a user-supplied address. The binary counter requires a relatively small amount of power due to the use of CMOS technology for construction of its circuitry, may be initiated at any of 2.sup.N (where N=bit count) start locations, and can be easily adapted to accommodate any desired number of counter cells. Further, it is capable of operating over wide ranges of temperatures and power supply conditions. The high speed binary counter is formed of a plurality of counter cells in which each counter cell includes a pass gate device responsive to a counter-update signal for allowing true and complement addresses to control a switching device when the counter-update signal is in the low state and for isolating the true and complement addresses from the switching device when the counter-update signal is in the high state.

Abstract: An inverter for use in a binary counter comprises a flip-flop having first and second input/output nodes respectively applied with input signals of opposite polarities, a first field effect transistor having a source-drain path connected between the first input/output node and a third node and a gate connected to receive a control clock signal, and a capacitor connected to the third node so as to hold the potential on the first input/output node when the first transistor is turned on. Further, there is provided a switch circuit connected between a supply voltage and a ground and having a first input connected to the third node, a second input connected to receive an inversion control signal, and an output connected to the first input/output node. This switch circuit is responsive to the inversion control signal so as to bring its output to a voltage condition opposite to that held in the capacitor.

Abstract: A counter for counting clock pulses and having a plurality of output bits successively numbered from a first output bit to a highest output bit. The counter includes a plurality of bistable devices, one bistable device being associated with each output bit, and each bistable device including a clock input for receiving clock pulses to be counted, and an output for providing one of the output bits and its complement. The bistable device which is associated with the first output bit toggles with the receipt of each clock pulse to be counted. The counter also includes a decode section responsive to the outputs of the plurality of bistable devices for providing decoded signals, and a select section for receiving the clock pulses to be counted and responsive to the decoded signals and the complement of the first output bit. The select section selects which of the plurality of bistable devices associated with the second and higher output bits will toggle on the receipt of the next clock pulse.

Abstract: A logic arrangement for low power integrated circuits which reduces the number of state changes at the synchronously clocked parallel outputs of the integrated circuit. Logic is included which determines the number of output lines which would normally change state when the next output word is clocked onto the output lines. Additional logic determines whether this number is greater than or equal to a predetermined number, being one-half the number of output lines for even numbers of output lines. When the number of state changes will exceed this number, the output word is complemented before being clocked onto the output lines. An extra output line is used to signal the circuitry connected to the output lines that the output states have been complemented. When the number of state changes equals the predetermined number, the output word is complemented only if the previous output word was complemented.

Abstract: A code conversion circuit comprising logic for converting an n-bit binary number having a sign bit in two's complement code to sign-magnitude code is provided where n is an integer. The logic identifies whether or not the binary number is positive or negative. Regardless of polarity, the sign bit and least significant bit are directly outputted. If the binary number is positive, all bits are outputted with unchanged logic states. If the binary number is negative, the least significant bit of the n magnitude bits which has a logic one value is identified. The remaining n magnitude bits of higher significance are inverted and outputted with the other magnitude bits.