Abstract: In a pulse phase difference coding circuit, a count unit includes a plurality of partial counters connected to each other in series so that the most significant bit of an output of the previous stage serves as an operation clock of the subsequent stage. A circulation number detecting unit includes a first latch circuit which is provided for each of the partial counters and latches an output of the partial counter according to a pulse for measurement, and a first delay circuit which treats the partial counter in the second stage or later as an object counter and delays the pulse for measurement by a total delay time in all the partial counters located at the previous stages of the object counter. The pulse for measurement is inputted into the first latch circuit which latches an output of the object counter.

Abstract: A shift register circuit and method includes: a plurality of shift registers configured to generate latch clock signals by sequentially shifting input signals according to first and second clock signals, the first and second clock signals including: periods longer than a shift register clock signal, and phases different from each other, wherein odd shift registers among the plurality of shift registers are configured to be driven by the first clock signal, and wherein even shift registers are configured to be driven by the second clock signal.

Abstract: Phase shifter circuits and methods use counters to define the positions of the output clock edges. A plurality of counters are each clocked by a count clock relatively much faster than the input clock. A first counter counts for one input clock period, and a delay value is determined based at least in part on the counted value. In some embodiments, the delay value has a maximum value that depends on the counted value. The delay value is provided to a second counter, which counts from zero to the delay value and generates a pulse one delay value after the beginning of the input clock period. A third counter running at the same clock rate generates a pulse after an additional delay. The pulses from the counters are used to provide output clock edges at predetermined times during the input clock cycle. Some circuits also perform a duty cycle correction.

Abstract: A multi-shifting shift register is adapted for outputting a selected address signal to a memory unit, and includes a control circuit for outputting a number (i) of shift signals and a timing pulse signal. One of the shift signals is at an enabled state and the other ones of the shift signals are at a disabled state during each cycle of the timing pulse signal. A multi-shifting circuit includes a number (N), which is larger than the number (i), of cascaded register units, each of which has a flip-flop that has an input end, and an output end for generating an address signal, and a selector that has the number (i) of select inputs for receiving the number (i) of the shift signals respectively from the control circuit, the number (i) of address signal inputs, and an output. The output end of the flip-flop is connected to a first one of the address signal inputs of the selector.

Abstract: A counter operated on the 2-phase clock which divides a lag time occurring in shift circuits into two parts, one being on the basis of a first clock and the other being on the basis of a second clock, the lag time in each part being independently accumulated so as to diverge the lag time, thereby speeding up the operation of the counter.

Abstract: A pulse phase difference encoding circuit provides a digital signal indicating a phase difference between a first input pulse and a second input pulse. The first input pulse is provided to and circulated in a ring signal delay circuit having a plurality of signal delay elements that are connected in series. Intermediate points between the delay elements provide delayed pulses having different delay times. Upon receiving the second input pulse, a selector selects one delay pulse provided by the delay element at which the first input pulse has arrived, and generates a digital positional signal indicating a position of the selected delay element. The number of rounds of circulation of the first input pulse in the ring signal delay circuit is separately counted. According to the number of rounds of circulation of the first pulse and the positional signal, the digital signal indicating the phase difference between the first and second input pulses is formed.

Abstract: An object of the present invention is to provide an A/D conversion device capable of compensating for quantizing errors occurring as a result of variations in operating conditions and a physical quantity detection device using this A/D conversion device.

Abstract: A digital phase detector that stores four sequential digital samples in a shift register. The contents of the shift register is evaluated at one half the clock frequency which generated the digital samples. The digital phase detectors predicts what the value should be for each of the two middle samples in the shift register. The predicted value and the actual value of each middle are used to generated a correction signal. The correction signals for the two middle samples are then added to produce a total correction signal which is to be used in controlling the phase and frequency of the voltage controlled oscillator in the phase locked loop generating the clock that controls the generation of the digital samples.

Abstract: A pulse phase difference encoding circuit provides a digital signal indicating a phase difference between a first input pulse and a second input pulse. The first input pulse is provided to and circulated in a ring signal delay circuit having a plurality of signal delay elements that are connected in series. Intermediate points between the delay elements provide delayed pulses having different delay times. Upon receiving the second input pulse, a selector selects one delay pulse provided by the delay element at which the first input pulse has arrived, and generates a digital positional signal indicating a position of the selected delay element. The number of rounds of circulation of the first input pulse in the ring signal delay circuit is separately counted. According to the number of rounds of circulation of the first pulse and the positional signal, the digital signal indicating the phase difference between the first and second input pulses is formed.

Abstract: A pulse phase difference encoding circuit provides a digital signal indicating a phase difference between a first input pulse and a second input pulse. The first input pulse is provided to and circulated in a ring signal delay circuit having a plurality of signal delay elements that are connected in series. Intermediate points between the delay elements provide delayed pulses having different delay times. Upon receiving the second input pulse, a selector selects one delay pulse provided by the delay element at which the first input pulse has arrived, and generates a digital positional signal indicating a position of the selected delay element. The number of rounds of circulation of the first input pulse in the ring signal delay circuit is separately counted. According to the number of rounds of circulation of the first pulse and the positional signal, the digital signal indicating the phase difference between the first and second input phases is formed.

Abstract: A polarotator pulse generator circuit is disclosed in which a sine-to-square converter converts a sine wave of AC power supply to a square wave, a clock synchronizer synchronizes the square ware of the sine-to-square converter with a high frequency clock and provides a loading instance control signal, a latch provides after synchronizing the data corresponding to the pulse width for the control of the polarotator with a clock being applied, a counter counts the clock with a start value determined by the data provided from the latch in accordance with an applied clock and loaded in accordance with the loading instance control signal, and a counter disable part stops the count until the next loading signal enters when a carry over occurs.

Abstract: A velocity deception apparatus utilizes a serrodynable digital phase shifter of the Schiffman type where each cell of the phase shifter is driven by an output of a multi-bit counter whose clock input in turn is driven by a voltage-to-frequency converter which has a pulse train output which responds substantially instantaneously to the analog value of a linear or second order function which produces the desired frequency translation. In practice, this performs as a velocity gate stealer which produces slowly changing false doppler frequencies.

Abstract: A system for determining the position of movable machine parts including an incremental pulse generator for generating angular-speed pulses includes a computer. At least one counting circuit via which the incremental pulse generator is connected to the computer counts the generated angular-speed pulses.

Abstract: A machine position detecting apparatus according to the invention detects the absolute position of a machine by a pulse coder or the like attached to a movable element. Whenever the movable element of the machine is stopped, a check is performed to determine whether the detected position of the movable element is accurate. This is accomplished by a counter for counting the amount of shift of an absolute position detector circuit in one revolution based on a rotational position signal, and a collator for collating contents of the counting means with contents of position memory means and checking the stored contents of the position memory means when the movable element is stopped.

Abstract: A time delay circuit for providing a delayed replica of a digital input signal including first and second counters for providing first and second count outputs offset relative to each other by a predetermined value indicative of a predetermined delay, and further including a first-in first-out (FIFO) memory for controllably storing selected values of the digital input signal together with corresponding first count output values. First comparison circuitry compares each digital input with the immediately prior digital input, and controls the FIFO memory to store (a) each digital input which is different from the immediately prior digital input, and (b) the first counter output value associated therewith.

Abstract: A method and device for evaluating signals of an incremental pulse generator for generating at least two mutually phase-shifted angular speed signals includes counting the angular speed signals only if a permissible combination of the angular speed signals is present.

Abstract: A circuit for synchronizing digital signals with alternating current includes a first counter that repetitively starts a first counting sequence at a predetermined phase point in each AC line cycle and effects the sequence at a high frequency rate thereby generating a total count during each line cycle. The total count is then divided by a dividing integer to produce a count number. A second counter repetitively starts a second counting sequence at the predetermined phase point and effects the second sequence at the high frequency rate up to the count number continuously during each line cycle. A decoder responsive to the second counter produces a digital output signal at one or more predetermined points in preselected second counting sequences during each line cycle.

Abstract: A phase detection circuit for detecting the phase shift of an input signal. An A/D converter converts the input signal into first, second and third digital data according to successive three sampling points. A first subtractor subtracts the third data from the second data to produce a first subtraction signal. A second subtractor subtracts the first data from the second data to produce a second subtraction signal. A third subtractor subtracts the second subtraction signal from the first subtraction signal to produce a signal representing the phase shift. An adder adds the first and second subtraction signals together to produce a signal representing the amplitude of the input signal. A converter converts the signal representing the phase shift into a signal representing the absolute value of the phase shift according to the signals representing the phase shift and the amplitude.

Abstract: Timing unit for generating a timing signal for synchronous microprocessors in which an oscillator generates a base frequency equal to four times the timing frequency for the microprocessor. A frequency divider divides the base frequency by four, and a shift register clocked by the base frequency and receiving a timing signal from the frequency divider, generates a mask signal. The mask signal is selectively applied to a control input of the frequency divider in response to one or more control signals, to inhibit the switching of the frequency divider. This thereby introduces in the phases of the timing frequency, wait states equal to 1/4 (or multiple thereof) of the timing frequency, thereby matching the microprocessor speed to the memory read/write cycle time.

Abstract: A method for removing precipitate from a collecting surface of an electrostatic precipitator by rapping a point on the surface. Mechanical energy is applied a plurality of times with a rapper wherein the level of mechanical energy increases from one application of energy to another. Thus precipitate is removed from regions of the collecting surface progressively more distant from the energy application point. The time period between applications is selected to cause removal of precipitate from a region of the surface to be coincident with falling precipitate from regions above. The level of mechanical energy is controlled by applying to the rapper a sequence of full half-cycles of electrical energy followed by a single phase conduction cycle. The applied current is sensed and the duration of current application is adjusted to provide a predetermined energy level to the rapper. The polarity of the current is reversed to prevent magnetization of the rapper.

Abstract: The phase of an actual pulse signal (2') with respect to a phase reference pulse signal (1') can be accurately determined and a control output signal in form of a digital number be obtained rapidly depending on the relative temporal position of the phase pulse signals by counting at a high rate with respect to the pulse repetition rate of the phase reference pulse signal and providing count numbers as well as count rates in dependence of the time of occurrence of the actual pulse signal in relation to the reference pulse within a window period; if the actual pulse falls within the window period, the counting rate for the counter is increased, for example by decreasing the division ration of a divider (6), and the starting time for counting after the reference pulse is likewise extended, for example by addressing a starting time counter (4) from a PROM (5) the address of which is changed in dependence on the relationship of the actual pulse and the reference pulse.

Abstract: In construction of a digital phase locked loop for detection of the angular displacement of a mobile object depending on input signals from an encoder, is provided a bit number control circuit so that working bit numbers of A/D converters and a counter in the loop are automatically reduced as the frequency of the input signals rise and, in accordance with such reduction in working bit number, a function generating ROM of a smaller bit number is selected from a group of function generating ROMs of different bit numbers for supply of address data to multipliers connected to the A/D converters, thereby the signal processing speed of the loop is significantly raised to face up to current speed-up in the mobile object displacement.

Abstract: A pulse train divider circuit includes a first flip-flop (1) whose Q output is connected to the D input of a second flip-flop (2) whose Q output is connected to the D input of the first flip-flop (1). A pulse train to be divided is applied via an input (3) directly to the clock input C of the first flip-flop (1) and via a circuit (4) which delays the pulse train applied to the clock input C of the flip-flop (2) to provide a given phase relationship between the pulse trains at the two clock inputs. The circuit divides-by-two, and the resulting divided pulse trains available at the various outputs have phase relationships depending on the phase relationship of the applied pulse trains at the clock inputs.

Abstract: A novel digital phase shifter is provided for accomplishing digital phase shifting without the requirement of complex multiplication. The phase shifter includes buffer registers for receiving and storing the inphase and quadrature components of a complex number and for storing in a phase command register the information indicative of the phase shift to be accomplished. The phase shifting apparatus comprises a command map for generating a plurality of plus or minus phase shift command bits. A plurality of plus or minus phase shift registers are coupled to the phase shift command bits for performing plus or minus phase shifts of predetermined angles that diminish by a factor of approximately one-half from the previous phase shift angle.

Abstract: The digital phase-locked loop circuit extracts the clock signal from a serial flow of coded data by operating so as to determine the phase of the received signal and comparing this phase with that of a locally-generated signal. The error signal obtained from the comparison is digitally filtered and used to correct the phase of local signal. The error with respect to the signal extracted from a prior data stream is stored and used to effect corrections even in the absence of the data flow at the input or in presence of long zero sequences.

Abstract: During the receipt of a result of comparison from the phase detector representing that the synchronization signal is phase-delayed behind the input signal, the selection circuit sequentially selects the M number of counters, one by one, in a cyclic fashion, in such a direction as to permit the reference clock input to be phase-advanced correspondingly, so that the frequency-divided output signal from the counter to the phase detector can be sequentially phase advanced by 1/M of one cycle of the reference clock. During the receipt of a result of the comparison indicating that the synchronization signal is phase-advanced ahead of the input signal, on the other hand, the selection circuit sequentially selects the M number of counters, one by one, in a cyclic fashion, in such a direction as to allow the reference clock input to be phase-delayed, so that the frequency divided output signal from the counter to the phase detector can be sequentially phase-delayed by 1/M of one cycle of the reference click.

Abstract: Phase quantizer apparatus in an all digital phase locked loop to provide a two-part digital number representing the phase of the input signal (a noncontinuous pulse train) relative to the output signal of the all digital phase locked loop. The phase quantizer comprises a write counter (modulo m counter) and a phase counter (modulo n counter) which receive the noncontinuous pulse train as an input signal. The leading pulse edge in the noncontinuous pulse train increments the write counter and resets the phase counter. The write counter comprises a binary counter and a conversion circuit. The binary counter portion of the write counter was being used and is still being used in the digital communications system to provide address information to the elastic buffer to read data into predetermined storage locations in the elastic buffer.

Abstract: An all digital equivalent to a voltage controlled oscillator with low intrinsic jitter and the absence of sample aliasing within a nonzero bandwidth, the offset (non-symmetrical) digitally controlled oscillator comprising a divider (divide by n or n-1) which is timed from a high speed reference clock, a 2.sup.m counter and a digital comparator. The divider divides the high speed reference clock signal so that for every thirty second cycle of the high speed reference clock a pulse is output from the present invention. The output pulse is input to the 2.sup.m counter and increments same. The 2.sup.m counter counts the number of output cycles (or pulses) that have occurred since the last phase adjustment and comares this m-bit number to the input to the present invention. When the output of the 2.sup.m counter becomes greater than or equal to the input, a divide by n-1 signal is sent to the divider which shortens the output cycle and adjusts the average output frequency and phase. The 2.sup.

Abstract: A digital phase locked loop to function as a stable reference clock given a gapped, or pulse stuffed, input clock signal which may have a frequency offset relative to the nominal specified frequency and a phase jitter relative to the average frequency of the input signal, the digital phase locked loop comprising an input synchronizer for synchronizing the input clock signal to a stable high frequency reference clock. The output of the input synchronizer increments a write counter and resets a phase counter to zero at the begininning of each cycle of the input clock signal. The outputs of the write counter and the phase counter are sampled by a sampling circuit which interprets the sampled data in two's complement form.

Abstract: A pulse width control circuit for providing a control signal to adjust variations of electrical characteristics among a plurality of printing elements has an up/down counter and a plurality of control signal generating circuits. The up/down counter counts the number of pulses of a clock signal and delivers the counted value. The control signal generating circuit compares the counted values from the up/down counter with set values corresponding to conduction time periods of the currents used for driving light emitting diodes, and generates a plurality of control pulse signals having pulse widths whose central positions thereof are in accord with each other.

Abstract: A system for and a method of generating a four phase clock signal is disclosed. The system includes an oscillator circuit that generates a clocking signal of frequency F. A flip-flop, under control of a Master Clear signal, establishes the first stage of a shift register in an active state while the clocking signal drives the shaft register to serial, end-around, shift the active state through the shift register. The parallel outputs of the shift register are coupled to respectively associated pulse generators which are also triggered by the clock signal to emit the four phase clock signal therefrom. The method ensures that the first phase signal is always the first signal to be emitted from the system while compatible semiconductor circuitry is used throughout and is operated at or near the frequency limit of the semiconductor circuitry used.

Abstract: An electronic phase shifter utilizes a serrodynable digital phase shifter which is driven by the output of a multi-bit counter. The counter in turn has its clock input driven by a pulse train which produces the desired frequency translation for noise and deception jamming. Alternatively, the counter has jam inputs for electronic antenna steering and electronic phase shift applications. In order to compensate for step phase error which causes undesirable spurious sidebands, the cells of the phase shifter are pretested for individual phase errors and an interface memory is provided which by use of a corrected counter code minimizes the errors.

Abstract: A process and an arrangement for generating control signals in a predeterminable phase position relative to an alternating voltage at an at least short term-stable frequency through the utilization of a higher-frequencied, at least short term-stable auxiliary timing pulse. The process contemplates determining the duration of a presettable number of periods of the alternating voltage, in which there are counted the periods of a first auxiliary timing pulse occurring within this duration; counting the periods of a second auxiliary timing pulse of a different frequency which is correlated over a period of time with the first auxiliary timing pulse; and upon coincidence of the period count of the first and second auxiliary timing pulses, generating the control signal. The circuit arrangement consists of standard digital circuits.

Abstract: A first 5-stage ring counter generates a signal having a frequency of (4/5)f.sub.SC by dividing a frequency 8f.sub.SC of a signal. A second 5-stage ring counter generates a signal having a frequency of (4/5)f.sub.SC by dividing a frequency of a signal obtained by inverting the signal of frequency 8f.sub.SC by an inverter. A first sampling pulse output circuit generates a first sampling pulse from an output signal from the first 5-stage ring counter. A second sampling pulse output circuit generates a second sampling pulse from an output signal from the second 5-stage ring counter. A phase correction circuit causes synchronization of the count operation of the first 5-stage ring counter with a clock run-in signal. This phase correction is performed by shifting the phase of the output from the first 5-stage ring counter in units of the period of the signal of frequency 8f.sub.SC.

Abstract: Analog-to-digital conversion and a computer produce finer resolution for interferometer distance measurement. The system applies to a laser interferometer producing two detected signals with voltages 19 and 20 that vary to form two sine waves in quadrature as interference fringes occur. A pair of analog-to-digital converters 21 and 22 converts each of these signals into digital values subdividing each sine wave fringe cycle into a plurality of increments. An up/down counter 25 supplied with a significant digit from each of the converters counts fringes corresponding to changes in path lengths. A computer 30 arranged with access to the fringe count and the digital increments determines a distance measurement based on the fringe count and a fine resolution of the distance measurement based on final values of the signals at any subdivided fringe cycle increments after changes in the path lengths.

Abstract: Characteristics of a pulse sequence, such as frequency, are controlled in a simple circuit without requirement for specific storage components. The cumulative effect of a sequence of control signals is maintained by providing a phase shift between a pair of waveforms. The phase shift between the waveforms is used to provide a number of control pulses to the circuit for varying the desired characteristic. In a particular embodiment, control signals are externally provided for varying the phase shift between two waveforms. In response to the phase variation, a number of control signals are provided for adding or deleting pulses to a pulse stream. The use of feedback control loops results in repeated addition and/or deletion of pulses to or from the pulse stream, thereby varying the output frequency in accordance with a one time input of the external control signals.

Abstract: A phase shift between two repeated square wave signals having equal frequency and duty is detected and detected phase shift is integrated during the appointed cycles of the square wave signals and the mean value per cycle is calculated from the integrated value, and a phase of one signal is overlapped on a phase of another signal automatically at the mean value. The same phase can be automatically given to two square wave signals having different phases.

Abstract: A phase measuring arrangement for sampled signals changes the phase of the sampling signal in fine phase increments while comparing the magnitudes of the signal samples so produced to determine whether they have magnitudes within a given range of values. The range of values is indicative of a known phase angle. The number of magnitudes falling within the given range is indicative of the phase of the sampled signal relative to the known phase angle. Embodiments are disclosed in which such phase measuring arrangement is employed in a phase-locked loop useful for processing chrominance signals in a television receiver.

Abstract: A synchronous signal generator includes a counter controller for producing a control signal from a reference signal inputted thereto, and a counter circuit responsive to the control signal for generating a given cyclic signal. The counter controller accumulates each frequency of appearances of phase positions within a given period of time. When any of accumulated frequencies of the phase positions reaches to a given value from which the largest number of appearance times of the phase position is obtained, the counter controller supplies the counter circuit with the control signal. The counter circuit is reset or preset by the control signal. Since the probability that a phase position of the control signal is exactly coincide in time with a true phase position of the reference signal is very strong, the counter circuit can continue to repeat its cyclic count operation in synchronism with the control signal and yet being independent of the jittered reference signal.

Abstract: A phase control device for producing a reference pulse train and a plurality of pulse trains and controlling the latter pulse trains so that each of the latter pulse trains is independently displaced by a desired phase amount from said reference pulse train. The device can be preferably embodied in underwater detection systems.

Abstract: A digital frequency relay for use in protecting an electrical power transmission line in the event of frequency deviations indicative of a fault condition, including an input device for receiving AC electric signals, and an oscillator for generating a reference frequency, which are connected to respective first and second counters which respectively count the number of output pulses from the oscillator during the AC electric signal positive half-cycle, and during the AC electric signal negative half-cycle. The resultant output from the first and second counters is added and compared with a set value to produce a trip signal for the frequency relay.

Abstract: A phase-locked loop is implemented using strictly digital techniques. The average frequency of the input signal is first sampled by counting the number of pulses from a clock source which occur during a predetermined number of occurrences of the input signal. Thereafter, the number of pulses counted is divided by the number of cycles of the input signal which occurred during the counting period to determine an average number of pulses per input signal cycle. The number of pulses which occur between successive cycles of the input signal are then counted and compared against the previously determined average. A count which differs from the average indicates a change in phase of the input signal, and after appropriate weighting, is used to update the average to a new average. An output signal is produced when the number of pulses counted during a cycle of the input signal equals the average number of pulses determined to occur between successive cycles of the input signal.

Abstract: The present invention is a system for accurately phase locking two signals having the same frequency but which are of arbitrary wave shape, and which can be at very low or at substantially higher frequencies. Elements of two signals are stored at sequential address locations in a pair of ROMs. An oscillator drives a counter which provides a sequential address output signal, which is used to address the first ROM. A binary signal which can be generated from a manual control calibrated in 360.degree. provides a phase control signal which is added to an address signal generated from the same oscillator, and which is used to address the second ROM. The increment between the two ROMs established from the control provides control over the phase differential between the two generated signals. Since the addresses of both ROMs are generated from the same oscillator, their frequencies are the same, and their phases are locked at the desired phase differential.

Abstract: Apparatus for imparting a delay to an input signal utilizing counter means comprised of a plurality of binary coded decimal counter stages connected in cascade. The high frequency input signal applied to the counter undergoes a divide-by 10.sup.N operation wherein N equals the number of binary coded decimal stages. Preferably, the least significant stage is adapted to be selectively and periodically preset to a binary coded decimal value different from its normal reset state to either increase or reduce the number of pulses required to cause the counter stage to read a terminal count to selectively either advance or retard the phase of the reduced frequency output signal developed at the output of the counter relative to the phase of the input signal applied to the counter in accordance with a preprogrammed value set into said counter stage.

Abstract: This disclosure relates to a timing circuit for a digital display, which circuit includes a series of counters, each having four stages such that each counter will drive the next stage only when it has progressed from zero to seven. By reading out the state of each stage of the respective counters, selected counts can be decoded from only two of the respective stage readouts.

Abstract: In a multiple stage data transfer circuit, suitable for transferring a plurality of bits to or from a bit processor or 1-bit arithmetic logic unit, each bit stage includes a shift register portion and a latch portion. Each shift register(S/R) portion is constructed of a series circuit consisting of a static (input) inverter, a switching element, and a dynamic (output) inverter. Each latch portion is constructed of a closed loop consisting of a static inverter, a switching element, and a dynamic inverter. Each bit stage also includes a data transfer switch element, which may be activated through an externally connected control line. The data transfer switch is coupled beween the data output terminal of the S/R switch and the data output terminal of the latch switch. The S/R and latch portion switches are activated by two different clocks, with a phase deviation therebetween of one-half cycle. When the S/R switch and data transfer switch are both "ON", data may flow from the S/R's input inverter to the latch.

Abstract: A circuit for detecting leading or lagging phase relationship between first and second two-level input signals at each level transition of a selected one of the input signals and comprising first and second Exclusive OR gates each having first and second input terminals and a single output terminal and each responsive to signals of equal and non-equal logic levels supplied to the first and second input terminals thereof to produce an output signal having high and low logic levels, respectively. Further connections supply the first and second input signals to the first input terminal of the first and second Exclusive OR gates, respectively.