Abstract: Methods and systems are described for automatic system access using facial recognition. According to at least one embodiment, an apparatus for automatic system access using facial recognition includes a processor, a memory in electronic communication with the processor, and instructions stored in the memory which are executable by a processor to identify faces of a plurality of persons relative to a premises, and determine, based at least in part on the identifying, a first person from the plurality of persons satisfies a frequent occupant threshold. The instructions are executable recognize the first person at the premises after determining the first person from the plurality of persons satisfies the frequent occupant threshold and initiate a change of state of a security and/or automation system based at least in part on the recognizing.

Abstract: The presentment and redemption system offers discounts directly to consumers through their mobile phones. The discounts are based upon the user of the mobile phone meeting a targeting criterion and the discounts are determined using the targeting criterion. Mobile phone users that do not meet the targeting criterion are not eligible for the discount. Because the discounts can be targeted to each individual consumer, there can be a better correlation between consumers' interests and the transmitted discounts.

Abstract: A person counting device generates a single panorama image by using a plurality of images respectively captured by a plurality of cameras, inserts an imaginary line to the single panorama image; and counts the number of persons that pass the imaginary line. To this end, identification numbers are allocated to respective persons in the plurality of images, the single panorama image including the imaginary line is restored to a plurality of images including same imaginary line information, the number of persons that pass a new imaginary line in each of the plurality of restored images is determined, and the number of duplicate-counted persons is ruled out.

Abstract: A contactless sensor utilizes analog and digital circuitry to provide direct interchangeability with a simple potentiometric sensor, matching all of the electrical properties of a potentiometer, including supply voltage range, power supply current, output voltage range, and having three connection terminals. The contactless sensor operates with voltages from 2 to 30 volts direct current, which includes all of the common industrial sensor power supply voltages: 5V, 10V, 24V, and +/? 15V. The contactless sensor utilizes a total current of less than 0.005 amperes, and its output voltage range includes the power supply rails. These improvements combine to enable the contactless sensor to be a direct replacement when a potentiometric sensor is removed from service.

Abstract: A data processing method may include counting one of a plurality of clock signals with a first mode, counting clock signals based on a predetermined number of the plurality of clock signals with the first mode, to output a first clock signal every time a counter value becomes a first predetermined value, counting the first clock signal with the first mode, counting one of the clock signals with a second mode while the counted value is considered as a first initial value, counting clock signals based on the predetermined number of the plurality of clock signals with the second mode, to output a second clock signal every time the counter value becomes a second predetermined value while the counted value is considered as a second initial value, counting the second clock signal with the second mode, and outputting the counter values with the second mode as difference data between a first data signal and a second data signal.

Abstract: A system that includes a controller for enabling an enumeration operation. The enumeration operation is performed by a controller (110) and logic elements (120) in a system, such that each logic element in the system assigns itself a unique identifier. Each logic element can then be controlled by another source or have a means to communicate with other logic elements in the system. The unique identifier enables greater system flexibility, thereby reducing cost and improving efficiency.

Abstract: A solid-state image pick up device including a pixel array unit having unit pixels arranged in a matrix pattern. Each unit pixel includes a photoelectric converter. Additionally, the solid-state image pick up device has column signal lines that correspond to the respective columns of the matrix pattern, a row scanning means for selectively controlling each unit pixel, and an analog-digital converting unit for converting analog signals output from the unit pixels in a row selectively controlled by the row scanning means. The analog-digital converting unit further includes an asynchronous counter which performs counting in two modes and the asynchronous counter includes a counter processor configured so that when switching between the count modes occurs, a running count value is broken and there is an interval between the count modes and when a mode begins the running count value is reset to the value before the running count value was broken.

Abstract: An asynchronous counter that is capable of switching count mode includes flip-flops, and three-input single-output tri-value switches respectively provided between the adjacent pairs of the flip-flops. The tri-value switches switch among three values, namely, non-inverting outputs and inverting outputs of the flip-flops and a power supply level. Each of the tri-value switches switch among the three input signals according to two-bit control signals, and input a selected signal to a clock terminal of a subsequent flip-flop. When count mode is switched according to the control signals, a count value immediately before the mode switching is set as an initial value, and counting after the mode switching is started from the initial value.

Abstract: The invention relates to a method for overload-free driving of an actuator, in which an activation counter is incremented or decremented each time an activation request signal occurs, in which, depending on each occurrence of an activation request signal, a drive signal for the actuator is generated if the counter reading of the activation counter is less than or greater than a predetermined maximum or minimum counter reading, in which the counter reading is in each case decremented or incremented if the time since the last generation of a drive signal or since the deactivation of the drive signal is greater than or equal to a predetermined or predeterminable interval time or if the time since the last decrementing of the activation counter is greater than or equal to the interval time.

Abstract: An asynchronous up-down counter includes a plurality of counter blocks. Each of the counter blocks has a counter output, an up-down control output, and an up-down control input. A counter signal output from each of the counter blocks has at least two bits. The asynchronous up-down counter also includes a signal bus coupling the up-down control output of a first counter block counting lesser significant bits to the up-down control input of a second counter block counting more significant bits. An up-down control signal output from each of the counter blocks has at least two bits. The up-down control signal may include a first control signal enabling counting operation of the second counter block and a second control signal indicating counting-up and counting-down.

Abstract: A conventional up/down Gray code counter has both a logic circuit section for up counting and a logic circuit section for down counting, and thus has a large circuit scale. To overcome this inconvenience, an up/down Gray code counter of the invention has a one-way Gray code counter that can count only in one, up or down, direction and a highest bit selecting circuit that receives the highest bit of the data output from the one-way Gray code counter and that then outputs the bit selectively either intact or after inverting it.

Abstract: An improved DDLL containing a majority filter counter circuit is disclosed. The majority filter counter circuit is located between the phase detector and the shift register of the DDLL. The majority filter counter circuit receives shifting commands from the phase detector and filters the shift commands from reaching the shift register until a predetermined number (e.g., 16) have been received from the phase detector before transmitting a shift command (either shift right or shift left) to the shift register. Once the shift register receives the shift command, the shift register directs the delay line to shift by one tap in either a shift right or a shift left direction depending upon the phase relationship between CLKIn and CLKOut. By waiting for e.g., 16 shift commands, the majority filter counter circuit ensures that a premature shift command is not delivered to the shift register in the case of a noise event.

Abstract: A method for counting a number of objects passing through an entry threshold, comprising the steps of disposing a sensor (11) having a matrix of sensing points in an area of the entry threshold, identifying successive complete footprints of the same object on the sensor, and distinguishing between different footprints using clustering. The method is used in association with a pressure mat disposed at the entry threshold and tracks the progress of the object across the mat. Specifically, when a footprint vanishes from the mat, retroactive processing is effected in respect of the body associated with that footprint so that other footprints belonging to the same body may be ignored. The number of footprints thus associated with the body and which are not ignored serves as a counter of the number of bodies crossing the entry threshold.

Abstract: An apparatus for eliminating noise is disclosed. The present invention includes a counter, which counts in a first direction when an input signal is active, and in a second direction otherwise. A determining device is used to determine a predetermined first threshold value, and assert an output signal while such value is reached. The present invention also includes a limiting device, which prevents the counter from counting beyond or below a predetermined limit value.

Abstract: The invention herein provides a supervisory circuit which is adapted to monitor an input signal and produce as an output signal, a parametric signal corresponding to the input signal. The circuit includes an input for receiving the input signal, and a stochastic processor coupled to the input for receiving the input signal and processing it to derive a signal that represents a parametric measure of the input signal. An output connected to said stochastic processor provides the parametric output signal as an output for supervisory purposes.

Abstract: The counter of the present invention includes an input unit, a sampling unit and a determiner unit. The input unit receives a plurality of control signal including a mode selection signal, a clock signal and a reset signal. The sampling unit receives output signals of the input unit based on the clock signal and reset signal. The sampling unit has a plurality of latches and generating a plurality of first output signals and the adjacent latch of the plurality of latches are coupled to each other. The determiner unit is coupled to the sampling unit to receive the plurality of first output signals and is coupled to the input unit to receive an output signal based on the mode selection signal. The determiner unit outputs a plurality of count signals indicative of a count value, which is incremented or decremented based on the mode selection signal.

Abstract: An output buffer with a slew rate that is load independent is comprised of an output buffer (14) that is connected to an output terminal (12). The output buffer (14) is controlled such that it can drive a load (18) with different drive levels by changing the transconductance internal thereto. The transition on the input to the buffer (14) is passed through an intrinsic delay block (34) and variable delay block (40) to provide a delay signal on a node (42). A first phase detector latch (50) with a first threshold voltage compares this transition with the transition on the output terminal (12). A second phase detector latch (60) with a second threshold voltage, also compares this delayed transition with that on the output terminal (12). If both of the latches (50) and (60) indicate that the delayed transition occurred after the transition on the output terminal (12), a control signal on a line (78) is changed by incrementing a counter (74). This will increase the drive to a load (18).

Abstract: In a ramp signal producing apparatus, a ramp signal is produced under low clock signal frequency in a compact circuit arrangement. Luminance control and a white balance control are carried out by the ramp signal in a liquid crystal display. The ramp signal producing apparatus is comprised of: an up/down counter for either counting up, or counting down a clock signal supplied thereto; amplitude amount converting means for converting the amplitude of the supplied clock signal into such an amplitude value corresponding to the count value of the up/down counter and for converting the amplitude value in such a manner that a change amount per one count value is increased during the count down operation by the up/down counter; and ramp signal producing means for producing such a ramp signal with an amplitude corresponding to the converted amplitude value.

Abstract: A zigzag scanning address generator includes a row address generator for generating a row address signal which stops, increases or decreases a present state in response to an enabling signal, and a column address generator for generating a column address signal which stops, increases or decreases a present state in response to the enabling signal. Therefore, the zigzag scanning address generator can generate zigzag scanning addresses according to a zigzag scanning method, simplifying the circuit configuration needed for generating the address signals corresponding to the zigzag scanning pattern.

Abstract: An apparatus for counting occurrences of a particular input during a plurality of succeeding periods. The apparatus comprises an input terminal for receiving the input, a toggle signal generating circuit for generating a periodic toggle signal to mark the plurality of periods, and a plurality of n counter cell circuits for effecting the counting in n bits. Each counter cell circuit generates at least a respective bit output, a respective toggle output, and respective carry output. The counter cell circuits are arranged in hierarchical order from a least-significant counter cell circuit to a most-significant counter cell circuit.

Abstract: Monolithic arrays having closely spaced laser stripes which output laser beams with large, but well-controlled, wavelength separations. The monolithic array uses a plurality of stacked active regions which are stacked in the order of decreasing energy bandgaps as one moves away from the substrate. Those active regions are separated by one or more thin etch stop layers. Between the bottom active regions and the substrate is a lower cladding layer, while over the topmost active region of each stack is an upper cladding layer. Beneficially, an electrical connection is made to each stack using a heavily doped capping layer/metallic contact above each stack and a metallic contact on the substrate (which is shared by all stacks). Lateral carrier and optical confinement is achieved using a confinement layer which surrounds each stack. Beneficially, that confinement layer is formed using layer induced disordering.

Abstract: A frequency doubler having adaptive biasing includes one shot circuits 10 and 12, which are responsive to particular transitions of an input signal for generating pulsed signals at each such transition. The widths of the pulses are determined by the magnitude of a bias current supplied to the one shot circuits. The pulsed signals of one shot circuits 10 and 12 are combined by OR gate 14 to provide an output signal whose frequency is twice the frequency of the input signal. A low-pass filter 16, coupled to the output signal, produces a signal which is a measure of the average voltage level of the output signal. Voltage-to-current converting FET 18, responsive to the average voltage level of the output signal, supplies bias current to one shots 10 and 12. Comparators 20 and 22 detect when the average voltage level is not within a predetermined range, and enable either up or down counting of digital counter 24.

Abstract: A tape recorder comprises a reproducer for reproducing an information signal recorded on a tape-shaped recording medium, a transporter for transporting the tape-shaped recording medium, a dial and a controller for setting a transport speed of the tape-shaped recording medium at one of a plurality of speeds according to a rotation phase angle of the dial, the controller being arranged to be operable while the reproducer is in operation and establishing a plurality of predetermined specific speeds within the plurality of speeds having a relatively greater phase angle of rotation of the dial than the phase angle rotation of the dial for the plurality of speeds not at the predetermined specific speeds.

Abstract: A revolution counting circuit for performing such an operation includes a pulse multiplying unit for multiplying signal pulses generated by an encoder and a pulse dividing unit for dividing the multiplied signal pulses by a divided value set up by a microprocessor. Further, a revolution counting circuit may include a pulse selection unit for selecting one of the signal pulses generated by the pulse multiplying unit and the pulse dividing unit. Also included are a waveform shaping unit for generating a pair of divided signal pulses having the same phase difference as the signal pulses generated by the encoder and a control signal generator for sending control signals to the waveform shaping unit.

Abstract: A linear time counter for calculating a tape running amount on the basis of a reel rotation number, comprises a reel rotation pulse detection mechanism for detecting the number of reel rotation pulses or reel rotation pulse edges, and a count and calculation processing portion for adding or subtracting values of tape running times t to calculate an accumulated value of the tape running times, wherein when any of the supply reel and the take-up reel rotates by one interval of the reel rotation pulses or reel rotation pulse edges, the number of reel rotation pulses or reel rotation pulse edges counted by the other reel is assumed as n, and the above-mentioned running time t obtained by converting a running amount of the tape to a running time at the time of a constant speed running is expressed as follows:t=(1+n-K.vertline.1-n.vertline.

Abstract: To sense the presence of written data on an optical disk, the readback signal from the disk is detected, and the intervals between detected signal events are measured. That signal event occurring at an expected time delta after the preceding signal event indicates a valid data signal time delta. Those signal events occurring at an unexpected time delta after the preceding signal event indicates the readback signal to be noise. If the count of valid signal time deltas minus the unexpected time deltas attributed to noise accumulates rapidly along a given track within a given sector of the optical disk that sector is determined to be written. Provision is made for counting signal events in accordance with the specific run-length limited in use.

Abstract: The input voltage from a fuel tank level sender is processed by an anti-slosh circuit which has a short time constant during a fast acquire operation and a longer time constant during normal operation. The slew rate of the output voltage provided to a gauge is determined by the clock rate of an up/down counter which is determined by switched resistances and a small valued capacitor. Either analog or digital anti-slosh outputs are provided.

Abstract: A precise digitally-controlled variable attenuation circuit for adjusting e attenuation of a signal in an external circuit includes a signal magnitude detector, a resistance adjustment control, and a resistance divider network. The signal magnitude detector has lower and upper threshold limits representing a desired range of attenuation and is operable to receive and compare a control signal with the lower and upper threshold limits, and, in response thereto, produce either a first signal if the control signal is less than the lower threshold limit or a second signal if the control signal is greater than the upper threshold limit. The adjustment control is capable of receiving the first and second signals and is operable to produce either a digital count-down signal in response to the first signal or a digital count-up signal in response to the second signal. The resistance divider network has a fixed resistance and a digitally-adjustable device with a variable resistance.

Abstract: A counter circuit comprises a signal detector for providing an up/down indication signal and a count clock signal according to an up/down signal and a reference clock signal. A n-bit counter for providing up/down count data of "n" bits according to the up/down indication signal and count clock signal. A counting direction detector provides a counting direction signal according to the up/down indication signal and reference clock signal. This counter circuit itself determines whether it is counting up or counting down, by hardware, and thus can instantaneously respond to a direction identification request from a central processing unit.

Abstract: A reload timer circuit comprises an n-bit up/down counter circuit for receiving input data of n bits and providing up/down count data of n bits; an n-bit timer circuit for receiving the n-bit up/down count data and providing timer data of n bits; and a timer period setting means for generating a timer period signal in response to an overflow signal of the n-bit timer data and providing the n-bit up/down counter circuit with the timer period signal. This reload timer circuit automatically sets a reload value by hardware without relying on software, thereby reducing the load on a central processing unit.

Abstract: An arrangement for driving a rotary tool is provided in which the tool shank is engaged and frictionally driven by the engagement of three or more drive rollers. Axial movement of the tool is accomplished by tilting the axes of the rollers as permitted by flexible portions of the shafts which drive the rollers. The tool is released by moving one roller away from the other two. A pressure foot is provided at the bottom of the assembly reciprocated by a cam arrangement to engage the workpiece when the tool is in operation. A position pick-off senses the axial position of the tool so that the tilt angle of the rollers can be controlled by a dual feedback path servo loop having an improved preconditioning circuit for its feedback position counter.

Abstract: A simple technique for determining and indicating, in real times as an image is scanned, the presence of halftones within a page. in brief, the technique contemplates monitoring a pixel stream, typically on a line basis, determining the proportion of pixel transitions (relative to the overall number of pixel intervals), and controlling the process based on this information. In one embodiment, a numerical value representing such a proportion is compared to a threshold, and a value in excess of the threshold is taken to signify the presence of halftone regions. Based on this, special processing for halftones is enabled or special processing for non-halftone regions is disabled. In a specific hardware embodiment, the pixel monitoring circuitry includes a transition detector (50), an up/down activity counter (52), a threshold selector (55), and a counter controller (57).

Abstract: An updown counter up-counts binary data stored in respective flip-flops in an up-count mode, and down-counts the binary data stored in the respective flip-flops in a down-count mode. When a command for an up-count mode is applied by an up/down control signal, the binary data stored in the respective flip-flops is converted into a complement on two after converting it into a complement on one. When a command for a down-count mode is applied by an up/down control signal, the binary data stored in the respective flip-flops is converted into a complement on one after converting it into a complement on two. The converted data is used to rewrite the data stored in the respective flip-flops.

Abstract: A clock jitter suppressing circuit includes a control circuit, a delay circuit, and a selection circuit. The delay circuit sequentially delays a clock signal at time intervals sufficiently shorter than the period of the clock signal. The selection circuit selects and outputs one of delay outputs from the delay circuit which is determined in accordance with a selection signal. The control circuit generates a selection signal for selecting a predetermined delay output when no jitter is caused in the clock signal. Every time jitter is caused in the clock signal, the control circuit generates a selection signal for selecting a delay output which is shifted by an amount corresponding to the phase amount of the jitter in a direction to cancel a polarity of the jitter.

Abstract: A Gray Code counter is provided having synchronous, modular circuits for each of the three types of bit positions, i.e., least significant bit ("LSB"), most significant bit ("MSB") and middle bit ("MB"). One LSB and MSB circuit each are used with as many MB circuits in between as are necessary to provide a counter having the desired number of bits. The LSB, MSB and MB circuits' designs are truly modular in that duplicate MB circuits can be freely coupled together between an LSB circuit and an MSB circuit to provide the desired number of counter bits without modifying any input or output interfaces between the circuits. The counter can count either up or down in accordance with a normal Gray Code sequence.

Abstract: A digital resolver is provided that accepts an analog representation of an angular or linear displacement within a reticle modulation cycle of a rotatable or translatable member, and provides a highly accurate output digital representation of the displacement within the cycle, even during rapid movement of the member. An encoder cooperative with the interpolator receives an analog signal that represents the displacement, and yields a pair of quadrature-phased sine wave signals accordingly. These signals are provided to the interpolator, wherein each is multiplied by a stored digital representation of a trigonometric function of the output digital signal. The resulting products are then added so as to provide an error signal which is used to drive a digital control loop, such that a digital output signal is provided that represents displacement within a reticle cycle.

Abstract: Apparatus for controlling the time constant of a signal includes an up/down counter for counting pulses of a clock signal. The count value is utilized as output signal. The output signal is compared with the input signal to provide a first control signal determinative of whether the counter counts up or down. The output signal is compared with the input signal offset by a constant value to provide a signal which is ORed with the first control signal, and the ORed signal is utilized to enable/disable the counter. Applying a constant offset value to the input signal to be compared precludes the system from alternately counting up and down by one unit value during intervals of relatively constant amplitude input signals.

Abstract: A system for determining the position of movable machine parts including an incremental pulse generator for generating angular-speed pulses includes a computer. At least one counting circuit via which the incremental pulse generator is connected to the computer counts the generated angular-speed pulses.

Abstract: A digital signal clamp circuit is realized using an adder and an up/down counter. The digital signal is coupled to one input of the adder and the counter output is coupled to a second input of the adder. The up/down counter is enabled to count only during signal intervals exhibiting the desired clamping level. The counter is controlled to count up or down depending on the polarity of the signal provided by the adder. The count value in the counter is continuously applied to the adder to provide clamping. Using a truncated count value from the counter enhances clamping performance.

Abstract: A method and device for evaluating signals of an incremental pulse generator for generating at least two mutually phase-shifted angular speed signals includes counting the angular speed signals only if a permissible combination of the angular speed signals is present.

Abstract: A digital logic circuit for use with an incremental positioning encoder is presented. The circuit converts two quadrature pulse train signals, generated by an incremental position type encoder, to a counting CLOCK signal and an UP/DOWN count signal. The signals are transmitted on counters to generate counting clock signal and the UP/DOWN count position information. The circuit utilizes gate delays to detect the edge of a pulse train signal. No external clocks or comparators are nested. The design, by relying on the propagation delay of gates, keeps the circuit simple and more reliable.

Abstract: An electronic pulse counter includes a given number of shift registers each having a different number of memory elements, an input, an output and a clocking line. Each of the shift registers is countercoupled by a negation between the input and the output thereof. A pulse counter input is formed by interconnection of the clocking lines of all of the shift registers. Pulse counter outputs are formed by the outputs of the shift registers.

Abstract: This invention relates to a precise position device, particularly to such device in which an insensitive zone of an absolute signal consisting of a stepped analog signal formed on the basis of the two-phase incremental position detection signal obtained from an encoder section is eliminated, and an output signal having an approximately linear form may be obtained.

Abstract: A two-phase encoder circuit for detecting a moving status of a moving article in accordance with first and second detecting signals which are input having a phase offset of 90 degrees and having repeated status of "H" and "L" according to the movement of said moving article, wherein the first detecting signal is taken in synchronization with a clock signal and an output received signal is sequentially output while a delay circuit having an input from at least the received signal outputs a delay signal more delayed than the received signal by less than one period of the clock signal, a pulse signal circuit having an input from at least the received signal outputs, a pulse signal in synchronization with an inversion of status of the received signal and the number of pulses of the pulse signal is counted while counted up or down according to the status of the delay signal with the counting operation being made when the second detecting signal has one status of ""H" and "L".

Abstract: An N stage Gray code generator includes an N stage binary counter having an input for receiving clock pulses to be counted and providing N outputs forming an N bit binary code. N minus 1 storage stages capable of being toggled between a logic "1" and a logic "0" state, each having a toggle input to cause them to toggle, have their toggle inputs coupled to the outputs of the first N minus 1 stages of the binary counter. The outputs of the N minus 1 storage stages form the first N minus 1 Gray code outputs and the most significant output of the binary counter provides the most significant output of the Gray code generator.

Abstract: A track counting circuit for an optical disk driver is disclosed. The pickup passing a track is detected through a differential amplifier receiving signals from photo diodes, an amplifier, a tracking processor, a positive zero crossing detector, and a negative zero crossing detector. The signals sensed by photo diodes are applied to one of the input terminals of each of a pair of NAND gates through a differential amplifier, level comparators and a flip-flop, and the other input terminals of the NAND gates receive the signals which are obtained by the signals sensed by the photo diodes being processed through an adder and a level comparator to distinguish whether the pickup is placed on the track or land of the disk, the output signals of the NAND gates controlling the output signals of a flip-flop which control an up/down counter to make an up/down count depending on the moving direction of the pickup on the track so that the intended track is found precisely and easily.

Abstract: Disclosed is a combination of a counter operating in response to an input signal, a latch circuit for latching the output of the counter and a read-command signal inhibiting circuit controlling the latch circuit so as not to effect the latch operation for a predetermined period from the input signal for a time necessary for the operation of the counter, in response to a read-command signal.

Abstract: A digitally controlled timing circuit for providing an output pulse signal precisely delayed with respect to an input signal irrespective of the time of occurrence of a system clock, but which uses the precision of the system clock to self-correct any inaccuracy in the delay includes a plurality of delay elements, the delay period of a respective one of which is adjustable, coupled between an input terminal, to which an input terminal is applied, and an output terminal, from which a delayed output signal is to be derived. Coupled to the input terminal and the plurality of delay elements is a toggled flip-flop which, with the delay elements, during a calibrate mode, forms an adjustable oscillator and generates a sequence of signals the lapse of time between successive ones of which is established by delays imparted by selected ones of the delay elements. The delays imparted by selected ones of the delay elements.

Abstract: This invention relates to an improved signal reader for reading signals from transponders placed on moveable objects such as ship containers, automobiles or railroad cars. The reader sends out a continuous signal, which is modified by the information contained in the transponder attached to the moveable object. Multiple antennas, each of which receive separate signals, may be multiplexed at the reader. The improved circuit of the invention provides quick recognition of the receipt of a valid signal from a transponder or, in the alternative, the absence of such a valid signal.

Abstract: The position of the moving mirror (20) in a Fourier-transform infrared spectrometer is monitored with a circuit which has an incremental counter formed of a plurality of cascaded up/down counters (82, 84, and 86) that count the pulses received by a laser detector (42) to yield a relative position count. A microprocessor (100) maintains an absolute position count by reading the counters (82, 84, and 86) and updating its absolute position count at regular intervals. A portion of the circuit is dedicated to discriminating the direction of the moving mirror (20) by gating circuitry connected to the digitized output of the laser detectors (42, 44).