Abstract: A high speed digital counter that can be easily tested comprises a plurality of subcounters having an input for receiving an incrementing signal and a carry output for outputting a carry signal when the subcounter has reached its counting capacity. The carry output of each subcounter is gated to the input of a next more significant subcounter by an OR gate which receives as inputs the carry signal and a test signal. The OR gate performs an OR on these two signals and outputs the result to the input of the next more significant subcounter. The OR gate allows the test signal to access each subcounter separately, and thus, each subcounter may be tested individually.

Abstract: The revolutions of a diesel engine are counted by providing vibration detector converting the vibration propagating through the fuel injection pipe into an electric signal; an amplitude sorter for receiving the electric output signal of the detector and providing an output signal when the amplitude becomes larger than a predetermined level; a waveform shaper for receiving the output signal of the sorter and converting respective pulse groups to single pulse outputs. The respective pulses from the sharper are judged to determine whether signal pulse in the present period is within a predetermined allowable range or not, and thereby determining whether respective pulses are "normal" pulses or not. The number of normal pulses per unit time are counted and displayed on a monitor.

Abstract: Two cascaded eight-bit maskable counters (62) and (64) provide a sixteen-bit output, for instance, to a digital-to-analog converter (10). Each of the counters (62) and (64) is a maskable counter that is operable to mask off a programmable number of the least significant bits therein. The next adjacent bit thereto comprises a virtual least significant bit. During the counting operation, the count is initiated at the virtual least significant bit such that the virtual least significant bit is clocked for each counting cycle. An initial value is first loaded into the counter (62) and (64) on a data bus (74). Thereafter, masked data is loaded into the counters (62) and (64) on the same data bus (74) to define the ones of the least significant bits that are masked off. In such a manner, the overall resolution of the counter can be varied without varying the clock rate to the counter.

Abstract: An uninterrupted event-time recorder enables high-precision measurements of the time-of-occurrence of randomly- and rapidly-occurring, digitally specified events such as the leading and/or trailing edges of asynchronous pulses. The lowest order binary digits of the recorder are constructed of high-speed synchronous integrated circuit counter devices. For an N-bit timer having M low-order bits, the highest order (N-M) bit counting is executed by two parallel (N-M)-bit slow-speed counters, one of which is incremented by the terminal count of the M-bit high-speed counter and the other which is incremented by the most significant bit (MSb) of the M-bit counter. The (N-M)-bit counters are read out through a multiplexer controlled by the MSb.

Abstract: Disclosed is a divide-by-m counter for generating an ouptut clock signal having a fifty percent duty cycle from a higher frequency source clock signal having m cycles for each single cycle of the output clock signal and wherein m may be an odd or even integer number, the divide-by-m counter including a modulo binary counter for counting up to a predetermined number, circuitry for presetting the modulo binary counter by another predetermined number, counter clock selector for providing a counter clock signal to the modulo binary counter which, when m is odd, will be either an non-inverted source clock or an inverted source clock based upon the occurrence of either the HIGH or LOW intervals of the output clock, and interval defining circuitry for defining the beginning of such HIGH and LOW intervals of the output clock based upon the occurrence of a ripple carry pulse from the modulo binary counter.

Abstract: A PWM waveform generator has a cycle timer for generating pulses at regular intervals, and a duty timer for generating a pulse of a program-selected duration after each pulse from the cycle timer. A register stores one bit of data which designates whether the PWM output starts high or low at the beginning of each cycle. The pulses from the cycle timer are fed through gates controlled by the register contents to the set and reset terminals of a flip-flop. Pulses from the duty timer cause the flip-flop to toggle. The starting level can be changed in any PWM cycle by rewriting the data in the register.

Abstract: An event counter has dual counting channels, each employing a ripple counter, and a timing generator supplying square wave switching signals of opposite phases to gates at the inputs of the two counters, the switching signals having a much greater periodicity than that of events to be counted, so that one, and only one, of the counters is counting at any one time. The timing generator also generates control signals to transfer a count from whichever counter is inactive to an associated latch and then reset the counter. When a counter is again enabled, the switching signal is also used to enable output from the latch of the previously stored count. This arrangement enables ripple counters to be used in an arrangement providing both continuous counting and continuous output availability.

Abstract: A two-modulus variable frequency-divider circuit comprises a variable frequency-divider, a plurality of .div.2 frequency-dividers succeeding the variable frequency-divider, and a monitor. Outputs of one or more of the .div.2 frequency-dividers are coupled to the monitor which develops a monitor output determined by the states of the .div.2 frequency-divider outputs applied thereto. The monitor output is fed back to the variable frequency-divider as a frequency dividing factor setting signal. The two-modulus variable frequency-divider circuit is further provided with a signal converting circuit having a signal inverting function, which can selectively invert, in accordance with an externally applied control signal, the output of the two-modulus variable frequency-divider circuit or the output of the final one of those .div.2 frequency dividers which provide the outputs thereof to the monitor.

Abstract: Apparatus for controlling the time constant of a signal includes an up/down counter for counting pulses of a clock signal. The count value is utilized as output signal. The output signal is compared with the input signal to provide a first control signal determinative of whether the counter counts up or down. The output signal is compared with the input signal offset by a constant value to provide a signal which is ORed with the first control signal, and the ORed signal is utilized to enable/disable the counter. Applying a constant offset value to the input signal to be compared precludes the system from alternately counting up and down by one unit value during intervals of relatively constant amplitude input signals.

Abstract: A scaler comprising a plurality of flip-flops, varies its frequency division to correct phase by 0.5 clock cycle. Each flip-flop is continuously and synchronously responsive to either a rising or a falling edge of the clock pulses. Normally, the scaler's state transits along one of two loops, which generate output pulses having identical repetition rates. When a control signal is applied, the scaler's state transits from one loop to the other, generating at least one output at an alternative repetition rate. The alternative repetition rate is either lower or higher than the identical repetition rate by an integral number of half cycles of the input clock pulses. Where there are two control signals, a lower or higher alternative repetition rate can be selected. Since the flip-flops are responsive to either edge of the clock pulses without clock gating interruptions, there is no jitter and the scaler's robustness is improved. Also the clock frequency can be effectively halved.

Abstract: A semiconductor integrated circuit constructed on a single chip. Either one of a signal inputted to a clock signal input terminal and a signal obtained by dividing the frequency of the clock signal inputted to the clock signal input terminal is selected by a selecting circuit responsive to a selection signal supplied from the exterior of the chip to be supplied to a control circuit. Consequently, the frequency dividing circuit can be bypassed in response to the selecting circuit. Accordingly, it is possible to easily provide operation at a high frequency exceeding the maximum operating frequency of component devices forming the semiconductor integrated circuit. This can be done by connecting an external circuit having the same function as that of the circuit bypassed and capable of higher-speed operation.

Abstract: An asynchronous ripple counter counts from a predetermined binary value to zero in response to an input clock signal. Zero detection logic is coupled to the ripple counter for detecting, from a most significant bit to a least significant bit of the ripple counter, when the counter has counted to zero. Both the counter and the zero detection logic receive and store the predetermined binary value. The monitoring of the ripple counter's digits from MSB to LSB prevents false detections of zero states in the ripple counter and allows the ripple counter to be extended to an arbitrarily large number of bits without sacrificing the maximum input clock frequency.

Abstract: A system for determining the position of movable machine parts including an incremental pulse generator for generating angular-speed pulses includes a computer. At least one counting circuit via which the incremental pulse generator is connected to the computer counts the generated angular-speed pulses.

Abstract: A vital microcompressor-based rate decoder for use in a vital processing system in on-board main line railroad and rapid transit automatic train protection systems; the design is such that a method is incorporated for tolerating specific kinds of signal disruption and in such a way that the probability of a wrongside failure has a calculable upper bound. A pickup coil transmits external or wayside signals to an arrangement which involves two channels and which provides period and duty cycle measurement of the pulses resulting from demodulation of the external signals. A counter is employed in each of the channels and a tolerance accumulation rate decoding device is included, the maximum amount of tolerance accumulated, and the minimum time required to accumulate it, being functions of the rate code selected.

Abstract: A machine position detecting apparatus according to the invention detects the absolute position of a machine by a pulse coder or the like attached to a movable element. Whenever the movable element of the machine is stopped, a check is performed to determine whether the detected position of the movable element is accurate. This is accomplished by a counter for counting the amount of shift of an absolute position detector circuit in one revolution based on a rotational position signal, and a collator for collating contents of the counting means with contents of position memory means and checking the stored contents of the position memory means when the movable element is stopped.

Abstract: The asynchronous time division multiservice satellite center can be used for connecting analog subscribers, digital subscribers, and asynchronous time division digital subscribers. It comprises multiservice concentrators that may be local (CBLA, CBLN, CBLNA, CBLOA), distant (CBEA, CBEN, CBENA, CBEOA), versatile local (CBLM), and versatile distant (CBEM), and a synchronous to asynchronous and asynchronous-to-synchronous converter (CAS), together with a multiservice control unit (UCB) including a multiservice switching network (RCB) and a control station (CS). The multiservice switching network is connected to the multiservice concentrators and to a parent exchange via multiplex links conveying cells, and it provides cell switching. The concentrators connected to analog subscribers or to digital subscribers cellulize and decellulize information therefor.

Abstract: An apparatus is described for the dual modulus prescaling of a high frequency signal. The apparatus comprises a dual modulus divider, second divider, synchronization circuit for providing a first modulus control signal to the dual modulus divider, and means for coupling the output of the second divider to the input of the synchronization circuit when a second modulus control signal is in a first state.

Abstract: A counter comprising n one-bit cells receiving a clock signal (CK0) having a frequency f to be counted and a read transfer order (TO). The lower rank p cells operate at the frequency f and the n-p higher rank cells at a frequency f/2.sup.p. The lower rank p cells (51-53) directly receive the clock signal (CK0) at frequency f and, if necessary, the transfer order (TO) synchronized in correspondence with CK0. The higher rank n-p cells receive as a clock signal at frequency f/2.sup.p, a signal (CK1) delayed by at least two periods of said clock signal CK0 and at the most by (2p-2) pulses CK0 with respect to the counting signal of the highest rank cell among the lower rank p cells.

Abstract: A method and device for evaluating signals of an incremental pulse generator for generating at least two mutually phase-shifted angular speed signals includes counting the angular speed signals only if a permissible combination of the angular speed signals is present.

Abstract: A logic analyzer has a counter/timer that can reconstruct the higher resolution with which data was acquired using multiple phases of the logic analyzer system clock signal. For a two-phase data sampling system, separate pairs of event recognizers monitor the data collected using the two phases of the system clock. Counter/timer control logic uses the information from these separate pairs of event recognizers to control the behavior of the counter/timer so that it can either single count or double count, depending on whether an event was true during both phases or only one phase of the data acquisition, thus allowing the counter/timer resolution to be as high as the information inherent in the data acquired using both clock phases. The counter/timer employed is capable of single or double counting and has two stages, a prescaler and an extension counter/timer, for increased power and cost effectiveness.

Abstract: A multi-stage M-bit binary counter is disclosed including S counter stages in which each counter stage includes an N-bit counter (M=S.times.N). During a test operation, the stages are decoupled for individual operation, a count value is loaded into the N-bit counter provided in each of the stages, and the N-bit counters of each stage are clocked 2.sup.N times to check independently the function of the N-bit counters. The stages are then coupled together to function as a multi-stage M-bit counter and a single clock pulse is supplied to the M-bit counter to check the carry propagation between stages. If the N-bit counters are of a type which only generate an output when fully incremented or decremented and the actually count value cannot be read from the M-bit counter, then the stages are decoupled together for a second time and the N-bit counters are clocked an additional 2.sup.N times.

Abstract: A first input section inputs a first signal serving as a trigger. A second input section inputs second and third signals having phases opposite to each other to set a time period width. A first data hold section obtains a first hold output in response to the first and second signals respectively output from the first and second input sections. A second data hold section obtains a second hold output in response to the first and third signals respectively output from the first and second input sections. A determination section determines whether the first hold output from the first data hold section or the second hold output from the second data hold section is output first. A selection section selects the second or third signal from the second input section in accordance with a determination result from the determination section.

Abstract: A preset counter apparatus for copying machines and the like having respective keys corresponding to digit positions of units and tens and a display for displaying numerical value in the digit positions of units and tens. The preset counter apparatus is so controlled that a value "0" is automatically displayed in the units digit position when the key corresponding to the tens digit is initially activated and that a value previously set in the units digit position is maintained as it is regardless of the posterior activation of the key corresponding to the tens digit.

Abstract: An analog/digital voltage controlled oscillator includes a voltage to pulse converter which responds to a control voltage to generate appropriate control pulses to change the mode of operation of a divider to thereby vary the output frequency of the oscillator.

Abstract: A circuit for generating clock and control signals from first and second asynchronous binary signals. The circuit generates first and second pulse signals responsive to the first and second asynchronous binary signals, a clock pulse signal responsive to the first or second pulse signal, and an identification control signal to indicate which of the two binary signals is responsible for the clock signal. The circuit is also responsive to the first and second pulse signals for generating an overlap control signal to indicate overlap in the first and second pulse signals.

Abstract: A digital logic circuit for use with an incremental positioning encoder is presented. The circuit converts two quadrature pulse train signals, generated by an incremental position type encoder, to a counting CLOCK signal and an UP/DOWN count signal. The signals are transmitted on counters to generate counting clock signal and the UP/DOWN count position information. The circuit utilizes gate delays to detect the edge of a pulse train signal. No external clocks or comparators are nested. The design, by relying on the propagation delay of gates, keeps the circuit simple and more reliable.

Abstract: A dividing mechanism for use in frequency synthesizers: comprising:a two modulus divider system having a first and second counter for providing respective programmable count totals A, M, and first counter being coupled to a dual modulus device providing moduli of n and n+1 whereby the two modulus divider system provides a division ratio of (Mn+A) for incoming signals:first and second input means for receiving first and second programming number signals N, Q, synchronization means for receiving a strobe signal from a further counter which provides a count total P, and logic interface means responsive to said first and second input means and said synchronization means to provide programming number signals A, M to said two modulus divider system, the logic interface means being such that in the absence of said strobe signal the two modulus divider system provides a count total C.sub.

Abstract: A two-phase encoder circuit for detecting a moving status of a moving article in accordance with first and second detecting signals which are input having a phase offset of 90 degrees and having repeated status of "H" and "L" according to the movement of said moving article, wherein the first detecting signal is taken in synchronization with a clock signal and an output received signal is sequentially output while a delay circuit having an input from at least the received signal outputs a delay signal more delayed than the received signal by less than one period of the clock signal, a pulse signal circuit having an input from at least the received signal outputs, a pulse signal in synchronization with an inversion of status of the received signal and the number of pulses of the pulse signal is counted while counted up or down according to the status of the delay signal with the counting operation being made when the second detecting signal has one status of ""H" and "L".

Abstract: Frequency counter-locked-loop apparatus for controlling digitally programmable oscillators includes an arrangement for locking the output frequency of the oscillator to an accurate frequency reference. Frequency, reference and delay registers, a counter and a comparator are configured in a feedback path from the output of the oscillator to its input for continuous control of the output frequency.

Abstract: A track counting circuit for an optical disk driver is disclosed. The pickup passing a track is detected through a differential amplifier receiving signals from photo diodes, an amplifier, a tracking processor, a positive zero crossing detector, and a negative zero crossing detector. The signals sensed by photo diodes are applied to one of the input terminals of each of a pair of NAND gates through a differential amplifier, level comparators and a flip-flop, and the other input terminals of the NAND gates receive the signals which are obtained by the signals sensed by the photo diodes being processed through an adder and a level comparator to distinguish whether the pickup is placed on the track or land of the disk, the output signals of the NAND gates controlling the output signals of a flip-flop which control an up/down counter to make an up/down count depending on the moving direction of the pickup on the track so that the intended track is found precisely and easily.

Abstract: A timeout circuit with internal calibration includes an oscillator (11) for generating an initial frequency for division by a modulo-n counter (20). The counter (20) receives the value of n from a calibration register (22) and divides the frequency of the oscillator by the value of n. A gate (26) prevents alteration of the contents of the register (22). The output of the counter (20) provides a calibrated frequency which is further divided by a day counter (32) for output to a countdown counter (34). The countdown counter (34) provides a predetermined countdown of the signal output by the day counter (32) and, at the end of the count, generates a Timeout signal. The predetermined countdown value is determined by a value stored in a register (36) which can be protected by a customer lock out circuit (42).

Abstract: A frequency of a signal, particularly a frequency, partly varied as time passes, of a signal is counted in real time by producing a delay signal by delaying the signal as much as a predetermined time, detecting delayed zero-cross pulses from the delayed signal, detecting zero-cross pulses from the non-delayed signal, counting a first number of the delayed zero-cross pulses after the predetermined time is over, counting a second number of the zero-cross pulses during and after the predetermined time, producing a number difference between the first number and the second number by subtracting the first number from the second number and halving the number difference. The predetermined time is designated longer than a half period of the signal frequency to be counted. When the predetermined time is set long, the average frequency of the signal is counted, and when that is set short comparing with the partly varied interval of the signal frequency, the partly varied frequency of the signal is counted in real time.

Abstract: A pulse generating circuit which, when a counting value of a counter and a value previously set at a register are coincident with each other, converts an output into the preset level to thereby generate each elementary pulse, and is provided with a register buffer for storing therein a value for defining the time, when the level of the pulse output is reconverted so that when the level of the pulse signal is converted, the stored value of the register buffer is set in the register through no software to thereby eliminate the influence on software processing with respect to the elemental pulse width, and is provided with a counter buffer for storing therein a counting start value to be set at the counter in addition to the above-mentioned construction so that the value is constructed to be desirably changeable to thereby enable the counting start value of the counter to be changeable each time the overflow occurs, thus enabling the cycle duration of the pulse signal to be changed with ease.

Abstract: A look ahead terminal counter and a method for generating a terminal count output signal are disclosed. The counter comprises a plurality of counter registers connected to counter enable circuitry for sequencing the registers at a predetermined counter rate. Terminal count enable circuitry is connected to the counter circuitry, e.g. at the input ports of the counter registers, and is operative to generate a terminal count enable signal when those input ports are at a predetermined state. The terminal count enable signal and clock signal are communicated to an output register operative to generate a terminal count output signal when a clock signal is received during the simultaneous presence of the terminal count enable signal.

Abstract: A multi-mode counter network and a method of testing the operation of the multi-mode counter network are disclosed. The multi-mode counter network comprises a counter circuit formed of a plurality of counter registers and a multiplexer circuit formed of a plurality of multiplexers wherein said multiplexers are connected to and associated with one of the registers and are operative to selectively vary the input signal communicated to the associated register such that the registers operate in one of a plurality of operational modes. By controlling the selection of the input signal communicated to the registers the network may be alternately configured to perform traditional counting functions or may be configured to provide a serial signal path for communicating a test pattern through the registers and multiplexers to test the operation of the multiplexers and registers. The test pattern is communicated through the circuit, bypassing counter enabling circuitry, and thus independent of the network counter rate.

Abstract: An improved duty cycle timer provides a duty cycle control signal having alternate "on" and "off" intervals of different logic states. The timer utilizes integrated circuitry having first and second independent clock sources respectively driving first and second multistage, binary counters. One counter measures the "off" interval and the other counter measures the "on" interval. Each counter provides a signal representative of the completion of the interval which it measures, and that signal is connected to a resetting input of the opposite counter for initiating the measuring interval of that opposite counter. Typically, one interval is longer than the other. The duty cycle control signal is provided by the output of one of the counters. In an illustrated embodiment, the duty cycle timer controls operation of a defrost mechanism for a refrigeration circuit and the "off" interval is longer than the "on" interval.

Abstract: A circuit for providing an indication of watt-hours from a voltage input that is an analog of watts comprises a source of a high-frequency square wave and a precision triangular wave at a frequency that is derived from the high-frequency square wave by frequency division. A time interval is derived by selecting a period between a time when the triangular wave crosses zero volts and the time at which the amplitude of the triangular wave equals the analog input voltage. A count of the number of cycles of the high-frequency signal during that interval provides a measure of the value of the input voltage, and a continuing count of that number of cycles provides a time-integrated value of the count. When the input signal is analogous to watts, the integrated output provides a measure of watt-hours.

Abstract: A high speed, low power, multi-bit, single edge triggered, wraparound binary counter is provided which is resettable and loadable from a user-supplied address. The binary counter requires a relatively small amount of power due to the use of CMOS technology for construction of its circuitry, may be initiated at any of 2.sup.N (where N=bit count) start locations, and can be easily adapted to accommodate any desired number of counter cells. Further, it is capable of operating over wide ranges of temperatures and power supply conditions. The high speed binary counter is formed of a plurality of counter cells in which each counter cell includes a pass gate device responsive to a counter-update signal for allowing true and complement addresses to control a switching device when the counter-update signal is in the low state and for isolating the true and complement addresses from the switching device when the counter-update signal is in the high state.

Abstract: A divider-by-factor frequency divider circuit is described. The rate-multiplier principle of eliminating pulses as regularly as possible from a number of pulses of the signal to be frequency-divided is modified so that low-frequency variations in the frequency-divided signal are reduced at the expense of an increase in higher-frequency variations. This modification is achieved through the addition of a second accumulator, a pair of adders, a subtracter and a presettable counter to the accumulator of a frequency divider circuit. A rate multiplier with a coloring characteristic inverse to pink noise is thereby obtained.

Abstract: An electronic integrator for integrating a linear voltage signal utilizes a voltage-to-frequency converter for converting the voltage to input frequency. A binary counter counts pulses of the input frequency. The binary counter generates a first operating frequency which is applied to a scaling circuit and another calibration frequency which has a much higher rate than the operating frequency. Both, however are proportional to the input frequency. The scaling circuit scales the operating frequency to a selected extent to form a counting signal. Using the double pole switch, either the calibration frequency or the counting frequency are applied to a pulse counter which is either used to integrate the input voltage signal by counting up pulses of the scaled counting signal, or the integrator can be calibrated using the calibration frequency which quickly increments the pulse counter.

Abstract: A liquid crystal display device comprises first and second substrates coated on the inner surfaces thereof with electrodes, at least one of said first and second substrates including an extended portion thereof with projects beyond the edge of the other of said substrates, a sealing member disposed around the periphery enclosing liquid crystal material and sealing between the substrates, input conductors disposed on the inner surface of said extended portion and electrically connected to said electrodes, a plurality of driving integrated circuit chips mounted on the inner surface of said extended portion and electrically connected to said input conductors, including a plurality of pairs of input terminals thereof electrically connected, one input terminal constituting each pair is arranged in the reverse order on one side of a reference line with respect to the other constituting the pair on the other side of a reference line, metal film conductor formed on the inner surface of said extended portion and conne

Abstract: A multi-purpose register formed of various cells of a customized integrated circuit gate array chip having input gate cells, multiplexor cells, flip-flop cells and output gate cells. The flip-flop cells may be segmented into registers of different widths or may be employed as individual flip-flop cells depending upon the mode in which the register array is to be employed.

Abstract: An up-down counter is fed pulses generated manually and/or automatically from either or any of two or more command sources. Gating circuitry ahead of the up-down counter may be used to enable counts from only one source at a time. The output of the counter represents the magnitude of the parameter to be controlled. The purpose is to transfer control of a parameter to any of several command sources without changing the value of the parameter, thereby achieving "stepless" switching. Only one counter is needed regardless of the number of command sources, no synchronizing circuitry is required, and switching is provided with no steps or delays. Multiple command sources may be active simultaneously when command source input gating is not used ahead of the up-down parameter magnitude counter.

Abstract: An up/down counter interface converts input information suitable for the operation of one type up/down counter, which type receives input information in the form of a direct current logic signal indicating direction and a train of electric pulses representing increments of information, to input information suitable for the operation of a second type up/down counter, which second type receives input information in the form of two identical pulse trains representing increments of information, direction being determined by the relative displacement in time of the two pulse trains.

Abstract: A gating arrangement for a pulse compression circuit includes a surface acoustic wave delay line SAW responsive to an input pulse to generate a frequency-modulated radio-frequency output signal which is applied to an output gate OG. The output signal is also applied to circuit means DC operable to product a digital pulse corresponding to each cycle of the output signal. The pulses are counted by a counter CT and applied to control means CM. This responds to first and second predetermined counter states to control the operation of the output gate OG.

Abstract: A self-arming, prescaling frequency counter system comprises an armable frequency counter, an envelope detector, a prescaling pulse-shaper, and a delaying means. The envelope detector detects occurrence of an oscillating signal to be frequency measured and transmits an arming signal to arm the frequency counter for the duration of the oscillating signal. The prescaling pulse-shaper is coupled to receive the oscillating signal burst and generate a pulsed test signal of frequency an integer fraction of the oscillating signal frequency. The delaying means couples the test signal to the armable frequency counter input, delaying receipt of the pulsed signal burst until after the counter is armed, and delaying termination of the pulsed signal until after counter is disarmed.

Abstract: A circuit detects that a plurality of signals are generated in a predetermined sequence. The plurality of signals are applied to address terminals of a memory which has stored therein a predetermined pattern, and a divide-by-N counter (N:positive integer) counts a first data output signal from the memory N times and applies a carry output signal generated as a result thereof to another address terminal of the memory. An output signal of the circuit is derived from a second data output terminal of said memory when the plurality of input signals occur in the predetermined pattern of the memory and the carry signal from the counter is applied to the memory.

Abstract: An n stage array of gas discharge chambers is divided into m groups of y stages each. Priming arrangements are provided whereby serial readout of the stages in each group can be accomplished simultaneously thereby increasing the speed of readout.

Abstract: A multibit counter circuit uses a plurality of essentially identical stages which each have a feedback circuit, a flip-flop, and a carry circuit. Each of the stages is connected together in essentially the same way. A counter circuit of any desired bit capacity can be relatively quickly and easily formed with a saving in silicon area compared to standard configurations.

Abstract: The counter circuit is adapted to counting high frequency pulses and to being read while counting said pulses. It comprises a plurality of pulse counting stages of increasing numerical significance, and read means for reading the states of said stages. Said plurality of pulse counting stages comprises lower significance stages (10.sub.1 to 10.sub.4) connected as a synchronous counter (10) and higher significance stages (12.sub.1 to 12.sub.n) connected as a ripple counter (12). The synchronous counter is so connected that it counts the high frequency pulses (H) directly, and that any change of state required in any of its stages on counting a pulse occurs substantially simultaneously with the arrival of said pulse. The ripple counter is so connected that it counts count cycles of the synchronous counter, and that it takes a long time relative to the interval separating two successive high frequency pulses for a change of state to propagate, where necessary, from the least significant stage (12.sub.