Abstract: An integrated circuit that includes a generating circuit is described. During operation, the generating circuit may provide an edge clock having a target phase within a clock period of an input clock, where the generating circuit does not include a delay-locked loop (DLL). For example, the generating circuit may include a gated ring oscillator that provides a reference clock having a first fundamental frequency that is larger than a second fundamental frequency of the input clock. Note that the gated ring oscillator may be programmable to adjust the first fundamental frequency within a predefined range of values. Moreover, the generating circuit may include a control circuit that determines a reference count of a number of edges of the reference clock within a reference period of the reference clock.

Abstract: An integrated circuit that includes a generating circuit is described. During operation, the generating circuit may provide an edge clock having a target phase within a clock period of an input clock, where the generating circuit does not include a delay-locked loop (DLL). For example, the generating circuit may include a gated ring oscillator that provides a reference clock having a first fundamental frequency that is larger than a second fundamental frequency of the input clock. Note that the gated ring oscillator may be programmable to adjust the first fundamental frequency within a predefined range of values. Moreover, the generating circuit may include a control circuit that determines a reference count of a number of edges of the reference clock within a reference period of the reference clock.

Abstract: An integrated circuit that includes a generating circuit is described. During operation, the generating circuit may provide an edge clock having a target phase within a clock period of an input clock, where the generating circuit does not include a delay-locked loop (DLL). For example, the generating circuit may include a gated ring oscillator that provides a reference clock having a first fundamental frequency that is larger than a second fundamental frequency of the input clock. Note that the gated ring oscillator may be programmable to adjust the first fundamental frequency within a predefined range of values. Moreover, the generating circuit may include a control circuit that determines a reference count of a number of edges of the reference clock within a reference period of the reference clock.

Abstract: According to an embodiment, a magnetic storage device includes a magnetic member, a switch element, a shift control circuit, a base current control circuit, and a controller. The magnetic member includes a portion extending in a direction. The switch element is connected in series to the magnetic member, and maintains an on state in a case where a current equal to or larger than a holding current value continues to flow in the on state. The shift control circuit shifts magnetic domains retained in the magnetic member. The controller causes the base current control circuit to supply a base current to the switching element and causes the shift control circuit to supply a shift pulse current a plurality of times.

Abstract: A hybrid counter generates a multi-bit hybrid counter value. The hybrid counter includes two or more asynchronous counters, each configured to generate a subset of the bits of the multi-bit hybrid counter value. The asynchronous counters are interconnected by a logic gate and a clock gating circuit. The logic gate generates an asynchronous logic value based on the bits generated by the previous asynchronous counters. The clock gating circuit re-times the asynchronous logic value to generate a synchronous logic value that is used to toggle the next asynchronous counter. The hybrid counter functions more accurately than conventional asynchronous counters and with less power than conventional synchronous counters.

Abstract: A driver circuit outputs a result of classifying and counting photons based on one or more energy levels to a column line. The driver circuit includes a multiplexer for receiving the result from a counter, a driving inverter for receiving a signal from the multiplexer and a power supply, and a switch connected between the power supply and an input terminal of the driving inverter.

Abstract: An addressing type frequency counter circuit is disclosed, which receives a multiple parameter and a clock of addressing input from an external circuit, and uses a hardware address to perform the addressing operation for outputting a clock value, thereby utilizing memory more efficiency, reducing the cost by purchasing less memory to achieve the same performance, and improving integration of the addressing type frequency counter circuit.

Abstract: A pulse signal processing circuit, a parallel processing circuit, and a pattern recognition system including a plurality of arithmetic elements for outputting pulse signals and at least one modulation circuit, synaptic connection element(s), or synaptic connection means for modulating the pulse signals, the modulated pulse signals then being separately or exclusively output to corresponding signal lines.

Abstract: An asynchronous counter that is capable of switching count mode includes flip-flops, and three-input single-output tri-value switches respectively provided between the adjacent pairs of the flip-flops. The tri-value switches switch among three values, namely, non-inverting outputs and inverting outputs of the flip-flops and a power supply level. Each of the tri-value switches switch among the three input signals according to two-bit control signals, and input a selected signal to a clock terminal of a subsequent flip-flop. When count mode is switched according to the control signals, a count value immediately before the mode switching is set as an initial value, and counting after the mode switching is started from the initial value.

Abstract: A machine used for digital counting which can provide multiple output counts. The machine is particularly useful in analog-to-digital (A/D) converters and in digital-to-analog (D/A) converters. The multiple output counts can change in different directions or in the same direction, and are generated using shared circuitry. The invention exploits properties of counting systems to allow A/D and D/A conversions in convenient digital number formats or in multiple different formats. The invention can be used in integrating converters to help eliminate errors such as comparator offset and dielectric absorption while converting and to increase the conversion rate.

Abstract: Methods and systems for automatic generation of an at-speed binary counter are described. The binary counter includes a slow counter that increments when a fast counter overflows to keep up with a fast clock. A framework to automatically generate a Hardware Description Language (HDL) for an at-speed binary counter is also described.

Abstract: A system and method are presented for providing a multi-stage counter. In one embodiment, a signal propagates from the most significant bit of the counter to the least significant bit of the counter that indicates that all “more significant” stages of the counter have reached a limit value (e.g., all 1's). Use of this propagating signal means that only the first (or first couple) stages of the counter are time critical, while the remainder are less so. The described counter may have a modular design and may result in lower power consumption.

Abstract: A shared counter performs multiple counting functions in an electronic circuit, such as a memory integrated circuit. An input selection circuit selects one of M input data sets at a given time to be provided as counter initialization data. A counter circuit provides counter output data based on the counter initialization data. An output circuit provides the counter output data to K destination circuits in the electronic circuit. The output circuit provides only one of the K destination circuits with the counter output data at a given time.

Abstract: There is disclosed a loop counter reload circuit loads an initial count value into a counter and a shadow register. A count value output from the counter is changed by a predetermined displacement resulting in a changed count value. The count value from the shadow register is loaded into the counter if the changed count value has reached a predetermined reference value, and otherwise the changed count value is loaded into the counter.

Abstract: A shared counter performs multiple counting functions in an electronic circuit, such as a memory integrated circuit. An input selection circuit selects one of M input data sets at a given time to be provided as counter initialization data. A counter circuit provides counter output data based on the counter initialization data. An output circuit provides the counter output data to K destination circuits in the electronic circuit. The output circuit provides only one of the K destination circuits with the counter output data at a given time.

Abstract: An asynchronous reading circuit improves reliability of data read from a binary counter. Count data generated by a binary counter 101 according to a counting clock is converted into a gray code by a gray encoder. The count data represented by the gray code is sampled by a sampling circuit according to a timing signal asynchronous with the counting clock. The sampled count data is decoded into binary count data by a gray decoder.

Abstract: Circuitry is provided that allows a register without an asynchronous loading capability to be asynchronously loaded. Logic gates are provided before and after the register. The logic gates are driven by an output signal from a storage circuit such as a latch. When the output signal has one value the logic gates act as non-inverting buffers. When the output signal has another value the logic gates act as inverters. The circuitry allows the normal synchronous operations of the register to be maintained. A hazard coverage circuit can be provided to prevent glitches from appearing at the output during asynchronous operations. The logic gates may be formed from exclusive OR gates implemented in programmable logic on a programmable logic device.

Abstract: A burst address sequence generator includes a counter, a latch and an exclusive-OR gate. The counter is controlled by a mode signal for generating count values. The latch generates pre-address signals. The count values and the pre-address signals are received by the exclusive-OR gate generate a burst address sequence.

Abstract: A synchronous counter performing a count operation in response to an input of a clock having a fixed frequency. The synchronous counter including a first transmission gate receiving a counter initialization signal and transferring the counter output signal to a carry output node when the counter initialization signal is received during a time period in which the external address signal is not received, and a second transmission gate receiving the counter initialization signal and transferring an address signal to the carry output node when said counter initialization signal is received during a time period in which the external address signal is received.

Abstract: A sector pulse generating apparatus for multiple zone recording includes only first and second counters. The first counter counts reference clock pulses and outputs a present position signal. The second counter is incremented in response to a increment signal and outputs a next sector number signal. A first register stores the sector length of a zone in which a head is located. A multiplier outputs a next sector position signal representative of a multiplication of the next sector number and the sector length. A first comparator compares the magnitude of the present position and the next sector position. When the present position and the next sector position match, a sector pulse generating device generates a sector pulse and a first increment device outputs the increment signal.

Abstract: An N+1 frequency divider counter (20) has a binary counter (22), ones detect circuitry (26), control logic (24), and an output flip-flop (28). The binary counter (22) counts from an initial value to a final value for each half of an output clock signal. If N+1 is an even number, one full cycle is added to each half cycle of the output clock signal. If N+1 is an odd number, one-half of a cycle is added to each half phase of the output clock signal. At the final count value, the control logic (24) causes the output clock signal to transition on either the rising edge or the falling edge of an input clock signal. The N+1 counter (20) has a fifty percent duty cycle for all count values of N, and does not require additional circuitry to accommodate when N equals zero.

Abstract: In a signal selecting device, a mode determination portion 61 comprises a shift register 11, a clock generating portion 20 and decoder 51. The clock generating portion 20 receives a mode signal M and generates a clock signal CK1 used for decoding the mode signal M from a system clock SYS. The shift register 11 receives the mode signal M and the clock signal CK1 and outputs signals Q.sub.0 to Q.sub.3. The decoder 51 receives the output from the shift register 11 and outputs control signals S.sub.00 to S.sub.03. Therefore, there needs only one terminal for receiving the mode signal M and no terminal for receiving a clock.

Abstract: An input clock delay circuit includes an up counter for estimating the approximate number of internal clock cycles that occur during one cycle of the input clock signal and another up counter for determining the portion of each cycle of the input clock signal that is high. A clock manipulation circuit receives each counter's value, and may be set to perform a fixed transform on the input clock signal, such as clock delay/advance, duty cycle shifting, and frequency multiplication/division. The clock manipulation circuit output values are loaded into two down counters that are also clocked by the internal clock. On the rising edge of the input clock signal, the first down counter starts decrementing until the counter reaches zero, indicating that the desired delay interval has passed, at which point the delayed output clock signal is taken high. The second down counter then starts decrementing for an interval that is equal to the desired duty cycle of the output clock signal.

Abstract: A device for printing an image onto a surface, such as food containers, employs a laser that is scanned across a surface to produce a latent image on a charged photosensitive surface formed on the surface. The surface is moved relative to the laser source while the laser is activated and deactivated according to a pattern of signal pulses from a control circuit. The device thus forms a raster image. To form very fine images, the control circuit must produce pulses with very small steps in duration. The control circuit of the present invention divides a digital value representing a duration of firing of the laser into high and low order bit sequences. The high order bits, representing a value M, are applied to a counter that generates a first pulse M clock cycles long. The low order bits and the first pulse are applied to a delay circuit. The delay circuit generates a delayed version of the first pulse, which is delayed by an amount represented by the low order bits.

Abstract: A comparator is provided in the counter circuit to compare the counted value of clocks by a counter with the value of a register in which a target changing value of a comparison register which sets a value to be compared with the counted value of the counter is set. The value of the register is set in the comparison register when the counted value of the counter does not reach the set value of the register, whereas the value of the register is not set in the comparison register if the counted value does not reach the set value of the register, but the value of the comparison register is turned changeable at the desired timing while the counted value of the counter is being compared with the set value of the comparison register.

Abstract: The device comprises a switched-mode power supply (1) equipped with an electronic switching member (T.sub.1), the closing of which controls the power supply to an inductor (L.sub.1) which discharges, when the member reopens, into a capacitor (C.sub.1) at the terminals of which the output voltage of the device appears, characterized in that it comprises (a) storage means for recording a sequence of image numbers of successive segments of the predetermined waveform, (b) a clocked digital counter (2) and (c) means (3) for successively loading this counter (2) with each of the numbers of this sequence considered as a bound of the count performed by the counter (2), the latter cyclically controlling the closing of the switching member (T.sub.1) for a predetermined time interval, each time the count performed reaches the limit thus fixed.

Abstract: A reference signal generator that operates in response to a digital control signal has an increased resolving power without the requirement for increasing the basic clock rate or increasing the bit capacity of a down counter by thinning a pulse from the basic clock signal each the down counter overflows so as to adjust the down-counting clock rate of the down counter. The down counter counts the higher-bit data of the digital control signal. The basic clock signal is multiplied by a decoded signal to obtain the adjustment of the down counting clock signal. The decoded signal is obtained by counting the overflow pulses from the down counter and decoding the counter output with the lower-bit data of the digital control signal.

Abstract: A pulse generator has a presetting clock synchronous counter having a count enable terminal, the counter which counts up input data using a clock signal whose basic unit of time width corresponds to its one period. The output from said counter is decoded to produce a first state signal. A second state signal is produced from said clock signal and a count enable signal for said counter. An output pulse having a desired pulse width is obtained by calculating the logical product of said first and second state signals.

Abstract: A data coincidence detecting circuit including a register for receiving n-bit data, a counter for counting up until 2.sup.n to compare the n-bit data with it, a comparator for comparing the outputs of the register and the outputs of the counter, respectively to generate a coincidence detecting signal, a mask portion connected to the output of the comparator for masking the period from a time point when the n-bit data is input to a time point when the input of data ends, and a logic circuit for logically adding the output of the mask portion and the output of the comparator to output the result.

Abstract: A clock control apparatus having a basic period clock and a plurality of clocks with different phases from the basic period clock by t/N period, is used with an information processing unit.

Abstract: A reload-timer/counter circuit provides a reload-timer function and a counter function commonly and selectively. The circuit is comprised of first, second, third, and fourth registers. The third and fourth registers act as a control status register and a mode register, respectively. The first and second registers act as, in the reload-timer mode a data register and a counter register, respectively, while in the counter mode, the first and second registers act as the counter registers.

Abstract: A data compressor generates codewords representative of the location and length of a string match between an input data stream and a CAM array vocabulary table. A data decompressor looks up the codewords for a string match in its vocabulary table. The CAM array is arranged in a serpentine configuration to reduce track layout. A column priority encoder reverses the priority of alternate rows to maintain the logical flow through the CAM array. The CAM array uses a flipflop with a common control circuit to transfer data through the flipflop. When the data compressor is reset, the CAM array may locate matches in the unused portion which are interpreted as the reset character. A barrel shifter in the data compressor converts variable length codewords into fixed length for transmission. A barrel shifter in the data decompressor converts fixed length codewords back into variable length for decoding into the vocabulary table.

Abstract: A circuit for initializing the output voltage of an analog circuit includes a switch operative to connect an input of the analog circuit to a first reference potential during an initializing period. A comparator is connected to compare the output voltage of the analog circuit with a second reference potential to produce an output representing the comparison. A resistor ladder having a plurality of voltage step output lines along its length is connected to inputs of a multiplexer, the multiplexer having an output connected to bias the analog circuit. A counter having a clock input and a count output is connected with the count output connected to operate the multiplexer to sequentially select among the steps of the resistor ladder. A circuit clocks the counter until the output of the comparator reaches a predetermined value, wherein a voltage step output line of the resistor ladder is selected to control the output of the multiplexer.

Abstract: The invention provides a pulse generating circuit including a single timer or counter which conducts both a event base count and a subsequent time base count according to clock signals about the event and time base counts, any one of which is selected by a selector. A pulse signal is generated from a RS flip-flop circuit. When the time base count follows the event base count, during the event base count, the output signal from the flip-flop is a 0 signal. During the time base count, the output signal from the flip-flop is a 1 signal. The event base count defines a delay of a pulse generated from RS flip-flop circuit and the time base count defines a width of the pulse.

Abstract: Utilization circuits, such as logic chip circuits, are prevented from receiving the initial one or more pulses of a train of clock pulses produced after the master system clock is started, while the pulses of that train occurring thereafter are coupled to the utilization circuit. This prevents the skew usually present between the initial pulses of the train relative to the subsequent train pulses from adversely effecting operation of the utilization circuits. This clock swallowing preferably blocks a certain predetermined number of initial clock pulses from reaching the rest of the circuitry, although the system is adaptable to allow preselection of the number of such swallowed pulses.

Abstract: In the transmission of variable length data blocks, where data and addresses share the same bus lines, one of the other signals, which are present anyway (chip-select, CS-, read, write), indicates the block length. The first time slot following the setting of this signal is designated for an address (starting address), all subsequent time slots are designated for data, until the signal is reset. In this way, the length of the data block need not be known at the beginning of the transfer.

Abstract: According to one aspect of the invention, an apparatus includes a first processor coupled to a first system bus to provide data to a cache and a memory, and a second processor coupled to the first system bus and a second abbreviated system bus to receive read data from said first system bus. In accordance with a further aspect of the invention, an apparatus includes means for correcting errors in memory. In accordance with a further aspect of the invention, an apparatus includes a number of computing systems each including a memory device mounted on an infrequently replaced hardware unit, and capable of communicating with the number of computing systems. In accordance with another aspect of the invention, an apparatus includes a counter, means for detecting a selected state of said counter, and means, responsive to output signals from said counter, for selectively permitting or inhibitting transfer of data fed to a recirculating state device.

Abstract: The invention concerns a device for indicating the presence of optional components (01-04) that can be inserted on a microprocessor board, each component having a first pin (10) associated to a first contact (11) of the board connected to a first voltage corresponding to a predetermined logic state (0), the device comprising analyzing means (3) of each of the logic states present on specific lines respectively associated to the optional components. Each optional component has a specific pin (12) connected inside the component to said first pin (10) and associated to a second contact (14) of the board connected to the corresponding specific line.

Abstract: A frequency divider state machine synchronously divides an input clock's frequency by 1.5. The clock divider circuit includes two storage elements which are clocked on different edges of the input clock signal. The outputs of the two storage elements are combined together using combinatorial logic, the results of which are provided back to the inputs of the two storage elements. Further, the two outputs of the memory storage elements are combined together to provide the desired output frequency. Preferably, the circuit is designed such that if either of the two memory storage elements powers up in an undesired state, the divide by 1.5 circuit will automatically transition to one of the desired states and continue to provide the output frequency at the desired divide by 1.5 clock frequency after the initial transition. The circuit can be implemented as a digital circuit in an ASIC, an LSI, or the like.

Abstract: A display driving circuit includes a latch circuit provided with a resetting terminal for receiving a pulse signal having a constant period and a setting terminal, a logic product circuit for receiving an output signal of the latch circuit and the pulse signal, a counting circuit having a resetting terminal for receiving an output signal of the logic product circuit and a counting terminal for receiving a clock signal, the counting circuit outputting a data pulse every time a number of pulses of the clock signals reaches a preset constant value from a reception of the output signal of the logic product circuit; and a shift register for receiving the data pulse of the counting circuit at a data signal input terminal thereof and receiving the clock signal at a clock input terminal thereof, the latch circuit being adapted to receive the data pulse of the counting circuit at said setting terminal thereof.

Abstract: A pulse counter has a programmable prescaler that divides the frequency of an input clock pulse signal by a factor designated by a code signal. A counter counts the prescaled clock pulse signal output by the programmable prescaler to generate a count output. A code generator encodes the count output to generate the code signal that controls the programmable prescaler.

Abstract: A circuit configuration includes k linking cells each generating one of k output states from two of k input states. Each of the linking cells have two counters. Each of the counters have a serial data input, a serial data output, and a serial counting width input. The counters increase a counter state loaded through the data input and represent the respectively assigned input state by a value input through the counting width input. Comparators are each connected to the data outputs of two of the counters for serially comparing the two counter states with one another. Multiplexers are each connected to the data outputs of two of the counters for outputting one of the two counter states as an output state under the control of the comparator.

Abstract: In a capstan servo circuit, a waveform shaping error which might occur while shaping the waveform of an FG signal is suppressed to control the speed of a capstan motor stably. An FG signal from a frequency generator mounted on the shaft of the capstan motor is shaped in waveform by an amplifier and a comparator and is multiplied to double its frequency by a multiplier. The multiplied FG signal is inputted to an FV counter where the time from a rise to a subsequent fall of the waveform-shaped FG signal and the time from a fall to a subsequent rise of the same FG signal are counted. The count values are latched in order by two levels of latch circuits. The N-bit count values latched are inputted to an adder where a mean of the two count values is calculated by outputting the upper N bits and is supplied to the capstan motor as a servo signal.

Abstract: An n-bit input count value is split into high-order n-1 bits and a low-order one bit so that the overflow signal 3a of the n-1 bit counter 2 for counting the high-order n-1 bits and the output signal 4a which is obtained by delaying the overflow signal 3a by half the cycle of the input clock by means of the delay circuit 4 are switched by the switch circuit 5 according to the low-order bit stored in the 1-bit register 6 to achieve a signal having a minimum decomposition width which is half the cycle of the input clock 7a.

Abstract: A pulse generating circuit equipped with a data register (17) in which there are stored data to designate output terminals (14a to 14m) which generate output pulses and data to define the output states of the output terminals (14a to 14m). Also included in the pulse generating circuit is a decoder (16) for decoding the contents of the data register (17) to output the decoding result to a port latch (15) having the output terminals (14a to 14m), so that one selected from the output terminals (14a to 14m) generates the output pulse.

Abstract: A high resolution digitally controlled oscillator is in the form of a digital frequency divider, which uses calculation logic to utilize both the rising edge and the falling edge (start edge and stop edge) of the input clock pulses to provide the capability of alternating between two adjacent frequencies. This results in significantly improved resolution, since the division ratio is not dependent upon any integral number of clock periods.

Abstract: A digital counting method and device for evaluating a digital signal (S.sub.S) using a digital counter (Z) applies the digital signal (S.sub.s) that is received by the input (ZE) of the digital counter (Z) as an output signal (N+1) to represent another binary position, in addition to the output signals (N) from the digital counter (Z).

Abstract: A data detector comprises a counter having a plural-bit parallel output, compensation means for compensating a shift of output times of a low order bit and a high order bit of the counter caused by a carry signal from the low order bit to the high order bit, and detection means for detecting data of the low order bit and the high order bit of the counter compensated by the compensation means.

Abstract: The present invention (50) corrects duty-cycle errors generated by imperfections in encoder scales and encoder detectors. A preferred embodiment of the invention operates by detecting successive transparent-to-opaque transitions of the encoder scale (20), calculating the distance between the transitions, dividing that distance by two, and generating a synthetic encoder pluse that is timed to represent a position 50 percent of the distance between the transparent-to-opaque transitions.

Abstract: A circuit arrangement generates a preset number of output pulses each time between two consecutive input pulses, the distance between the input pulses being subject to variation. The output pulses should be approximately evenly distributed, which even distribution, however, cannot be maintained when the cycle of the input pulses changes. To achieve first and foremost that the total number of output pulses is reached as quickly as possible in the case of a change in the input pulse cycle, the circuit includes a first counter device, which supplies a measure for the cycle duration of the input pulses in relation to a clock pulse, and this measure is used as a preset value for the next cycle for a further counter, which counts down the preset value in period with the clock pulses.