Abstract: Systems and methods for resonance aware performance management of processing devices. In one aspect, a method includes iteratively testing a performance operation for the processing device, wherein each iteration is performed at an iteration voltage level for a power delivery network. The performance operation is applied at different application periods and at the iteration voltage level for the iteration. If not failure condition is met, the iteration voltage is reduced and another iteration is done. Upon a failure occurring at a particular application period, an operational voltage level for the power delivery network that is based on the iteration voltage level for the iteration in which a failure condition was induced is selected, and application of the performance operation at the particular application period is precluded.

Abstract: An image sensor may include an array of imaging pixels and row control circuitry that provides control signals to the array of imaging pixels. In order to enable the row control circuitry to provide control signals to the array of imaging pixels that have a voltage greater than the power supply voltage, the row control circuitry may include voltage booster circuitry. The voltage booster circuitry may include two amplifiers and may be operable in three different modes. In the first mode, only the second amplifier may be enabled and the output voltage may be between 0V and 2.0V. In the second mode, both the first and second amplifiers may be enabled and the output voltage may be between 2.0V and 2.8V. In the third mode, only the first amplifier may be enabled and the output voltage may be between 2.8V and 4.0V.

Abstract: Apparatus and methods for a MOS varactor structure are disclosed. An apparatus is provided, comprising an active area defined in a portion of a semiconductor substrate; a doped well region in the active area extending into the semiconductor substrate; at least two gate structures disposed in parallel over the doped well region; source and drain regions disposed in the well region formed on opposing sides of the gate structures; a gate connector formed in a first metal layer overlying the at least two gate structures and electrically coupling the at least two gate structures; source and drain connectors formed in a second metal layer and electrically coupled to the source and drain regions; and interlevel dielectric material separating the source and drain connectors in the second metal layer from the gate connector formed in the first metal layer. Methods for forming the structure are disclosed.

Abstract: The driving device includes an applied voltage control unit configured to perform a transfer process of controlling a charge-coupled device to transfer electric charges. The applied voltage control unit is configured to switch, in order from a first end to a second end of a line of transfer electrodes of the charge-coupled device, a voltage applied to the transfer electrode from a control voltage for forming a potential well to a reference voltage for eliminating the potential well. The applied voltage control unit includes a control circuit configured to generate a driving signal based on a clock signal, and a driving circuit configured to apply the control voltage and the reference voltage selectively to the transfer electrode in accordance with the driving signal.

Abstract: A charge transfer circuit, such as a charge coupled device or other bucket brigade device, which incorporates an amplifier to assist with charge transfer.

Abstract: Disclosed is a CCD device in which a charge transfer register of a CCD structure is connected to a charge detector via an output gate and has a reset gate between the charge detector and a reset drain, and an output gate pulse opposite in phase from a reset pulse applied to the reset gate is applied to the output gate. A dummy charge detector and an amplitude adjusting circuit are provided. On the basis of detection of the potential of a diffusion layer in the dummy charge detector, the amplitude adjusting circuit controls the amplitude of the output gate pulse applied to the output gate.

Abstract: A charge recycling integrated circuit and a method for integrated circuit charge recycling. In one aspect, a charge storage collector is interposed between a high voltage supply or a low voltage supply and a function block of the integrated circuit. The charge collector is operable to selectively store a charge dissipated in the function block when the logic circuitry of the function block switches between a high voltage value and a low voltage value. The dissipated charge resulting from the switching in the logic circuitry of the function block is selectively stored to the charge collector and the charge collector selectively returns the charge stored on the charge collector to the high voltage supply, the low voltage supply or to another node in the integrated circuit as appropriate.

Abstract: A multiplication register for use in solid state imaging apparatus, such as a CCD, is described. The multiplication register has a gain element 22 comprising a plurality of register electrodes 30, 32, 34, and 36, for transferring charge along a change transfer channel, and for amplifying the charge. Channel edge defining electrodes 24 and 26 are disposed either side of the channel 28, in place of channel stops, removing the effects of spurious charges generated in the channel in the regions of amplification. The provision of the channel edge defining electrodes 24 and 26 allows the resulting structure of the channel electrodes to be made simpler, and means that a structure can be provided for clocking and amplifying charge in either direction along the channel.

Abstract: A shift register having a plurality of stages for shifting a start pulse and outputting a shifted start pulse to a next stage, each of the plurality of stages includes a pull-up transistor controlled by a first node to apply a first clock signal to an output line, a first pull-down transistor controlled by a second node to apply a first driving voltage to the output line, a controller for controlling the first and second nodes, and a compensating capacitor connected between the first node and an input line of a second clock signal, the second clock signal being different from the first clock signal.

Abstract: A technique for integrating a pre-existing business system with a fleet management system. The pre-existing business system includes, for example, an accounting system, a warehousing system, a dock management system, a yard management system. These fleet management system uses, for example, a combination of a raster map and vector data to provide an easy-to-read display for managing objects or articles, e.g., vehicle, container. The method uses a host gateway to provide a TCP/IP or like interface between the various systems.

Abstract: A method for reducing dark current within an image sensor includes applying, at a first time period, a first set of voltages to the phases of gate electrodes of vertical shift registers sufficient to accumulate holes of the vertical shift register, beneath each gate electrode and applying, at a second time period, a second voltage to a first set of the gate electrodes while simultaneously applying a more positive voltage to a second set of gate electrodes, the second voltage being of sufficient potential so holes that were accumulated beneath the second set of gate electrodes during the first time are collected and stored beneath the first set of gate electrodes during the second time period.

Abstract: Each of stages RS(1), RS(2), . . . of a shift register is constituted by six TFTs. A ratio of a channel width and a channel length (W/L) of each of these TFTs 1 to 6 is set in accordance with a transistor characteristic of each TFT in such a manner that the shift register normally operates for a long time even at a high temperature.

Abstract: A imager has an array of photodetectors, each of which accumulates charge during an integration period as a result of light detected during said integration period, said array having a charge capacity which increases during the integration period. A charge capacity controller coupled to said imager adjusts how the imager increases the charge capacity of the array based upon the brightness distribution detected by said imager during at least one previous integration period.

Abstract: The present invention is embodied in a charge coupled device (CCD)/charge injection device (CID) architecture capable of performing a Fourier transform by simultaneous matrix vector multiplication (MVM) operations in respective plural CCD/CID arrays in parallel in O(1) steps. For example, in one embodiment, a first CCD/CID array stores charge packets representing a first matrix operator based upon permutations of a Hartley transform and computes the Fourier transform of an incoming vector. A second CCD/CID array stores charge packets representing a second matrix operator based upon different permutations of a Hartley transform and computes the Fourier transform of an incoming vector. The incoming vector is applied to the inputs of the two CCD/CID arrays simultaneously, and the real and imaginary parts of the Fourier transform are produced simultaneously in the time required to perform a single MVM operation in a CCD/CID array.

Abstract: A two-dimensional image sensor comprises a matrix array of photodiodes and multiple vertical shift registers horizontally divided into an imaging part and a memory part. During a vertical blanking period, the imaging part receives charge packets from the photodiodes and shifts the charge packets via the memory part to a matrix array of storage cells. During a subsequent horizontal blanking period, the charge packets are restored from the storage cells to the memory part and shifted downwards by the distance of a row so that the charge packets of bottom row are shifted our into a horizontal register. Remaining charge packets are then withdrawn from the memory part to the storage cells and stored therein during a subsequent horizontal scan period. During this horizontal scan period, the memory part is maintained at such a voltage that no dark currents substantially exist and the charge packets in the horizontal register are sequentially delivered to external circuitry.

Abstract: A charge integration circuit incorporates first and second capacitors, and first and second reference voltage supplies. A first switch controls integration of charge in the first capacitor and selectively resets the first capacitor to the first reference voltage. A second switch selectively resets the second capacitor to the first reference voltage. A current mirror coupled to the capacitors effects discharge of the second capacitor by a quantity of charge equivalent to the charge integrated on the first capacitor so as to effectively transfer charge therebetween at the end of an integration period.

Abstract: When a voltage signal corresponding to charges circulating a circulating shift register including charge transfer channels, which are arranged in a ring pattern, are read out from the shift register as a signal value, since clocks for circulating the charges have a very high frequency, it is difficult to operate an A/D converter in synchronism with such clocks, and a very expensive A/D converter must be used. In view of this problem, when the signal is read out, the clock frequency is lowered, and the voltage signal corresponding to the charges is converted into a digital value using an A/D converter that operates at low speed. When a distance measuring device is configured using the circulating shift register, charges corresponding to an image are shifted by the circulating shift register. In this case, since the shift efficiency is less than 100%, the amount of charges immediately after a non-charge portion decreases as they are shifted, and such charges form a false image.

Abstract: A device and method for quantitative determination of an analyte in a biological sample utilizes a non-transparent support medium for retaining a chromatogenic reaction product with the medium being exposed to a source of light for transmitting therethrough a scattered, uniform response light signal which is collected at a photosensitive device whereby the amount of the analyte is correlated to the intensity of the response light signal. The response light signal may be converted to a time-duration signal proportional to light intensity to facilitate the quantitative determination.

Abstract: A method and apparatus for reducing bloom in output of a charge coupled device (CCD) image sensor is disclosed. The method includes the step of toggling at least two phases of said CCD after exposure of said CCD. The method and apparatus are particularly useful when a flash of light occurs during the exposure.

Abstract: In a drive circuit of a solid-state imaging device, no specific voltage source exclusively used to set a substrate voltage is required. An external circuit required when the entire drive circuit is fabricated as an integrated circuit, can be eliminated.

Abstract: A method and apparatus for nearly instantaneous and wide dynamic range exposure control in light-based measurement instruments. The excess charge drained from a CCD array by anti-blooming circuitry is effectively monitored and distinguished from leakage current. Detection of the drained charge generates a signal to deactivate the light source exposing the CCD array. The exposure control device includes a unique circuit for detecting the operating state of an anti-blooming circuit associated with a CCD array, and a unique laser light driver that ramps up the light intensity of the laser light source in an approximately exponential manner.

Abstract: A switched CCD electrode photodetector includes a substrate made of first semi-conductor type, a drain made of a second semi-conductor type formed in the substrate, a collection well made of the second semi-conductor type formed in the substrate, and a switched CCD electrode resistor formed between the drain and the collection well. The collection well is operable in cooperation with a photosensitive region. The switched CCD electrode resistor includes a channel region defined in the substrate and having a first end disposed adjacent to the collection well and a second end disposed adjacent to the drain. The switched CCD electrode resistor also includes a first electrode insulatively spaced from and disposed over the first end and a second electrode insulatively spaced from and disposed over the second end.

Abstract: A solid state image sensing device has a photoelectric transfer section for transducing incident light into signal charges, at least firs% and second charge transfer paths, a charge transferring section for transferring the signal charges from the photoelectric transfer section to the first path at a first timing and for transferring the signal charges transferred to the first path to the second path at a second timing and a charge supply section for applying bias charges to the signal charges to be transferred from the first to the second path. In the device, bias charges supplied to the first path is transferred to the second path. Signal charges are transferred to the first path and then to the second path. The signal and the bias charges both transferred to the second path are outputted.

Abstract: The present invention is directed to methods and apparatus for accurately detecting light energy of a signal of interest (e.g., a laser pulse) even when the signal-to-noise ratio is relatively low. The present invention is further directed to accurate detection of a signal of interest even when either or both the signal of interest and background illumination vary across plural pixels of an imaging an array. For example, a signal of interest can be accurately detected even in the presence of pixel response non-uniformity and fixed pattern noise, or when the incident signal of interest is not confined laterally to a single pixel.

Abstract: A horizontal charge coupled device (HCCD) is provided with a multiple reset gate in order to establish a more stable, less noisy voltage in an output node floating diffusion. Charges are transferred from an input of the HCCD to the floating diffusion by multiple, overlapping gate structures. Signal charges are detected or read out from the floating diffusion through an amplifier/inverter circuit. Periodically, the voltage of the floating diffusion is established to a reference level by application of a reset signal to a multiple reset gate structure, which results in charges in the floating diffusion being transferred to a reset drain. Noise induced by the reset operation is lessened on average due to the multiple reset gate structure.

Abstract: The present invention is embodied in a charge coupled device (CCD)/charge injection device (CID) architecture capable of performing a Fourier transform by simultaneous matrix vector multiplication (MVM) operations in respective plural CCD/CID arrays in parallel in O(1) steps. For example, in one embodiment, a first CCD/CID array stores charge packets representing a first matrix operator based upon permutations of a Hartley transform and computes the Fourier transform of an incoming vector. A second CCD/CID array stores charge packets representing a second matrix operator based upon different permutations of a Hartley transform and computes the Fourier transform of an incoming vector. The incoming vector is applied to the inputs of the two CCD/CID arrays simultaneously, and the real and imaginary parts of the Fourier transform are produced simultaneously in the time required to perform a single MVM operation in a CCD/CID array.

Abstract: In a drive circuit of a solid-state imaging device, no specific voltage source exclusively used to set a substrate voltage is required. An external circuit required when the entire drive circuit is fabricated as an integrated circuit can be eliminated. An image sensing system has a solid-state imaging device formed on a semiconductor body. The solid-state imaging device includes a plurality of photo sensors formed in a major surface of the semiconductor body. The photo sensors receive light incident thereon and generate charges corresponding to the incident light and accumulating the charges therein. A video signal output outputs a video signal corresponding to the accumulated charges, and a charge drain discharges charges from the photo sensors. A timing generator generates a timing signal. A first power supply source provides a first voltage to the solid-state imaging device. A second power supply source provides a second voltage to the solid-state imaging device.

Abstract: An image sensing device with electronic shutter having a semiconductor substrate of a first conductivity type and a buried channel layer of a second conductivity type disposed on the substrate. Virtual phase electrodes in the buried channel layer having the first conductivity type form virtual gate potential areas in the substrate below the virtual phase electrodes. An insulating layer is formed on the substrate. Conductive electrodes disposed on the insulating layer and located over portions of the substrate between the virtual phase electrodes form clocked gate potential areas in the substrate below the conductive electrodes. The virtual gate potential areas and the clocked gate potential areas form charge transfer columns along which charge can be transferred to an end of the charge transfer column.

Abstract: A method for driving a solid-state imaging device which includes the steps of (1) reading a signal from an i-th pixel in the pixel portion into a vertical charge transfer portion over k bit portions thereof starting from the i-th bit portion thereof; (2) transferring the read signal corresponding to k bits of the vertical charge transfer portion in the vertical direction during one horizontal blanking period; (3) reading a signal from an (i+1)-th pixel of the n pixels arranged in the pixel portion into the vertical charge transfer portion over k bit portions thereof starting from the (i+1)-th bit portion thereof after the completion of the transfer of signal portions corresponding to the (k-1) bits of the read signal corresponding to the k bits of the vertical charge transfer portion; (4) repeating the steps (1) through (3) for the pixels arranged in the pixel portion starting from the first pixel nearest to a horizontal charge transfer portion to a pixel farther therefrom; and (5) repeating the step (2) afte

Abstract: It is known to bring the surface into the inverted state in CCD imaging devices with buried channels during the integration period in order to keep the dark current low (All Gates Pinning). The desired potential profile, with wells in which the charge is integrated bounded by potential beers, is obtained through the use of a two-phase structure with a doping profile in the channel or with a gate oxide having thickness differences. Owing to limiting conditions which hold for the clock voltages used for charge transport, serious limitations are imposed on the depth of the potential wells and thus also on the charge storage capacity of the pixels. This disadvantage is counteracted by the operation of the device not as a two-phase but, for example, as a four-phase CCD according to the invention, whereby a d.c. shift is present between the clock voltages for compensating the built-in, comparatively great potential differences described above.

Abstract: A CCD delay line comprises of first, second and third transfer regions which are formed in a semiconductor substrate. Output portions of the second and third transfer regions are connected to a differential amplifier. The output terminal of the differential amplifier is connected to input sources of the first and second transfer regions. The third transfer region is able to carry at most 30% of maximum amount of charge which the first and second transfer regions can carry. A signal is supplied from a signal source through a clamp circuit to an input gate electrode of the first transfer region. Bias changing means independently change one of an input bias voltage supplied to the input gate electrode of the first transfer region and a reference bias voltage supplied to an input gate electrode of the second transfer region.

Abstract: In CCD's, the major part of the dark current is caused by surface states. This dark current is disturbing, especially in image sensors, because the sensitivity of the camera is limited thereby. When according to the invention the integrating gates are varied periodically, the subjacent surface parts of the - buried - channel being brought periodically into inversion and into depletion, while maintaining the charge-containing capacity, a considerable reduction of the dark current can be obtained. In image sensors, voltage variation preferably occurs during the fly-back time.

Abstract: A charge coupled device transfers a charge packet to a floating diffusion region for producing voltage variation therein, and the voltage variation is relayed to an output terminal by means of a driving unit implemented by a plurality of source follower circuits coupled in cascade, wherein each of the second to final source follower circuits is implemented by a series combination of an enhancement type driving transistor and an enhancement type load transistor, and the enhancement type load transistor changes the channel conductance thereof complementary to the enhancement type driving transistor under the control of a control unit so as to improve the dynamic range of the output signal thereof without sacrifice of the sensitivity of the floating diffusion region.

Abstract: A floating diffusion type signal charge detection circuit for use in a charge transfer device includes a charge transfer region formed in a semiconductor layer, a plurality of transfer electrodes formed on the charge transfer region through an insulating layer, a floating diffusion formed in the semiconductor layer adjacent to a final stage of the charge transfer region, a reset drain formed in the semiconductor layer separate from the floating diffusion and connected to a reset drain voltage, and a reset gate formed through an insulating layer on a portion of the semiconductor layer between the floating diffusion and the reset drain. The floating diffusion, the reset drain and the reset gate forms a reset transistor. An amplifier is connected at its input to the floating diffusion so as to detect a voltage change appearing in the floating diffusion.

Abstract: A CCD amplifier circuit including an active load type source-grounded inverting amplifier circuit which includes a driving MOS transistor, an active load MOS transistor connected to the driving MOS transistor, and a control circuit. The control circuit controls the voltage at the gate electrode of the active load MOS transistor with a control signal of low output impedance which is substantially inversely proportional to the drain-source voltage of the active load MOS transistor and level-shifted by a predetermined voltage. Further, a CCD delay line includes a floating diffusion region of predetermined impurities formed at an end of a charge-coupled device with a gate section having a predetermined fixed gate voltage, and a switched capacitor integrator for detecting the injection charge of the floating diffusion region to detect signal charges transferred to the floating diffusion region from the charge-coupled device.

Abstract: A charge detection circuit includes a p-type semiconductor substrate, a reference voltage source for generating a reference voltage having a predetermined voltage difference with respect to the potential of the semiconductor substrate, a first n.sup.+ -type semiconductor region formed in the semiconductor substrate, for storing a carrier packet, a second n.sup.

Abstract: In this invention, a plurality of clock buffers are provided to supply clock signals to a charge transfer apparatus. These clock buffers are driven by the same basic clock which is introduced through a plurality of clock logics. Accordingly, even if the charge transfer apparatus is comprised of a multi-stage charge coupled device having a large number of stages, those clock buffers still have enough ability to drive the charge transfer apparatus with high frequency. So, the driving circuit according to this invention can drive a multi-stage charge transfer apparatus with keeping the excellent frequency characteristics, even if the charge transfer apparatus is driven with high frequency.

Abstract: A charge transfer device comprises a charge transfer section having a charge transfer region formed in a semiconductor substrate and transfer electrodes formed on the semiconductor substrate, and a reset transistor having a floating diffusion region formed in the semiconductor substrate for receiving an electric charge transferred from the charge transfer section, a reset drain applied with a reset voltage, and a reset gate formed above a channel between the floating diffusion region and the reset drain, the reset gate being applied with a reset pulse. A a peak hold circuit is connected to the reset gate of the reset transistor for hold a peak level of the reset voltage. A potential detection circuit includes a dummy transistor having a drain connected to a voltage V.sub.DD, a source grounded through a resistor which is considerably larger than an on-resistance of the dummy transistor itself, and a gate electrode connected to an output of the peak hold circuit.

Abstract: An amplification MOSFET in a source ground form receives at its gate an output signal of a source-follower circuit through a second capacitor. The source-follower circuit, on the otherhand, receives a voltage of a first capacitor which receives a signal charge. A predetermined bias voltage is supplied to the gate of the amplification MOSFET through a switch device while the signal charge of the first capacitor is reset. According to this structure, the second capacitor can transmit only the signal component and the voltage signal itself can be amplified by the source ground type amplification MOSFET. The amplification MOSFET can be biased to its optimum operation point by the switch device during the reset period of the first capacitor; hence, sensitivity can be substantially improved with a simple circuit structure.

Abstract: A charge coupled device is provided with a first signal input path for supplying an information signal for transfer through a delay line, which contain an inverting amplifier, and a second signal input path which has no inverting amplifier. The first and second signal input paths are arranged in parallel to each other. The charge coupled device also has a switching means associated with the first and second signal input paths so as to selectively establishing connection between one of the first and second signal input paths and the delay line so that non-inverted and inverted information signals can be selectively supplied to the delay line.

Abstract: A control device for a charge detection circuit comprising a CCD final gate electrode formed on a semiconductor substrate, an electric potential barrier forming gate electrode placed adjacent to the CCD final gate electrode, a diffusion region formed adjacent to the electric potential barrier forming gate electrode, a reset transistor connected to the diffusion region, a source follower circuit which uses as an input an electric potential in the diffusion region, a sample and hold circuit for receiving the output of the source follower circuit at a specified timing, a reference voltage source which has a value determined by the dynamic range of the source follower circuit, and an integrator which integrates a difference between the output of the sample and hold circuit and the output of the reference voltage source, and applies a value obtained by the integration to the electric potential barrier forming gate electrode.

Abstract: A solid state image sensor comprises a p-type semiconductor region, an n-type photoelectric conversion region formed in a surface region of the semiconductor region, an n-type charge transfer region formed in the surface of the semiconductor region separately from the photoelectric conversion region, and an electric charge read-out gate region formed between the photoelectric conversion region and the charge transfer region. A p.sup.+ thin surface layer region if formed to cover a surface of the photoelectric conversion region excluding an end portion adjacent to the electric charge read-out gate region. A gate electrode is formed above the electric charge read-out gate region. The end portion of the photoelectric conversion region not covered by the thin surface layer region, has a short length sufficient to make a potential well formed in the portion shallow under influence of potentials of the p.sup.+ thin surface layer region and the electric charge read-out gate region.

Abstract: An input structure of CCD comprises a primary register having an input gate and a source region and an automatic biasing system which generates a feedback signal to be fed back to input of the primary register. The output of the automatic biasing system is connected to one of the input gate and the source of the primary register for supplying the feedback signal thereto for adjusting input bias level of the primary register. The other one of the input gate and the source is connected to an information signal input terminal to receive therefrom an information signal to be transferred therethrough.

Abstract: A Charge-Coupled Device is operable as an exposuremeter during the normal exposure of the parallel register by switching one of the parallel register gates temporarily back and forth between drive circuitry and a sense amplifier. During the exposure of the CCD to photons, the gate potentials are set so that photonic generated charge is stored under one or more phases. An arbitrary gate in the parallel register, designated the sense gate, is disconnected from a normal gate driver and connected to a high input impedance amplifier. The potential on a gate adjacent to the sense gate is changed so that charge is transferred under the sense gate and back again thus producing a voltage transient which is proportional to the total transferred charge.

Abstract: A charge-coupled device (CCD) delay line having a temperature compensation circuit capable of compensating for temperature variations for providing an accurate and consistent delay of an input signal. The temperature compensation circuit includes first and second registers for transferring charges, and a sample-and-hold circuit connected between outputs of each register and two inputs of a differential amplifier. The differential amplifier supplies a signal which corresponds to temperature variations to properly bias the input signal.

Abstract: In a CCD in which a pixel is defined by at least two adjacent gate electrodes, voltages are applied to both gate electrodes to simultaneously place both gates of each pixel in a mode of operation whereby holes are accumulated at the surface of a substrate in which the CCD is formed. Preferably one of these voltages is at a higher potential level than the other.

Abstract: There is provided a charge transfer device comprising a shift register comprised of a plurality of shift stages directly connected to each other, phase pulses for a multi-phase control pulse being delivered to the shift stages, respectively, a transfer control pulse being delivered to the shift register stage arranged at one end of the plurality of shift stages; and a transfer unit having a plurality of transfer electrodes provided in correspondence with the shift stages of the shift register, transfer pulses being delivered from the shift stages of the shift register to the transfer electrodes, respectively, to apply transfer pulses in a predetermined order from the shift stages of the shift register to the transfer electrodes of the transfer unit, respectively, to thereby sequentially transfer signal charges stored below the transfer electrodes in a predetermined direction.

Abstract: A horizontal transfer shift register is formed on a semiconductor substrate for use in a solid state image sensor of the charge transfer device type. The horizontal transfer shift register is coupled to receive electric charge signals in parallel and operates to serially transfer the received electric charge signals to an signal output circuit. The horizontal transfer shift register comprises a plurality of horizontal transfer electrodes formed on the substrate, a control electrode formed on the substrate adjacent to a horizontal transfer electrode adjacent to the signal output circuit, and a drain diffusion region formed in the substrate adjacent to the control electrode.

Abstract: An input circuit for a charge-coupled device (CCD) delay line is comprised of a semiconductor substrate, a CCD delay line formed on the semiconductor substrate, first and second registers each having substantially the same maximum treating charge amount as that of the CCD delay line and formed on the semiconductor substrate, an input portion of the first register having substantially the same structure as that of the CCD delay line, output portions of the first and second registers having substantially the same structure each other, a control circuit for controlling the second register so that an output signal from the second register becomes a signal corresponding to the maximum treating charge amount, a comparing circuit for comparing output signals of the first and second registers, wherein an output signal of the comparing circuit is fed back to an input source of the input portion of the first register so that the output signal from the first register becomes equal to the output signal from the second re

Abstract: Each of stages RS(1), RS(2), . . . of a shift register is constituted by six TFTs. A ratio of a channel width and a channel length (W/L) of each of these TFTs 1 to 6 is set in accordance with a transistor characteristic of each TFT in such a manner that the shift register normally operates for a long time even at a high temperature.