Abstract: A display device includes a display panel including data lines, gate lines crossing the data lines, and pixels arranged in a matrix form, a touch screen which is embedded in the display panel or is installed on the display panel, a data driving circuit supplying a data voltage to the data lines, a gate driving circuit supplying a gate pulse to the gate lines, and a touch sensing circuit which supplies a driving signal to lines of the touch screen and senses a touch input. The gate driving circuit alternately drives pull-down transistors connected in parallel to one gate line. The gate driving circuit drives one of the pull-down transistors or simultaneously drives the pull-down transistors during a drive period of the touch screen.

Abstract: Described herein is a low-voltage multi-stage interleaver. The interleaver includes at least a first interleaver stage and a second interleaver stage. The first interleaver stage is either blocked or operating in a saturation region. The first interleaver stage facilitates cancellation of DC current, including a biasing current, so that the second interleaver stage receives no DC current input. The second interleaver stage is either blocked or operating in a linear region to allow the second interleaver stage to act as a passive current switch.

Abstract: A charge transfer circuit, such as a charge coupled device or other bucket brigade device, which incorporates an amplifier to assist with charge transfer.

Abstract: Performing a hash algorithm in a processor architecture to alleviate performance bottlenecks and improve overall algorithm performance. In one embodiment of the invention, the hash algorithm is pipelined within the processor architecture.

Abstract: A shift register having a plurality of stages in which each of the stages includes: an input circuit part arranged to receive an input signal; an exclusive OR circuit arranged to generate a toggle signal by an exclusive OR operation on a non-inversion output and an inversion output of the input circuit part; and an output circuit part arranged to supply one of a clock signal and a feedback signal from an output terminal to the output terminal and an input terminal of the next stage in response to the toggle signal.

Abstract: A shift register apparatus and a method thereof are provided. The technique manner submitted by the present invention utilizes two NMOS transistors for pulling down the voltage level of the scan signals output by the shift registers within the shift register apparatus to the low level gate voltage, wherein one of the NMOS transistors is controlled by a control unit, and the other NMOS transistor is controlled by a clock signal or the inverted clock signal provided to the shift registers. Therefore, shifting amount of the threshold voltage of those NMOS transistors can trend to be flat, and the reliability of those NMOS transistors can be promoted. In addition, since only one control unit is needed to dispose in each shift register so that the layout area of whole shift register apparatus can be reduced, and the panel with narrow frame size also can be achieved by the present invention.

Abstract: A multiplication register for use in solid state imaging apparatus, such as a CCD, is described. The multiplication register has a gain element 22 comprising a plurality of register electrodes 30, 32, 34, and 36, for transferring charge along a change transfer channel, and for amplifying the charge. Channel edge defining electrodes 24 and 26 are disposed either side of the channel 28, in place of channel stops, removing the effects of spurious charges generated in the channel in the regions of amplification. The provision of the channel edge defining electrodes 24 and 26 allows the resulting structure of the channel electrodes to be made simpler, and means that a structure can be provided for clocking and amplifying charge in either direction along the channel.

Abstract: In a differential bucket-brigade device (BBD) pipeline it is necessary for proper circuit function to maintain the common-mode charge within an acceptable range at each pipeline stage. Embodiments of the present invention provide for reducing common-mode charge variations in a differential charge-domain pipeline. Common mode charge at a given stage of the pipeline is adjusted according to one or more measured characteristics, thereby controlling common mode charge variation throughout the differential charge-domain pipeline.

Abstract: An ADC implementation of a bucket brigade type charge transfer pipeline using Metal Oxide Semiconductor (MOS) Bucket Brigade Devices (BBDs) that can be used in Analog-to-Digital (A/D) converters and other applications. In one embodiment a control circuit provides independent control of charge storage and charge transfer timing. Other arrangements provide high-speed and high-accuracy (A/D) conversion by employing a “boosted” charge-transfer circuit. The implementation can also achieve lower power consumption and improved resolution compared to other charge-domain methods by the use of a tapered pipeline, in which the amount of charge being processed is reduced in later pipeline stages compared to earlier ones. Still other embodiments enable implementing more than one decision threshold per stage, to support multi-bit resolution per stage and RSD-type A/D conversion algorithms.

Abstract: A charge multiplication amplifier device comprises a series arrangement of a first separation barrier facility, a temporary storage well for charge carriers, a second charge transfer barrier facility, an impact ionization facility that is operative through electric field strength effective on mobile charge carriers, and a charge collection well for receiving charge carriers so multiplied. Advantageously, the device comprises a charge collection and transfer facility (32) that is geometrically disposed next to the impact ionization facility (31) whereas impact ionization facility is controlled at a substantially static electric potential (DC1, DC2) for controlling the electric field strength. Advantageously, another embodiment of this device comprises charge collection and transfer facilities (41, 42) implemented as two (or more) independently clocked signals ?1, ?2 that require nearly two times less swing to achieve same effect.

Abstract: An ADC implementation of a bucket brigade type charge transfer pipeline using Metal Oxide Semiconductor (MOS) Bucket Brigade Devices (BBDs) that can be used in Analog-to-Digital (A/D) converters and other applications. In one embodiment a control circuit provides independent control of charge storage and charge transfer timing. Other arrangements provide high-speed and high-accuracy (A/D) conversion by employing a “boosted” charge-transfer circuit. The implementation can also achieve lower power consumption and improved resolution compared to other charge-domain methods by the use of a tapered pipeline, in which the amount of charge being processed is reduced in later pipeline stages compared to earlier ones. Still other embodiments enable implementing more than one decision threshold per stage, to support multi-bit resolution per stage and RSD-type A/D conversion algorithms.

Abstract: In a differential bucket-brigade device (BBD) pipeline it is necessary for proper circuit function to maintain the common-mode charge within an acceptable range at each pipeline stage. Embodiments of the present invention provide for reducing common-mode charge variations in a differential charge-domain pipeline. Common mode charge at a given stage of the pipeline is adjusted according to one or more measured characteristics, thereby controlling common mode charge variation throughout the differential charge-domain pipeline.

Abstract: A pulse to static converter for SRAM in which the converter latch is comprised of two cross-coupled, complementary, FET pairs. The FETs of each pair are coupled drain to drain between a positive voltage source and ground. The output state of SRAM sense amplifier is coupled as an input to the grates of one FET pair and the state established by this input is latched via the cross coupling with the other FET pair.

Abstract: A circuit for adding or subtracting an amount of charge from a charge sample, such as in a Charge Coupled Device (CCD), by portioning and pipelining the processing stages, to avoid introducing a memory effect. The operation, such as subtraction, is split into multiple stages, with each stage responsible for removing only a portion of the total amount of charge that is desired to be removed. The subtraction pipeline stages operate together to remove the total desired charge amount. In one embodiment each successive subtraction stage removes a corresponding lesser amount of charge. As a result, greater accuracy in the amount of charge removed is achieved as well operation at higher frequencies than previous charge subtraction approaches.

Abstract: This invention controls the signal amplification rate in a simple way with high precision in a CMD or CMD-carrying CCD device. CMD 12 has plural sections, such as M sections (U1-UM), each of which is a CMD unit U that can perform a charge multiplication operation, set in series. Each section of CMD unit Ui has plural (such as 4) electrodes G1, G2, G3, G4 set in a row via an insulating film, such as silicon oxide film 100, on a silicon insulating film. Among driving voltages P1, P2, P3, P4 applied on the electrodes G1, G2, G3 and G4, P1 and P2 are applied in the same cycle as the transfer clock, P4 for impact ionization is applied in intermittent cycles with respect to P1 and P2, and P3 is applied as a DC voltage at a prescribed level.

Abstract: A sensor chip assembly time delay integration circuit useful with image sensing arrays uses a duplex bucket brigade circuit (120) with two or more charge transfer paths, a number of capacitors (130, 133, 136) common to the charge transfer paths, and a number of capacitors (131, 132, 134, 135) specific to each of the charge transfer paths. Each of the charge transfer paths has a number of MOSFET transfer gates (122, 124, 126, 128; 123, 125, 127, 129) connected in series, and the common capacitors and the path-specific capacitors are alternately connected to the paths. Each of the common capacitors is controllably connected (112, 115, 118) either to a unit cell input circuit (113, 116, 119). a reset node (111, 114, 117), or an open circuit. The circuit operates by storing accumulated image sensor charges from alternate sensor lines on the path-specific capacitors. The common capacitors are reset and then connected to the unit cell input circuits to acquire a first set of image sensor charges.

Abstract: The image sensing device incorporates a charge multiplication function in its serial register. The design layout is compact in size and the charge multiplication register consists of multi-channel sections that are evenly positioned around the periphery of the image sensing area. The individual charge multiplying register sections are coupled together by only 90-degree multi-channel turns located at the image area array corners. The device allows for the optical image sensing area center to be located near the chip center and consequently near the mechanical package center with the minimum silicon chip area sacrifice.

Abstract: A programmable two-dimensional timing generator according to the invention employs a clock generator (102) and a user-defined two-stage waveform generator (106, 108). A single static random access memory (SRAM) (112) stores a user-defined waveform control word for both waveform generator control units. The SRAM data is entered via the host controller external data bus. A single waveform control word may be used to control both waveform generators.

Abstract: There is provided a register system of a microcomputer having a register that includes at least one register bit and having an additional storage arrangement allocated to the register and on which the data content of the register is able to be intermediately stored. To reduce the computing time for saving the data content of the register, while keeping the silicon surface required for the register system as small as possible, the additional storage arrangement includes at least one shift register having at least two shift register cells, the content of an arbitrary shift register cell being transferable into a register bit, and, conversely, the content of a register bit being transferable into an arbitrary shift register cell.

Abstract: This invention controls the signal amplification rate in a simple way with high precision in a CMD or CMD-carrying CCD device. CMD 12 has plural sections, such as M sections (U1-UM), each of which is a CMD unit U that can perform a charge multiplication operation, set in series. Each section of CMD unit Ui has plural (such as 4) electrodes G1, G2, G3, G4 set in a row via an insulating film, such as silicon oxide film 100, on a silicon insulating film. Among driving voltages P1, P2, P3, P4 applied on the electrodes G1, G2, G3 and G4, P1 and P2 are applied in the same cycle as the transfer clock, P4 for impact ionization is applied in intermittent cycles with respect to P1 and P2, and P3 is applied as a DC voltage at a prescribed level.

Abstract: A TDI sensor includes a bias charge voltage circuit, a reset voltage circuit, a bucket brigade column having a plurality of nodes, and a plurality of pinned photodiodes. Each photodiode is formed integral with a corresponding node of the bucket brigade column. The bucket brigade column is coupled between the bias charge voltage circuit at an initial node and the reset voltage circuit at a final node. The bucket brigade column includes a plurality of first phase clock conductors, and a plurality of second phase clock conductors, and the first and second phase clock conductors are interdigitated and formed of poly-crystalline silicon. The TDI sensor is formed in a substrate of a first conductivity type, and a cathode of each pinned photodiode is formed of a second conductivity type, and each pinned photodiode includes a pinning layer of the first conductivity type.

Abstract: A shift register has m stages which store one of two states, where m is an integer more than 1, each stage including clock input terminals at which n-phase clock signals are input, where n is an integer more than 1, and an input terminal, and an output terminal. The input terminal of one stage receives the signal delivered from an input terminal of the shift register or from the output terminal of the previous stage. The signal output at the output terminal of one stage is passed to the input terminal of the subsequent stage or to an output terminal of the shift register. Each stage receives an initial state level from one of the clock input terminals. The initial state level is used to initialize the state of each stage.

Abstract: Circuits for sequentially addressing memory locations in time with pulses received from a clock are disclosed. The circuits may provide a positive voltage output signal at successive output nodes associated with corresponding stages in the circuit responsive to the application of a clock signal to the circuit stages. The circuit may comprise at least first and second stages wherein said first stage comprises means for providing a positive voltage signal at a first output node in the first stage in response to application of a first positive clock pulse to the first stage, and wherein said second stage comprises means for providing a positive voltage signal at a second output node in the second stage in response to application of a second positive clock pulse to the second stage. Addressing of memory locations that contain pixel information for a video display is one particular application in which sequential addressing may be required.

Abstract: A method and device for the electrolytic formation of a deposit on a group of electrodes of an electrolysis support. The support has a plurality of electrodes. Electric charges are selectively deposited on chosen electrodes. The support is placed in the presence of an electrolyte to produce the deposit on the chosen electrodes by electrolysis. The electric charges deposited on the electrodes provide an electrolysis current for each chosen electrode. The formed device may be used as a biological sensor.

Abstract: The present invention is embodied in a charge coupled device (CCD)/charge injection device (CID) architecture capable of performing a Fourier transform by simultaneous matrix vector multiplication (MVM) operations in respective plural CCD/CID arrays in parallel in O(1) steps. For example, in one embodiment, a first CCD/CID array stores charge packets representing a first matrix operator based upon permutations of a Hartley transform and computes the Fourier transform of an incoming vector. A second CCD/CID array stores charge packets representing a second matrix operator based upon different permutations of a Hartley transform and computes the Fourier transform of an incoming vector. The incoming vector is applied to the inputs of the two CCD/CID arrays simultaneously, and the real and imaginary parts of the Fourier transform are produced simultaneously in the time required to perform a single MVM operation in a CCD/CID array.

Abstract: When a voltage signal corresponding to charges circulating a circulating shift register including charge transfer channels, which are arranged in a ring pattern, are read out from the shift register as a signal value, since clocks for circulating the charges have a very high frequency, it is difficult to operate an A/D converter in synchronism with such clocks, and a very expensive A/D converter must be used. In view of this problem, when the signal is read out, the clock frequency is lowered, and the voltage signal corresponding to the charges is converted into a digital value using an A/D converter that operates at low speed. When a distance measuring device is configured using the circulating shift register, charges corresponding to an image are shifted by the circulating shift register. In this case, since the shift efficiency is less than 100%, the amount of charges immediately after a non-charge portion decreases as they are shifted, and such charges form a false image.

Abstract: A circuit arrangement for frequency multiplication is described, by means of which a digital output signal is produced, the pulse repetition rate of which is obtained from one of the output signals by multiplication by an adjustable factor K. A high accuracy of the frequency of the output signal is obtained by the fact that an input counter is clocked by a digitally controlled oscillator and by the fact that the following means for controlling an output counter are provided:a register, in which counting positions of the input counter are temporarily stored,a comparator, which compares these counting positions to the counting positions of the output counter, and produces a pulse then when the comparison yields a predetermined result,a feedback between the comparator and the output counter in such a manner that the pulses from the comparator reset the output counter to its initial position.

Abstract: A semiconductor device of the invention is provided with a charge-discharge capacitor and plural charge collecting capacitors which are respectively connected in parallel to the charge-discharge capacitor via switches. The charge-discharge capacitor is not only connected to a power source via a switch but also connected to a circuit for discharging via another switch. By controlling the switches which are used to turn on and off the connections between the charge collecting capacitors and the charge-discharge capacitor, charge is collected to the charge collecting capacitors in order of the electric potential, namely from the lower potential to the higher, and then the charge moves back to the charge-discharge capacitor in reverse order and is recycled. As a result, the charge recycling rate is raised to 50% or more, and the electric power to be consumed can be further decreased. Moreover this invention can be applied to a refresh operation for the identical memory-cell-array.

Abstract: The present invention is directed to methods and apparatus for accurately detecting light energy of a signal of interest (e.g., a laser pulse) even when the signal-to-noise ratio is relatively low. The present invention is further directed to accurate detection of a signal of interest even when either or both the signal of interest and background illumination vary across plural pixels of an imaging an array. For example, a signal of interest can be accurately detected even in the presence of pixel response non-uniformity and fixed pattern noise, or when the incident signal of interest is not confined laterally to a single pixel.

Abstract: We have recognized that in the prior art, to insure that there is at least some communication between the calling and called parties, when the called party is unavailable to take a call, the calling party may be connected to an alternate destination, e.g., a voice messaging system, and the caller's telephone call is considered completed. If the called party thereafter becomes available, the called party is not connected to the caller's telephone call. However, in accordance with the principles of the invention, this problem is overcome by, in response to receipt of an indication that the called party is available for a caller's telephone call after the caller's telephone call has already been connected to an alternate destination, a) disconnecting the caller's telephone call from the alternate destination and, instead, b) connecting it the called party, thus interrupting the connection between the caller and the alternate destination.

Abstract: The present invention is embodied in a charge coupled device (CCD)/charge injection device (CID) architecture capable of performing a Fourier transform by simultaneous matrix vector multiplication (MVM) operations in respective plural CCD/CID arrays in parallel in O(1) steps. For example, in one embodiment, a first CCD/CID array stores charge packets representing a first matrix operator based upon permutations of a Hartley transform and computes the Fourier transform of an incoming vector. A second CCD/CID array stores charge packets representing a second matrix operator based upon different permutations of a Hartley transform and computes the Fourier transform of an incoming vector. The incoming vector is applied to the inputs of the two CCD/CID arrays simultaneously, and the real and imaginary parts of the Fourier transform are produced simultaneously in the time required to perform a single MVM operation in a CCD/CID array.

Abstract: A logic circuit is driven by a single alternating voltage power supply so that the energy stored in parasitic capacitances can be mostly recovered, rather than dissipated, as in conventional logic designs. Successive stages of the logic circuit are of opposite conductivity types such that the successive stages are activated in alternate half cycles of the power supply without separate clock signals. Each stage of the logic circuit is precharged during a respective first half cycle of the power supply and is active in logical processing during a second half cycle. The half cycles are defined by the rising and falling edges of the power supply. The logic circuit resonates with an inductor coupled across the power supply but closely coupled to the logic circuit. This inductor and the method of charging and discharging the capacitors in the logic circuit serve to minimize the power dissipated during logical processing.

Abstract: The present invention provides a memory device for realizing an analog memory that or a multilevel memory easy to produce and requires only small scale circuitry. The memory device comprises: a CCD array "Ai" linearly arranged a refresh circuit "R" connected to a CCD on one end CCD array; a shaping circuit connected to a CCD on another end of the CCD array; a feedback line "FL" for connecting an output the shaping circuit to an input of the refresh a topology difference clock line "CL" for transmitting data CCD array.

Abstract: A solid-state imaging device includes a semiconductor substrate in which an element part including a plurality of light responsive elements for generating charge carriers in response to incident light and a transfer part for transferring the charge carriers generated in each light responsive element are incorporated; a lens layer is disposed on the element part so that incident light is collected in the light responsive elements; and a light beam dispersion layer is disposed between the lens layer and the element part and includes two light transmissive layers having different refractive indices for dispersing light collected by the lens layer so that collected light entering respective light responsive elements is closer to a parallel beam than the incident light. By suppressing broadening of incident light in the semiconductor substrate at the light responsive elements, fewer charge carriers enter the CCD channel region and smear is reduced.

Abstract: A thinned backside illuminated charge-coupled imaging device has improved quantum efficiency by providing a sharp ion implant distribution profile (20) disposed at the rear surface (22) of the device. The sharp ion implant distribution profile (20) is formed using ion implantation at a beam energy potential of between 100-150 keV, which forms an electric field beneath the surface of the device. The ion distribution profile (20) is brought to the surface (22) of the device by removing silicon (18) from the rear surface (22), using a polishing technique wherein the device is lapped with colloidal silica abrasive to controllably remove silicon down to the level of the ion implantation profile (20).

Abstract: Logically and thermodynamically reversible charge transfer (RCT) devices and logic are provided for conditionally transferring individually identifiable charge packets from one or more sources to one or more destinations under the control of one or more additional charge packets that indicate by their presence or absence whether the condition or conditions have been satisfied or not. The individual identities of all of these charge packets are substantially preserved while logic operations are being performed by this logic.

Abstract: A bucket brigade analog delay line with voltage limiting feedback includes an input stage for receiving an input signal and a series of delay stages coupled to the input stage for propagating the input signal through the line. Each delay stage contains a storage capacitor for holding either a signal charge or a reference charge, a transfer device for transferring charge from one stage to another at regular clock intervals, and a tap circuit for allowing external sampling of the propagated input signal. Each delay stage also includes a negative feedback amplifier for maintaining the drain terminal of the transfer device at a constant potential during charge transfer, thereby eliminating errors caused by finite output impedance of the transfer device. The negative feedback amplifier also prevents overvoltage conditions which could result in failure of the charge transfer devices.

Abstract: The present invention is directed to an output circuit for a charge transfer device which can reduce a coupling voltage of a floating diffusion type charge detecting section and in which a DC fluctuation of an output from a source-follower stage can be suppressed. A dummy floating diffusion region (FD2) is provided and an output thereof is converted by and derived from a bias generator circuit (7) of a source-follower configuration as a positive phase output. This positive phase output is supplied to a load MOS transistor (Q.sub.2) of a source-follower circuit (5) as a bias voltage and also fed back to the load MOS transistor (Q.sub.6) of the bias generator circuit (7) as a gate voltage.

Abstract: An exploiting or readout circuit for a linear or matrix type photodetector array is of the multiplex type, such as a charge-coupled device (CCD). The exploiting circuit has a number of input stages corresponding to the number of photodetectors or similar photosites, and the gains of the input stages are established as a function of the fields of view of their associated photodetectors. In one embodiment the input stages each comprise a storage device formed of a first and a second storage electrode separated by a dividing electrode, the storage electrodes having respective surface areas selected in a relation that varies as a function of solid angle field of view of the respective photodetector. In another embodiment the input stage can include an OpAmp with a negative feedback capacitor whose value is selected as a function of the viewing solid angle of the respective photodetector.

Abstract: In this invention, a plurality of clock buffers are provided to supply clock signals to a charge transfer apparatus. These clock buffers are driven by the same basic clock which is introduced through a plurality of clock logics. Accordingly, even if the charge transfer apparatus is comprised of a multi-stage charge coupled device having a large number of stages, those clock buffers still have enough ability to drive the charge transfer apparatus with high frequency. So, the driving circuit according to this invention can drive a multi-stage charge transfer apparatus with keeping the excellent frequency characteristics, even if the charge transfer apparatus is driven with high frequency.

Abstract: An amplification MOSFET in a source ground form receives at its gate an output signal of a source-follower circuit through a second capacitor. The source-follower circuit, on the otherhand, receives a voltage of a first capacitor which receives a signal charge. A predetermined bias voltage is supplied to the gate of the amplification MOSFET through a switch device while the signal charge of the first capacitor is reset. According to this structure, the second capacitor can transmit only the signal component and the voltage signal itself can be amplified by the source ground type amplification MOSFET. The amplification MOSFET can be biased to its optimum operation point by the switch device during the reset period of the first capacitor; hence, sensitivity can be substantially improved with a simple circuit structure.

Abstract: A FISO analog signal acquisition system includes a plurality of CCD arrays (20a-20d), with each array containing a plurality of CCD serial registers (22). Each serial register (22) has a first cell (23) and a large number of additional cells (24) coupled in series with the first cell (24), with acquired samples being transferred along the string of additional cells (24) according to a clock signal having two or more phases, with each CCD array (20a-20d) operating in response to a set of clock signals having a different phase (P1,P2,/P1,/P2). A tapped delay line (10), or other similar hold signal generating means, produces a plurality of closely spaced-in-time sequential hold signals in response to a master hold signal. In response to each one of the hold signals, a CMOS transistor (Q.sub.x) briefly connects an associated first cell (23) to the signal to be sampled so that a series of closely spaced-in-time samples of the signal are acquired.

Abstract: A charge-coupled device (CCD) delay line having a temperature compensation circuit capable of compensating for temperature variations for providing an accurate and consistent delay of an input signal. The temperature compensation circuit includes first and second registers for transferring charges, and a sample-and-hold circuit connected between outputs of each register and two inputs of a differential amplifier. The differential amplifier supplies a signal which corresponds to temperature variations to properly bias the input signal.

Abstract: A charge injection circuit for injecting a charge to a signal processing circuit has a photo-voltaic element for generating a photocurrent when an infrared light is received, a field effect transistor used for injecting the charge to the signal processing circuit, and an impedance conversion circuit for feeding back an output of the field effect transistor to a substrate potential of the photo-voltaic element. The impedance conversion circuit has a gain which is greater than zero and less than or equal to one.

Abstract: There is provided a one-dimensional MIM array having MIM structures arranged on an insulative substrate in a lateral direction and each used as a unit for storing a signal charge, for sequentially storing and transferring the signal charges between the adjacent MIM structures. With the above element structure, the signal charge is transferred in each of the MIM structures in a thickness direction (depth direction) thereof and stored in a capacitor. The signal charge stored in the capacitor is sequentially transferred in a lateral direction or to the next MIM structure. In order to drive the above charge transfer device, transfer pulses applied to a plurality of MIM structures constituting a one-dimensional MIM array are controlled to sequentially transfer and store the signal charges into the MIM structures starting from the MIM structure which is provided on the output terminal side of the one-dimensional MIM array.

Abstract: The invention concerns a device for reading quantities of electrical charge supplied by photodiodes. These photodiodes (1) are arranged at the intersections of rows and columns (4,5) of a matrix (area) array. The device consists of means (6) for storing charges coming from a row of column of the array during scanning, a shift register (10) having an input stage and n-1 intermediate stages, means (18, 20) for injecting bias charges into the receiving potential wells, and skimming type transfer means (19) for transferring the stored charges and bias charges towards the shift register. The readout during scanning of the charges form a row or column of photodiodes is obtained after n charge transfers and n-1 shift operations. With known devices, n readouts are carried out per row or column, making them very slow and/or inefficient with large or high-signal photodiodes.

Abstract: A solid-state imager comprising a substrate of a semiconductor material of one conductivity type having a major surface. A plurality of photodetectors are in the substrate and are arranged in an array of rows and columns. A separate CCD shift register is in the substrate along each column of the photodetectors and between adjacent columns of the photodetectors. Each shift register includes gates which can be operated to selectively transfer charge carriers from the photoconductors in the column at one side thereof into the shift register. A separate drain is adjacent each photodetector and the shift register adjacent the other side of the column of photodetectors. An anti-blooming barrier is provided between each drain and its adjacent photodetector. An exposure control barrier is provided between each drain and the shift register at the opposite side of the column of photodetectors.

Abstract: An image sensor is disclosed which comprises an imaging region and horizontal shift registers which receive charge carriers generated in the imaging region and transfer them to an output circuit for processing. In order to facilitate the transfer of charge carriers out of the sensor and to provide an image sensor which has a simplified structure, dual horizontal transfer registers are used and transfer of charge carriers between the two registers is accomplished without a separate transfer gate electrode. Transfer regions are disposed between alternate storage regions of the registers such that charge carriers in one-half of the storage regions in one register can be transferred to storage regions in the other register. The two registers can then be clocked out in parallel to read out a single line.

Abstract: In a charge transfer device including spaced apart channels on a semiconductor substrate, first electrodes are disposed in gaps between the channels, second electrodes are disposed opposite alternate channels overlapping the adjacent first electrodes, and a third continuous electrode overlies the alternating channels and first and second electrodes in the charge transfer direction. A first clock phase is obtained by connecting alternate first electrodes with the adjacent second electrode in the direction of charge transfer, and a second clock phase is obtained by connecting the remaining first electrodes with the third electrode. The portion of the first electrode overlapped by the second electrode in the second clock phase is larger than that in the first clock phase for stable driving by first and second clock signals out of phase by 180.degree. and generated by a driver including a resonance circuit.

Abstract: A uniphase, buried-channel, semiconductor charge transfer device wherein a portion of each cell includes an inversion layer, or "virtual electrode" at the semiconductor surface, shielding that region from any gate-induced change in potential. Each cell is comprised of four regions (I, II, III, IV) wherein the characteristic impurity profile of each region determines the maximum potential generated therein for the gate "on" and gate "off" conditions. Clocking the gate causes the potential maxima in regions I and II to cycle above and below the fixed potential maxima in regions III and IV beneath the virtual electrode. Directionality of charge transfer is thereby achieved, since the potential maximum for region II (.phi..sub.max II) remains greater than for region I (.phi..sub.max I) and .phi..sub.max IV>.phi..sub.max III, for both gate conditions.