Abstract: Disclosed is a CCD device in which a charge transfer register of a CCD structure is connected to a charge detector via an output gate and has a reset gate between the charge detector and a reset drain, and an output gate pulse opposite in phase from a reset pulse applied to the reset gate is applied to the output gate. A dummy charge detector and an amplitude adjusting circuit are provided. On the basis of detection of the potential of a diffusion layer in the dummy charge detector, the amplitude adjusting circuit controls the amplitude of the output gate pulse applied to the output gate.

Abstract: In a differential bucket-brigade device (BBD) pipeline it is necessary for proper circuit function to maintain the common-mode charge within an acceptable range at each pipeline stage. Embodiments of the present invention provide for reducing common-mode charge variations in a differential charge-domain pipeline. Common mode charge at a given stage of the pipeline is adjusted according to one or more measured characteristics, thereby controlling common mode charge variation throughout the differential charge-domain pipeline.

Abstract: The present invention is embodied in a charge coupled device (CCD)/charge injection device (CID) architecture capable of performing a Fourier transform by simultaneous matrix vector multiplication (MVM) operations in respective plural CCD/CID arrays in parallel in O(1) steps. For example, in one embodiment, a first CCD/CID array stores charge packets representing a first matrix operator based upon permutations of a Hartley transform and computes the Fourier transform of an incoming vector. A second CCD/CID array stores charge packets representing a second matrix operator based upon different permutations of a Hartley transform and computes the Fourier transform of an incoming vector. The incoming vector is applied to the inputs of the two CCD/CID arrays simultaneously, and the real and imaginary parts of the Fourier transform are produced simultaneously in the time required to perform a single MVM operation in a CCD/CID array.

Abstract: A charge transfer device comprising charge transfer means for transferring charges, a floating diffusion layer for accumulating the charges transferred from said charge transfer means, a floating gate electrode formed on said floating diffusion layer via an insulating layer, charge detection means connected to the floating gate electrode for outputting a voltage corresponding to an amount of charges accumulated in the floating diffusion layer, first precharge means connected to the floating gate electrode, the first precharge means starting precharging of the floating gate electrode responsive to transition of a first pulse voltage from a first state to a second state, the first precharge means terminating precharging of the floating gate electrode responsive to transition of the first pulse voltage from the second state to the first state, second precharge means connected to the floating diffusion layer, the second precharge means starting precharging of the floating diffusion layer responsive to transition

Abstract: Channel coupled feedback- technology for implementing many analog and digital signal processing functions in a single-polysilicon digital IC fabrication process is described. Field effect transistors are constructed having a common channel and the substrate regions of the field effect transistors in the channel are electronically connected. Thus, a fixed amount of charge can freely move within the channel in response to the application of the signal to be processed. By sensing the charge transferred within the channel when the input signal is applied, many signal processing functions are possible. Fixed-gain amplifiers, offset compensated amplifiers, integrators, differentiators, analog-to-digital converters, digital-to-analog converters, switchable gain amplifiers, automatic gain control systems, and linear transform computation circuits are constructed entirely with field effect transistors, eliminating the need for passive components for most signal processing functions.

Abstract: A charge transfer device formed on a semiconductor substrate comprising: a charge transfer section formed on the semiconductor substrate for transferring charges, a floating gate having a floating gate diffusion layer formed on the semiconductor substrate for accumulating the charges transferred from the charge transfer section, an output gate section formed between the charge transfer section and the floating gate on the semiconductor substrate, and a charge detecting circuit electrically connected to the floating gate for outputting a voltage corresponding to the amount of the charges accumulated in the floating gate diffusion layer, the output gate section having a first output gate region adjacent to the charge transfer means and a second output gate region adjacent to the floating gate diffusion layer, the first output gate region having a first output gate electrode formed thereon with an insulating film therebetween, the second output gate region having a second output gate electrode formed thereon wit

Abstract: A mobile telephone system with two home location register units mirroring each other is disclosed. In the event of a crash in one unit a backup copy is first loaded. Thereafter, records in the loaded backup copy that have changed after the latest position dump before the crash are updated with information from the other home location register unit, the mirror copy of which is updated after the position dump.

Abstract: A charge transfer device formed on a semiconductor substrate comprising: a charge transfer section formed on the semiconductor substrate for transferring charges, a floating gate having a floating gate diffusion layer formed on the semiconductor substrate for accumulating the charges transferred from the charge transfer section, an output gate section formed between the charge transfer section and the floating gate on the semiconductor substrate, and a charge detecting circuit electrically connected to the floating gate for outputting a voltage corresponding to the amount of the charges accumulated in the floating gate diffusion layer, the output gate section having a first output gate region adjacent to the charge transfer means and a second output gate region adjacent to the floating gate diffusion layer, the first output gate region having a first output gate electrode formed thereon with an insulating film therebetween, the second output gate region having a second output gate electrode formed thereon wit

Abstract: A charge transfer device formed on a semiconductor substrate comprising: a charge transfer section formed on the semiconductor substrate for transferring charges, a floating gate having a floating gate diffusion layer formed on the semiconductor substrate for accumulating the charges transferred from the charge transfer section, an output gate section formed between the charge transfer section and the floating gate on the semiconductor substrate, and a charge detecting circuit electrically connected to the floating gate for outputting a voltage corresponding to the amount of the charges accumulated in the floating gate diffusion layer, the output gate section having a first output gate region adjacent to the charge transfer means and a second output gate region adjacent to the floating gate diffusion layer, the first output gate region having a first output gate electrode formed thereon with an insulating film therebetween, the second output gate region having a second output gate electrode formed thereon wit

Abstract: The present invention is embodied in a charge coupled device (CCD)/charge injection device (CID) architecture capable of performing a Fourier transform by simultaneous matrix vector multiplication (MVM) operations in respective plural CCD/CID arrays in parallel in O(1) steps. For example, in one embodiment, a first CCD/CID array stores charge packets representing a first matrix operator based upon permutations of a Hartley transform and computes the Fourier transform of an incoming vector. A second CCD/CID array stores charge packets representing a second matrix operator based upon different permutations of a Hartley transform and computes the Fourier transform of an incoming vector. The incoming vector is applied to the inputs of the two CCD/CID arrays simultaneously, and the real and imaginary parts of the Fourier transform are produced simultaneously in the time required to perform a single MVM operation in a CCD/CID array.

Abstract: The invention concerns a charge-to-voltage converter including a read diode and a read transistor of no-load gain G.sub.o. The converter includes complementary circuits assuring a conversion gain greater than G.sub.o during read periods and a conversion gain substantially equal zero at other times.

Abstract: The process tracking bias generator for antiblooming structures includes a lateral overflow antiblooming drain and bias circuitry coupled to the antiblooming drain for automatically adjusting a bias for the antiblooming drain independent of process variations.

Abstract: The present invention provides a memory device for realizing an analog memory that or a multilevel memory easy to produce and requires only small scale circuitry. The memory device comprises: a CCD array "Ai" linearly arranged a refresh circuit "R" connected to a CCD on one end CCD array; a shaping circuit connected to a CCD on another end of the CCD array; a feedback line "FL" for connecting an output the shaping circuit to an input of the refresh a topology difference clock line "CL" for transmitting data CCD array.

Abstract: A bucket brigade analog delay line with voltage limiting feedback includes an input stage for receiving an input signal and a series of delay stages coupled to the input stage for propagating the input signal through the line. Each delay stage contains a storage capacitor for holding either a signal charge or a reference charge, a transfer device for transferring charge from one stage to another at regular clock intervals, and a tap circuit for allowing external sampling of the propagated input signal. Each delay stage also includes a negative feedback amplifier for maintaining the drain terminal of the transfer device at a constant potential during charge transfer, thereby eliminating errors caused by finite output impedance of the transfer device. The negative feedback amplifier also prevents overvoltage conditions which could result in failure of the charge transfer devices.

Abstract: Herein disclosed is an amplification circuit for realizing a substantially high sensitivity with a simple structure. The amplification circuit comprises: a first capacitor C1 for receiving a signal charge; a source-follower circuit for receiving a voltage of the first capacitor C1; an inversion amplification circuit including a source-earth type amplification MOSFET Q5 having its gate fed with the output signal of the source-follower circuit through a second capacitor C2; a feedback third capacitor C3 connected between the gate and drain of the amplification MOSFET Q5; and a switch element Q6 for feeding the gate of the amplification MOSFET Q5 with a predetermined bias voltage while the signal charge of the first capacitor C1 is being reset. The amplification MOSFET Q5 has its drain equipped as load means with a depletion type MOSFET Q4 having its gate and source connected, and the depletion type MOSFET Q4 has its source given the same potential as the substrate potential thereof.

Abstract: The present invention is directed to an output circuit for a charge transfer device which can reduce a coupling voltage of a floating diffusion type charge detecting section and in which a DC fluctuation of an output from a source-follower stage can be suppressed. A dummy floating diffusion region (FD2) is provided and an output thereof is converted by and derived from a bias generator circuit (7) of a source-follower configuration as a positive phase output. This positive phase output is supplied to a load MOS transistor (Q.sub.2) of a source-follower circuit (5) as a bias voltage and also fed back to the load MOS transistor (Q.sub.6) of the bias generator circuit (7) as a gate voltage.

Abstract: There is disclosed a solid-state image sensor comprising: photo-detecting devices arranged in a matrix structure for receiving external light signals; vertical charge transfer device interposed between the columns of said photo-detecting device for vertically transferring the charges produced from said photo-detecting device according to external control signal; first horizontal charge transfer device for horizontally transferring the charges coming out of said vertical charge transfer device according to external control signal; output control device for controlling the charges flowing from said first horizontal charge transfer device to said output device; second horizontal charge transfer device for transferring the output charges of said first horizontal charge transfer device controlled by said output control device to said vertical charge transfer device according to external control signal; and a feedback line for connecting the output of said first horizontal charge transfer device to the input of sai

Abstract: A high-gain, low-noise transistor amplifier comprises an input, an output, and first and second field effect transistors each having a gate, a drain, and a source and being formed in a common semiconductor substrate. The second transistor is a depletion mode transistor if it is of the same conductivity type as the first but is an enhancement mode transistor if it is of opposite conductivity type with respect to the first. In an amplifier configuration, the input is coupled to the gate of the first transistor, the source of the first transistor is coupled to the gate of the second transistor, the source of the second transistor is coupled to the output, and there is a direct-coupled feedback path from the source of the second transistor to the drain of the first transistor. At least the first transistor is formed in an isolated well of conductivity opposite to that of the substrate in the semiconductor substrate and its source is coupled directly to that well.

Abstract: A control device for a charge detection circuit comprising a CCD final gate electrode formed on a semiconductor substrate, an electric potential barrier forming gate electrode placed adjacent to the CCD final gate electrode, a diffusion region formed adjacent to the electric potential barrier forming gate electrode, a reset transistor connected to the diffusion region, a source follower circuit which uses as an input an electric potential in the diffusion region, a sample and hold circuit for receiving the output of the source follower circuit at a specified timing, a reference voltage source which has a value determined by the dynamic range of the source follower circuit, and an integrator which integrates a difference between the output of the sample and hold circuit and the output of the reference voltage source, and applies a value obtained by the integration to the electric potential barrier forming gate electrode.

Abstract: An input structure of CCD comprises a primary register having an input gate and a source region and an automatic biasing system which generates a feedback signal to be fed back to input of the primary register. The output of the automatic biasing system is connected to one of the input gate and the source of the primary register for supplying the feedback signal thereto for adjusting input bias level of the primary register. The other one of the input gate and the source is connected to an information signal input terminal to receive therefrom an information signal to be transferred therethrough.

Abstract: An input bias circuit employs a gate input type CCD register and an inversion-type amplifier. An output node of the inversion-type amplifier is connected to the input gate electrode of the CCD register, and an input signal to be biased is supplied to the input gate electrode. An output node of the inversion-type amplifier is connected to the floating diffusion region of the CCD register, and a signal charge is picked up from the floating diffusion region. A comparator performs comparison among the low level of the injection pulse supplied to the input diffusion region (which serves as an input diode), the potential level of the input signal supplied to the input gate electrode of the CCD register, and the level of the low-level generated by a low-level signal generating means. On the basis of this comparison, the potential level of the input signal of the CCD register is controlled such that it is higher than the low level of the injection pulse.

Abstract: A solid-state imaging device includes on a semiconductor substrate of a first conductivity type, a well of the opposite conductivity type and, in addition, a plurality of light-sensitive elements formed in the well. A reverse bias voltage applied to the semiconductor substrate with respect to the well causes charge stored in the light-sensitive elements less than or equal to a potential barrier voltage to leak out into the semiconductor substrate. On the substrate a detection circuit detects the resistance of the semiconductor substrate and a setting circuit sets the reverse bias voltage in such a manner as to keep the potential barrier voltage constant, based on the resistance detected by the detection circuit.

Abstract: An input structure of CCD comprises a primary register having an input gate and a source region and an automatic biasing system which generates a feedback signal to be fed back to input of the primary register. The output of the automatic biasing system is connected to one of the input gate and the source of the primary register for supplying the feedback signal thereto for adjusting input bias level of the primary register. The other one of the input gate and the source is connected to an information signal input terminal to receive therefrom an information signal to be transferred therethrough.

Abstract: A charge coupled device employs peak hold circuits for detecting electric charges transferred through reference registers for facilitating automatic iput bias control. The peak hold circuits are respectively connected to a pair of reference registers which are so designed that one of the reference registers has a given maximum rating and the other reference register is adapted to transfer electric charge having a given fraction of the maximum charge rating of the aforementioned one of registers. The peak hold circuits provide peak values of the outputs of the reference registers to a comparator which feedback controls the input bias of the one of the register. This controlled bias is also applied to an input bias for a signal register which is designed for transferring input electric charge.

Abstract: The invention relates to a semiconductor device including a charge transfer device having an output stage (8). The output stage (8) has a read-out zone (9), a feedback capacitor (11) and an amplifier (10). An inverting input (15) of the amplifier (10) is connected to the read-out zone (9) and an output (16) of the amplifier (10) is fed back via the feedback capacitor (11) to the inverting input (15). According to the invention, the capacitor (11) is a capacitor of the MOS type and means are provided by which during operation of the charge transfer device the surface potential of a surface region (13) in the capacitor (11) is solely determined by the potential of the read-out zone (9). Consequently, the capacitance of the feedback capacitor (11) is dependent upon the potential across it, as a result of which there is a linear relation between the charge supplied to the read-out zone (9) and the voltage variation across the capacitor (11 ).

Abstract: The present invention enables improved response time in a linked cell discharge detection device by providing additional discharge paths when indicated to speed discharge of circuit nodes in a plurality of detection cells. A circuit node is periodically precharged by connection to a voltage source. This node is selectively discharged in accordance with at least one input signal. An output device connected to the circuit node generates an output indicative of the state of the charge on the circuit node. An additional discharge device which is responsive to the output device provides an additional discharge path when the output signal indicates a charge on the circuit node less than a predetermined magnitude. This additional discharge path speeds up the complete discharge of the circuit node.

Abstract: A pulse counting device wherein a number of pulses is stored in a first register out of a plurality of registers, and subsequently a new pulse number counted is stored in the first register and pulse numbers stored in the registers are successively shifted with a pulse number erased from a final register. The pulse numbers stored in the respective registers are corrected dependent on the latest pulse number stored in the first register, and a value dependent on the corrected values stored in all of the registers is displayed. If the latest pulse number is abruptly varied in excess of a certain preset value upon comparison with the pulse numbers in the registers, then the pulse numbers in the registers are corrected with a value dependent on the latest pulse number.

Abstract: A charge-coupled-device analog input circuit, for generating packets of electrical charge representative of samples of a differentiated analog input signal, and a charge-coupled-device analog output circuit, for generating an analog output signal by a process of integration of the signal values represented by the charge packets. The differentiating input circuit includes a signal input circuit with a relatively large input capacitance, and a separate bias input circuit with a relatively small input capacitance, to generate charge packets at a selected bias level. The integrating output circuit includes a set of bias gates for removing from each packet an amount of charge equal to the bias charge generated at the input circuit, and also includes a feedback loop for adding to each charge packet presented at the output circuit a charge equivalent to the cumulative sum of all signal samples derived by the circuit.

Abstract: A bias voltage setting circuit for a main charge coupled device is disclosed in which first and second auxiliary charge coupled devices are formed on a semiconductor substrate together with the main charge coupled device, a reference voltage is generated by the first auxiliary charge coupled device, the output voltage of the second auxiliary charge coupled device is compared with the reference voltage by means of a comparator, the bias voltage applied to the second auxiliary charge coupled device is automatically changed by a feedback circuit so that the output voltage of the second auxiliary charge coupled device is approximately equal to the reference voltage, and the bias voltage applied to the second auxiliary charge coupled device is also used as the bias voltage applied to the main charge coupled device.

Abstract: Charge transfer devices exhibit transfer inefficiencies, so that a part of a transferred charge packet is left and lags the original charge packet. This results in "smearing" of the original charge packet, thereby adversely affecting the unit-function response and the frequency response of the charge transfer device. The invention provides a solution to this problem, utilizing a compensation charge derived from the original charge packet, which at a suitable instant is applied to a point where the residual charge is cancelled via a feedback loop.

Abstract: The invention relates to an electrical filter circuit operated with a definite sampling and clock frequency f.sub.T, such filter being made up of CTD elements, and having at least one bipolar or quadripolar resonator in the form of a self-contained conductor loop (for example, C.sub.1, C.sub.2) with unidirectional transmission behavior.Differences in the transfer capacitances of such circuits are reduced, as far as possible, in order to thereby simplify integrated manufacture as far as possible, by positioning the frequency band to be filtered out at a frequency position which lies above half the clock frequency (f.sub.T /2), or in the range from f.sub.T /2 through 3f.sub.T /2.