Abstract: A fuse circuit includes an E-fuse array including a plurality of E-fuse elements configured to store fuse data; a latch block including a plurality of latch groups configured to latch the fuse data read from the E-fuse array; and a control block configured to output latch reset signals corresponding to the plurality of latch groups in response to an apparatus reset signal and a clock signal, wherein the control block sequentially enables the latch reset signals.

Abstract: A shift register circuit includes plural shift register stages for providing plural gate signals. Each shift register stage includes a driving unit, an input unit, a driving adjustment unit and a pull-down unit. The driving unit is utilized for outputting a gate signal according to a system clock and a driving control voltage. The input unit is put in use for outputting the driving control voltage according to an input control signal and a first input signal. The driving adjustment unit is employed for adjusting the driving control voltage according to a second input signal and a third input signal. The pull-down unit is used for pulling down the gate signal and the driving control voltage according to a fourth input signal.

Abstract: The grayscale voltage generating circuit comprises an input/driving stage circuit amplifying an input voltage and output stage circuits receiving a output voltage from the input/driving stage circuit, outputting one of the grayscale voltages, and having a capacitor to keep a voltage level of the grayscale voltage. The output stage circuits are sequentially switched to be connected with the input/driving stage circuit, and an output voltage from the input/driving stage circuit is fed to the plurality of output stage circuits in order. Each of the output stage circuits outputs the grayscale voltage based on a voltage held in the capacitor irrespective of connection with the input/driving stage circuit.

Abstract: A serial shift register and method for simultaneously storing bits of data and a serially advancing pointer is provided. In one embodiment, each stage of the shift register may have only two latches: one to store a bit of pointer information and one to store data.