Abstract: A detection device includes a plurality of detection elements arranged in a matrix having a row-column configuration in a detection area, a plurality of scan lines each coupled to the detection elements arranged in a first direction, a drive circuit configured to drive the scan lines, a plurality of output signal lines each coupled to the detection elements arranged in a second direction different from the first direction, and a detection circuit configured to be supplied with detection signals from the detection elements through the output signal lines.

Abstract: A display device includes scan lines, pixels electrically connected to the scan lines, and a scan driver including stages for supplying scan signals through the scan lines to the pixels. The stages include a stage that includes the following elements: a first node setting unit for setting a voltage of a first node; a second node setting unit for setting a voltage of a second node based on the voltage of the first node; a third node setting unit for setting a voltage of a third node based on the voltage of the second node; and an output unit for outputting a scan signal based on the voltage of the third node. Each of the first and third node setting units includes an N-type transistor. The scan driver further includes a first charge pump for supplying a first bias voltage to a back-gate electrode of the N-type transistor.

Abstract: A semiconductor device or the like with a novel structure that can change the orientation of the display is provided. A semiconductor device or the like with a novel structure, in which a degradation in transistor characteristics can be suppressed, is provided. A semiconductor device or the like with a novel structure, in which operation speed can be increased, is provided. A semiconductor device or the like with a novel structure, in which a dielectric breakdown of a transistor can be suppressed, is provided. The semiconductor device or the like has a circuit configuration capable of switching between a first operation and a second operation by changing the potentials of wirings. By switching between these two operations, the scan direction is easily changed. The semiconductor device is configured to change the scan direction.

Abstract: In a pulse output circuit in a shift register, a power source line which is connected to a transistor in an output portion connected to a pulse output circuit at the next stage is set to a low-potential drive voltage, and a power source line which is connected to a transistor in an output portion connected to a scan signal line is set to a variable potential drive voltage. The variable potential drive voltage is the low-potential drive voltage in a normal mode, and can be either a high-potential drive voltage or the low-potential drive voltage in a batch mode. In the batch mode, display scan signals can be output to a plurality of scan signal lines at the same timing in a batch.

Abstract: The present disclosure provides a shift register unit, a driving method, a driving circuit and a display device. The shift register unit includes a first node potential adjustment circuit, a first tank circuit, a second node control circuit, a second tank circuit, a third node control circuit, a first node control circuit, and an output circuit; the first node potential adjustment circuit changes the potential of the first node according to the adjustment clock signal under the control of the potential of the first node; the first tank circuit is used to maintain the potential of the first node; the third node control circuit controls the potential of the third isolation node and the potential of the fourth node; the second node control circuit controls the potential of the second isolation node.

Abstract: A backlight module includes at least one drive light-emitting group. The drive light-emitting group includes a drive unit provided with plurality of signal transmission channels, a plurality of light-emitting units and a plurality of line groups. The signal transmission channel is connected to the light-emitting unit through the line group. The signal transmission channel, the line group and the light-emitting unit are arranged in one-to-one correspondence. The line group includes a main transmission line and a compensation line arranged in parallel. The compensation lines of the plurality of line groups are connected through a control switch group. When there is an abnormal signal transmission channel, the control switch group is enabled to control a compensation line corresponding to the abnormal signal transmission channel to be conducted with compensation line corresponding to at least one normal signal transmission channel.

Abstract: A display device includes a display panel including pixels in a display area, scan lines disposed in the display area and electrically connected to the pixels, a gate driving circuit disposed in the display area and electrically connected to the scan lines, and clock lines disposed in the display area and electrically connected to the gate driving circuit. The gate driving circuit includes stage blocks adjacent to each other and outputting a scan signal in response to a clock signal provided through a corresponding clock line among the clock lines, and a scan signal output from a stage block among the stage blocks is supplied to scan lines of another stage block among the stage blocks.

Abstract: A matrix-array detector having: an array of pixels arranged in a matrix along rows and down columns, each pixel for generating a signal according to a physical effect; a signal generator for generating two clock signals that are phase-shifted relative to one another; and a row-addressing device including a shift register, the shift register including a plurality of stages arranged in a cascade, each stage for receiving, in alternation from one stage to another, one clock signal from the two clock signals, and delivering an intermediate output signal that takes a high value and a low value allowing the pixels of the row to be activated and to be deactivated, respectively. The signal generator is also for generating a third clock signal.

Abstract: The present disclosure provides a shift register unit, including a detection signal input sub-circuit, a display signal input sub-circuit, an output circuit, a pull-down control circuit and a signal output terminal, the output circuit includes a pull-up sub-circuit and a pull-down sub-circuit, the pull-down control circuit includes a selection sub-circuit and a plurality of pull-down control sub-circuits. The present disclosure further provides a gate driving circuit, a display panel and a driving method for driving the display panel. The shift register unit has a simple structure and a long service life.

Abstract: To suppress malfunctions in a shift register circuit. A shift register having a plurality of flip-flop circuits is provided. The flip-flop circuit includes a transistor 11, a transistor 12, a transistor 13, a transistor 14, and a transistor 15. When the transistor 13 or the transistor 14 is turned on in a non-selection period, the potential of a node A is set, so that the node A is prevented from entering into a floating state.

Abstract: The present disclosure provides a gate driving circuit, a method of driving a gate driving circuit, and a display panel. The gate driving circuit includes a plurality of driving units connected in cascade. Each driving unit includes: N shift register units; and a mode control circuit connected to the N shift register units, wherein the mode control circuit is configured to receive a control signal for the driving unit, and connect the N shift register units in one of a plurality of resolution modes under the control of the control signal.

Abstract: A gate driver includes a first shift register to supply a gate signal to a plurality of gate lines through output nodes, and a second shift register to supply the gate signal to the gate lines through output nodes. The gate signal is supplied from the first shift register to one side of an i-th gate line and supplied from the second shift register to the other side of the i-th gate line, then the gate signal is supplied from the second shift register to the other side of the i-th gate line, then the gate signal is supplied from the first shift register to one side of the i-th gate line, and then, the gate signal is supplied from the first shift register to one side of the i-th gate line and simultaneously supplied from the second shift register to the other side of the i-th gate line.

Abstract: A semiconductor device or the like with a novel structure that can change the orientation of the display is provided. A semiconductor device or the like with a novel structure, in which a degradation in transistor characteristics can be suppressed, is provided. A semiconductor device or the like with a novel structure, in which operation speed can be increased, is provided. A semiconductor device or the like with a novel structure, in which a dielectric breakdown of a transistor can be suppressed, is provided. The semiconductor device or the like has a circuit configuration capable of switching between a first operation and a second operation by changing the potentials of wirings. By switching between these two operations, the scan direction is easily changed. The semiconductor device is configured to change the scan direction.

Abstract: A reversible superconducting circuit includes two Josephson transmission lines. Inductors connect Josephson Junctions in the array. Each transmission line passes a fluxon along the Junctions. The circuit includes an interface with first and second shunt capacitors coupled to the first and second transmission lines, and a third shunt capacitor, forming a connecting circuit with the first and second shunt capacitors. The shunt capacitors include Josephson junctions in parallel. The connecting circuit receives an input fluxon and transmits an output fluxon. The circuit also includes a Josephson Junction and inductor in parallel with the third shunt capacitor, forming a storage circuit. The storage circuit stores a SFQ. The output fluxon has polarity based on the SFQ stored when the first fluxon is received. The input fluxon causes the polarity of the stored SFQ to be the same as the polarity of the input fluxon, immediately after the input fluxon is received.

Abstract: A semiconductor device or the like with a novel structure that can change the orientation of the display is provided. A semiconductor device or the like with a novel structure, in which a degradation in transistor characteristics can be suppressed, is provided. A semiconductor device or the like with a novel structure, in which operation speed can be increased, is provided. A semiconductor device or the like with a novel structure, in which a dielectric breakdown of a transistor can be suppressed, is provided. The semiconductor device or the like has a circuit configuration capable of switching between a first operation and a second operation by changing the potentials of wirings. By switching between these two operations, the scan direction is easily changed. The semiconductor device is configured to change the scan direction.

Abstract: Proposed is a gate driver and a display device having the same. The gate driver includes a plurality of stage circuits, wherein each of the plurality of stage circuits includes a shift register configured to control charging and discharging of a Q node and a QB node, and a plurality of output buffers sequentially connected to the shift register, wherein each of the output buffers includes a first transistor configured to transmit a voltage of the Q node to a Q? node, a pull-up transistor configured to output a clock signal to a gate line in response to a voltage of the Q? node, and a pull-down transistor configured to output a low-potential voltage to the gate line in response to a voltage of the QB node.

Abstract: There is provided a gate driving circuit including cascaded Gate Driver On Array (GOA) units, each GOA unit drives a row of pixels and includes a starting sub-unit, an output sub-unit and an output terminal, in the GOA unit at a first stage, the starting sub-unit is coupled with a starting signal, a first control signal, a second control signal and a constant voltage potential, and the output sub-unit is coupled with a first clock signal and a first power supply signal; in the GOA unit at an nth stage, the starting sub-unit is coupled with the starting signal, the first control signal, the second control signal and the output terminal of the GOA unit at an (n?1)th stage, the output sub-unit is coupled with the first power supply signal and the output terminal of the GOA unit at an (n+1)th stage, n is an integer greater than 1.

Abstract: A display panel includes a scan driving circuit, signal pins and a first gating circuit. Signal pins include a detection signal pin and an enable signal pin. The scan driving circuit includes scan drive units disposed in a cascade manner. The first gating circuit includes a first switch unit and a second switch unit. An input terminal of the first switch unit is electrically connected to a scan signal detection terminal of an Nth-stage scan drive unit. An input terminal of the second switch unit is electrically connected to a scan signal detection terminal of a first-stage scan drive unit. An output terminal of the first switch unit and an output terminal of the second switch unit are both electrically connected to the detection signal pin. The first switch unit is configured to turn on in a forward scan detection stage and turn off in a backward scan detection stage. The second switch unit is configured to turn on in the backward scan detection stage and turn off in the backward scan detection stage.

Abstract: A gate driving circuit and a display device including the same are discussed. A signal transmitter of the gate driving circuit can include a first charge controller configured to charge a first control node in response to a voltage of a VST node, a second charge controller configured to charge a second control node using a first transistor that is turned on in response to an (N+1)th clock generated following an Nth clock, a first discharge controller configured to discharge the first control node in a charging period of the second control node, and a second discharge controller configured to discharge the second control node when the voltage of the VST node is a high voltage or in a charging period of the first control node.

Abstract: A unit circuit constituting each stage of a shift register serving as a gate driver of a display device charges an internal node to an H level via a transistor T2 when an output signal G(n?4) of a preceding stage turns to the H level and sets the internal node to an L level via a transistor T3 when an output signal G(n+8) of a succeeding stage turns to the H level. Each of the unit circuits of last eight stages in the gate driver is provided with a transistor T4 including a gate terminal to which the signal G(n?4) is applied and a drain terminal connected to the internal node. A signal is applied to a source terminal of the transistor T4, the signal being at the H level during a period when the internal node of any of the last eight stages is to be set to the H level, and being the L level during the other periods. This suppresses a voltage fluctuation generated in the internal node when a stabilization circuit does not normally function.

Abstract: A driving method, a driving circuitry and a display device are provided. The driving method is applied to a touch display panel. A shift register unit in a gate driving circuitry in the touch display panel is electrically coupled with a clock signal terminal, the clock signal terminal is used for providing a clock signal to a pull-up circuit in the shift register unit, and a display cycle includes a display time period and a touch time period. The driving method includes: within a period during which initial N rows of gate lines are turned on after entering the display time period from the touch time period in the display cycle, controlling and adjusting the clock signal to increase a falling speed of a potential of a gate drive signal outputted by the shift register unit; N is a positive integer. The phenomenon of poor horizontal stripes is improved.

Abstract: A semiconductor device including a biometric recognition function and a touch sensor or near touch sensor function is provided. The semiconductor device includes a light-emitting device and an imaging device. The imaging device includes a gate driver circuit and m rows of pixels (m is an integer more than or equal to 2). The gate driver circuit includes a plurality of first register circuits and second register circuits whose number is less than that of the first register circuits. The first register circuits are connected with each other in series and the second register circuits are connected with each other in series. The gate driver circuit has a function of operating in the first mode and the second mode. In the first mode, the first register circuits are in the on state and the second register circuits are in the off state, and in the second mode, the second register circuits are in the on state and the first register circuits are in the off state.

Abstract: A display apparatus with low power consumption is provided. The display apparatus includes a circuit for boosting a signal voltage output from a gate driver. The signal voltage from the gate driver can be boosted and then supplied to a pixel, which is suitable for driving a display device with a high threshold voltage. Furthermore, by utilizing a boosting function, output of the gate driver can be reduced, and power consumption can also be reduced. By combination with a pixel having a boosting function of image data, a display apparatus with lower power consumption can be achieved.

Abstract: Provided are a display panel, a method for the same and a display device. In the display panel, in a same shift register unit of a shift register circuit, a pull-down module is electrically connected to a first node, a second node, a first level signal terminal, and a signal output terminal separately. The pull-down module transmits a first level signal of the first level signal terminal to the second node and the signal output terminal under the control of a potential of the first node. The pull-down module includes at least a first transistor. A gate of the first transistor is electrically connected to the first node; the pull-down control module is electrically connected to the first node and the scanning control terminal separately; and the pull-down control module controls a scanning control signal of the scanning control terminal to be transmitted to the first node.

Abstract: A display device includes: a substrate including first and second display regions and first and second non-display regions; a plurality of first pixels in the first display region; a plurality of second pixels in the second display region; a plurality of first scan stage circuits in the first non-display region, the first scan stage circuits configured to provide a scan signal to the first pixels; a plurality of second scan stage circuits in the second non-display region, the second scan stage circuits configured to provide a scan signal to the second pixels; a plurality of dummy scan stage circuits in the second non-display region, the dummy scan stage circuits being between the second scan stage circuits; and a scan bridge line in the second non-display region, the scan bridge line connecting one second scan stage circuit among the second scan stage circuits and a dummy scan stage circuit adjacent thereto.

Abstract: A shift register unit, a gate drive circuit, and a drive method are provided. The shift register unit includes a first input circuit, a second input circuit, and an output circuit. The first input circuit is configured to charge a first node in response to a first input signal to control a level of the first node; the second input circuit is configured to charge a second node in response to a second input signal to control a level of the second node; and the output circuit is configured to output an output signal to an output terminal under common control of the level of the first node and the level of the second node; the first input circuit includes a first transistor and a first capacitor, and a second electrode of the first capacitor is connected to the first electrode of the first transistor.

Abstract: Disclosed are an array substrate row drive circuit unit, a drive circuit and a liquid crystal display panel thereof. The array substrate row drive circuit unit includes a pull-up control module; a pull-up module; a pull-down module connected to the pull-up control module and the pull-up module and being configured to simultaneously pull down a pull-up control signal and a row scan signal of a current stage array substrate row drive circuit unit to a low level according to a direct current low voltage signal when receiving the row scan signal; and a voltage dividing module electrically connected to the pull-up module and being configured to increase a falling edge during pull-down when the pull-down module simultaneously pulls down the pull-up control signal and the row scan signal of the current stage array substrate row drive circuit unit to a low level.

Abstract: A semiconductor device which shifts a low-level signal is provided. In an example, a first transistor including a first terminal electrically connected to a first wiring and a second terminal electrically connected to a second wiring, a second transistor including a first terminal electrically connected to a third wiring and a second terminal electrically connected to the second wiring, a third transistor including a first terminal electrically connected to a fourth wiring and a second terminal electrically connected to a gate of the second transistor, a fourth transistor including a first terminal electrically connected to a fifth wiring, a second terminal electrically connected to a gate of the third transistor, and a gate electrically connected to a sixth wiring, and a first switch including a first terminal electrically connected to the third wiring and a second terminal electrically connected to a gate of the first transistor are included.

Abstract: A gate driving unit, a gate driving circuit, a gate driving method, and a display device are provided. The gate driving unit includes a first output circuit and a second output circuit; the second output circuit comprises a first output sub-circuit; the first output circuit is respectively electrically connected to the first node, the second node and the first gate driving signal output end and is configured to control the first gate driving signal output end to output a first gate driving signal under the control of the potential of the first node and the potential of the second node; the first output sub-circuit is respectively electrically connected to the first node, the second gate driving signal output end and the first clock signal end, and is configured to control the second gate driving signal output end to be connected to the first clock signal end.

Abstract: The present disclosure discloses a shift register, a gate driving circuit and a display device. The shift register includes a display pre-charge reset circuit, a sensing cascade circuit, a sensing pre-charge reset circuit, a pull-down control circuit and an output circuit, where the display pre-charge reset circuit, the sensing cascade circuit and the sensing pre-charge reset circuit share the same pull-down control circuit and the same output circuit, the output circuit is coupled to at least one signal output terminal, the output circuit includes output sub-circuits in one-to-one correspondence with the at least one signal output terminal, and each output sub-circuit is configured to write a driving clock signal into the corresponding signal output terminal in a display output stage and a sensing output stage in response to a control of a voltage of a pull-up node in an effective level state.

Abstract: The present disclosure provides a phase shifting device, a driving method thereof, and an antenna. The phase shifting device of the present disclosure includes: data lines, scan lines and phase shifting units. Each phase shifting unit includes: a switch sub-circuit and a phase shifter. Control terminals of the switch sub-circuits in a same row are coupled to a same scan line, first terminals of the switch sub-circuits in a same column are coupled to a same data line, and a second terminal of each switch sub-circuit is coupled to a phase shifter included in the phase shifting unit to which the switch sub-circuit belongs. Each switch sub-circuit is configured to transmit, in response to a switch control signal provided by the scan line, a data voltage signal provided by the data line to the phase shifter to drive the phase shifter.

Abstract: A semiconductor device which shifts a low-level signal is provided. In an example, a first transistor including a first terminal electrically connected to a first wiring and a second terminal electrically connected to a second wiring, a second transistor including a first terminal electrically connected to a third wiring and a second terminal electrically connected to the second wiring, a third transistor including a first terminal electrically connected to a fourth wiring and a second terminal electrically connected to a gate of the second transistor, a fourth transistor including a first terminal electrically connected to a fifth wiring, a second terminal electrically connected to a gate of the third transistor, and a gate electrically connected to a sixth wiring, and a first switch including a first terminal electrically connected to the third wiring and a second terminal electrically connected to a gate of the first transistor are included.

Abstract: A shift register circuit includes a first input sub-circuit, an output sub-circuit and an output control sub-circuit. The first input sub-circuit transmits a signal received at a second signal input terminal to a pull-up node. The output sub-circuit transmits a signal received at a first clock signal terminal to a shift signal output terminal, and transmits a signal received at an output signal transmission terminal to a first scan signal output terminal. The output control sub-circuit transmits a signal received at a chamfering signal terminal to the first scan signal output terminal in a predetermined time before the first scan signal output terminal stops outputting the signal from the output signal transmission terminal. The chamfering signal terminal transmits a signal with a voltage amplitude within a variation range of a voltage amplitude of a signal of the first scan signal output terminal.

Abstract: A multiple input device is disclosed. The multiple input device includes a semiconductor structure extending in a first direction, a first dielectric material surrounding a portion of the semiconductor structure, a floating gate on the first dielectric material and surrounding the portion of the semiconductor structure, and a second dielectric material on the floating gate and surrounding the portion of the semiconductor structure. The multiple input device also includes a plurality of control gates on the second dielectric material. At least one of the control gates extends vertically away from the semiconductor structure in a second direction and at least one of the control gates extends vertically away from the semiconductor structure in a third direction.

Abstract: A shift register circuit is provided. The shift register circuit includes an input sub-circuit, an output sub-circuit, a first control sub-circuit and a second control sub-circuit. The input sub-circuit is connected to a first signal input terminal, a second signal input terminal and a first node. The output sub-circuit is connected to the first node, a first clock signal terminal and a first output terminal. The first control sub-circuit is connected to a first power supply voltage terminal, a second power supply voltage terminal, the first node and a second node. The second control sub-circuit is connected to the second power supply voltage terminal, a third power supply voltage terminal, the second node and a third node, and the third node is further connected to the input sub-circuit.

Abstract: Disclosed are a row drive circuit of array substrate and a display device. The row drive circuit includes N row drive units (10) arranged in cascade and auxiliary circuit units. The Nth row drive unit (10) is configured to output Nth gate driving signal to pre-charge and charge the Nth row of sub-pixels, when its signal input end receives the gate driving signal output by (N?2)th row drive unit (10). The Nth auxiliary circuit unit (20) is configured to control Nth row drive unit (10) skip pre-charging the sub-pixels, when (N?1)th timing control signal received by the first timing signal input end of Nth auxiliary circuit unit and (N+1)th timing control signal received by the second timing signal input end of Nth auxiliary circuit unit are high level. N is positive integer greater than or equal to two.

Abstract: A gate driver according to an exemplary embodiment of the present inventive concept includes a pull-up-pull-down circuit configured to pull up a gate signal to a high level of a first clock signal in a first duration and configured to pull down the gate signal to a low level of the first clock signal in a second duration, and a pull-down boosting circuit configured to output a first off voltage to the pull-up-pull-down part in the second duration in response to a second clock signal.

Abstract: The present disclosure provides a shift register unit, including: a first input sub-circuit configured to conduct a first voltage terminal with a first node under control of a first clock signal terminal; a first output sub-circuit configured to conduct a second voltage terminal with an output terminal under control of the first node; a second input sub-circuit configured to conduct an input terminal with a second node under control of the first clock signal terminal; a second output sub-circuit configured to conduct a second clock signal terminal with the output terminal under control of the second node; a first switching sub-circuit configured to conduct the first clock signal terminal with the first node under control of the second node; a second switching sub-circuit configured to conduct a third clock signal terminal with the storage sub-circuit under control of the first node.

Abstract: A gate driving unit circuit comprises an input sub-circuit and an output sub-circuit. The input sub-circuit is connected to a first pull-up node, a second pull-up node, and an input terminal, and transmits a signal input from the input terminal to the first pull-up node and the second pull-up node. The output sub-circuit is connected to the first pull-up node, the second pull-up node, a first control terminal, a third control terminal, a first output terminal, and a second output terminal. The output sub-circuit transmits a signal input through the first control terminal to the first output terminal, and transmits a signal input through the third control terminal to the second output terminal under the control of a potential of the second pull-up node, wherein, an effective voltage of a signal of the first control terminal is greater than that of a signal of the third control terminal.

Abstract: A shift register includes a first reset circuit having a first transistor and a second transistor, and a selection control circuit connected to a pull-down node, and control electrodes of the first and second transistors. First electrodes of the first and second transistors are connected to a first voltage terminal, and second electrodes of the first and second transistors are connected to a signal output terminal. The selection control circuit is configured to: control a line between the pull-down node and the control electrode of the first transistor, and a line between the pull-down node and the control electrode of the second transistor to be alternately closed. The first reset circuit is configured to output a voltage of the first voltage terminal to the signal output terminal under control of a potential at the pull-down node transmitted by the selection control circuit.

Abstract: The present application provides a shift register and a method of driving the same, and a gate driving circuit. In the shift register, an input sub-circuit is configured to output an input signal to a pull-up node under control of a first clock signal of a first clock signal terminal, an output sub-circuit is configured to output a second clock signal of a second clock signal terminal to the output terminal under control of a voltage level of the pull-up node, a reset sub-circuit is configured to reset voltage levels of the pull-up node and the output terminal under control of a voltage level of a pull-down node, and a reset control sub-circuit is configured to control the voltage level of the pull-down node such that the voltage levels of the pull-up node and the output terminal are reset to a level signal.

Abstract: The present disclosure provides a shift register unit, a driving method thereof, a gate driving circuit and a display device. The shift register unit includes a pull-up node state maintenance circuitry connected to a pull-up node and a first control voltage input end, and configured to control the pull-up node to be electrically connected to, or electrically disconnected from, the first control voltage input end in accordance with a potential at the pull-up node and an input potential at the first control voltage input end.

Abstract: A shift register unit, a gate driving circuit, a display device, and a driving method are provided. The shift register unit includes a first input circuit, an output control circuit, and an output circuit. The first input circuit is configured to output a first input signal to a first node in response to a first control signal; the output control circuit is configured to output an output control signal to a second node under control of a level of the first node; and the output circuit includes an output terminal, and the output circuit is configured to output an output signal to the output terminal under control of a level of the second node.

Abstract: Provided are a shift register unit and a control method thereof, a gate driving circuit and a control method thereof, and a display apparatus. The shift register unit may include: a first shift register coupled to an input signal terminal, a first clock signal terminal and a second clock signal terminal. The first shift register is configured to generate a first output signal based on the signal at the first clock signal terminal and generate a second output signal based on the signal at the second clock signal terminal; and a second shift register coupled to the input signal terminal and a third clock signal terminal, the second shift register is configured to generate a third output signal based on the signal at the third clock signal terminal; and a pull-up node of the first shift register is coupled to a pull-up node of the second shift register.

Abstract: A shift register unit, a gate drive circuit, and a drive method are provided. The shift register unit includes a first input circuit, a second input circuit, and an output circuit. The first input circuit is configured to charge a first node in response to a first input signal to control a level of the first node; the second input circuit is configured to charge a second node in response to a second input signal to control a level of the second node; and the output circuit is configured to output an output signal to an output terminal under common control of the level of the first node and the level of the second node.

Abstract: The present disclosure provides a shift register unit, including a detection signal input sub-circuit, a display signal input sub-circuit, an output circuit, a pull-down control circuit and a signal output terminal, the output circuit includes a pull-up sub-circuit and a pull-down sub-circuit, the pull-down control circuit includes a selection sub-circuit and a plurality of pull-down control sub-circuits. The present disclosure further provides a gate driving circuit, a display panel and a driving method for driving the display panel. The shift register unit has a simple structure and a long service life.

Abstract: Embodiments of the present disclosure provide a shift register. The shift register includes a blank input circuit, N shift register circuits, and a compensation selection circuit. The blank input circuit is configured to store a blank input signal, and provide a blank pull-down signal to N pull-down nodes based on the blank input signal and a blank control signal. The N shift register circuits are respectively coupled to the blank input circuit via the N pull-down nodes, and are configured to output respective blank output signals based on the blank pull-down signal and respective clock signals during a blank period. The compensation selection circuit is configured to provide the blank input signal to the blank input circuit under the control of a compensation selection control signal. Herein N is a natural number greater than 1.

Abstract: A shift register unit, a driving method, a gate driving circuit, and a display device are disclosed. The shift register unit includes: a shift circuit, used to output, to a first output end during a first time period, a power control signal, and output the power control signal to a second output end during a second time period; and a signal integrated circuit, used to output the power control signal to a third output end in response to the power control signal and a first output signal, output the power control signal to the third output end in response to the power control signal and a second output signal, and output, to the third output end at times other than the first and second time period in response to the power control signal, the first output signal and the second output signal, a first pull-down power signal.

Abstract: A pixel circuit includes a driving circuit, configured to drive a light-emitting element to emit light; a compensation control circuit, electrically connected to a first gate line and configured to control a control terminal of the driving circuit to be connected with a second terminal of the driving circuit under the control of a first gate drive signal provided by the first gate line; and a data writing circuit, electrically connected to a second gate line and configured to control a data voltage to be provided to a first terminal of the driving circuit under the control of a second gate drive signal provided by the second gate line. A voltage value of the first gate drive signal is substantially different from a voltage value of the second gate drive signal.

Abstract: A shift register includes: an input unit, configured to provide an input signal to a first node; a pull-up unit, configured to provide a voltage of a first supply voltage terminal to an output terminal; a pull-up control unit, configured to provide the voltage of the first supply voltage terminal or a voltage of a second supply voltage terminal to a second node; a pull-down unit, configured to provide a third clock signal from a third clock signal terminal to the output terminal; a pull-down control unit, configured to provide the voltage of the first supply voltage terminal to the first node; a first noise reduction unit, configured to reduce electrical leakage of the input unit to the first node; and a second noise reduction unit, configured to reduce electrical leakage of the pull-down control unit to the first node.