Abstract: A shift register circuit includes an input sub-circuit, an output sub-circuit and a control sub-circuit. The input sub-circuit is coupled to a first input signal terminal and a pull-up node, and configured to, under control of a first input signal, transmit the first input signal to the pull-up node. The output sub-circuit is at least coupled to the pull-up node, a first clock signal terminal and a first signal output terminal, and configured to transmit a first clock signal to the first signal output terminal under control of a voltage at the pull-up node. The control sub-circuit is coupled to at least one first reference node, at least one first control signal terminal and the pull-up node, and configured to transmit a voltage at a first reference node to the pull-up node under control of a first control signal.

Abstract: A diode having a simple structure and a simple manufacturing method of the diode are provided. A diode including: a semiconductor layer having a first region and a second region having a resistance lower than a resistance of the first region; a first insulating layer having a first aperture portion and a second aperture portion and covering the semiconductor layer other than the first aperture and the second aperture, the first aperture portion exposing the semiconductor layer in the first region, the second aperture portion exposing the semiconductor layer in the second region; a first conductive layer connected to the semiconductor layer in the first aperture portion and overlapping with the semiconductor layer in the first region via the first insulating layer in a planar view; and a second conductive layer connected to the semiconductor layer in the second aperture.

Abstract: A symmetric interleaver for a Convolutional Neural Network (CNN) and Recurrent Neural Network (RNN) encoder and a circular padding mode are disclosed. The interleaver interleaves elements of an input block to form an output block in which an output neighborhood of elements for each element of the output block is symmetric to an input neighborhood of elements for each element of the input block. A position of an element of the input block is interleaved based on an index i of the position times a parameter ? modulo K in which the parameter ? is relatively prime with K. A test loss function may be used to train the encoder that includes a Binary Cross Entropy (BCE) loss function plus a function that minimizes a number of codeword pairs based on a Euclidean distance. The RNN encoder may be implemented as part of a Turbo Autoencoder (TurboAE) encoder.

Abstract: A reversible superconducting circuit includes two Josephson transmission lines. Inductors connect Josephson Junctions in the array. Each transmission line passes a fluxon along the Junctions. The circuit includes an interface with first and second shunt capacitors coupled to the first and second transmission lines, and a third shunt capacitor, forming a connecting circuit with the first and second shunt capacitors. The shunt capacitors include Josephson junctions in parallel. The connecting circuit receives an input fluxon and transmits an output fluxon. The circuit also includes a Josephson Junction and inductor in parallel with the third shunt capacitor, forming a storage circuit. The storage circuit stores a SFQ. The output fluxon has polarity based on the SFQ stored when the first fluxon is received. The input fluxon causes the polarity of the stored SFQ to be the same as the polarity of the input fluxon, immediately after the input fluxon is received.

Abstract: The present application provides a display panel in which transistors in an input pull-up module, a stage transfer output module, and an output pull-up module are provided as P-type low temperature polysilicon thin film transistors, and a transistor in an output pull-down module is provided as an N-type metal oxide thin film transistor.

Abstract: Provided is a shift register unit. The shift register unit includes: a first input circuit, connected to a first control terminal, a turn-on signal terminal, a first node and a second node; a second input circuit, connected to a first power supply terminal, the first node and a third node; an output control circuit, connected to the first node, the second node, the third node, a second control terminal and a fourth node; and an output circuit, connected to the second node, the fourth node, the first power supply terminal, a second power supply terminal, a first output terminal and a second output terminal.

Abstract: The present application discloses a gate driving circuit and a display panel. The gate driving circuit comprises a plurality of cascaded gate driving modules. A first driving signal can be output through a first output node, and at the same time, a second driving signal with a same phase as the first driving signal can be output through a second output node, and a gate driving sub-module and an in-phase output sub-module share the first output node and a pull-down node, which simplifies a circuit topology of the gate driving circuit.

Abstract: A Gate Driver on Array (GOA) circuit and a display panel are provided. The GOA circuit includes a plurality of cascaded GOA units. An Nth stage GOA unit includes a pull-up control circuit, a pull-up output circuit and a scan direction control circuit. The scan direction control circuit can be controlled by the clock signal to realize the alternating forward and backward scanning. The output terminal of the scan direction control circuit is connected with the output terminal of the pull-up control circuit, and the output terminal potential of the pull-up control circuit can be alternately changed.

Abstract: This application provides a shift register, a gate drive circuit, a display panel, and an electronic device. The shift register includes a node control module, electrically connected to a first level signal receiving end, a second level signal receiving end, a first node, and a second node; an input module, electrically connected to a first clock signal end, a trigger signal input end, and the second node; an output module, electrically connected to the first level signal receiving end, the second level signal receiving end, the first node, a third node, and a drive signal output end; a first voltage stabilizing module, electrically connected to the first node, a fourth node, and the second level signal receiving end; and a second voltage stabilizing module, electrically connected to the second node, the third node, the fourth node, and a second clock signal end.

Abstract: A transistor whose channel region includes an oxide semiconductor is used as a pull down transistor. The band gap of the oxide semiconductor is 2.0 eV or more, preferably 2.5 eV or more, more preferably 3.0 eV or more. Thus, hot carrier degradation in the transistor can be suppressed. Accordingly, the circuit size of the semiconductor device including the pull down transistor can be made small. Further, a gate of a pull up transistor is made to be in a floating state by switching of on/off of the transistor whose channel region includes an oxide semiconductor. Note that when the oxide semiconductor is highly purified, the off-state current of the transistor can be 1 aA/?m (1×10?18 A/?m) or less. Therefore, the drive capability of the semiconductor device can be improved.

Abstract: Disclosed is a shift register, a gate driving circuit, a display apparatus and a driving method, the shift register including a first input sub-circuit, configured to receive a first input signal from a first input terminal and output an output blanking output control signal; a second input sub-circuit, configured to receive a second input signal from a second input terminal and output a display output control signal; a selection sub-circuit, having a first terminal connected to the second input sub-circuit, a second terminal connected to the first input sub-circuit, and a third terminal connected to a first node, configured to control a potential of the first node according to the display output control signal and the blanking output control signal; an output sub-circuit, configured to output a composite output signal via an output terminal under control of a first node.

Abstract: A scan driver for driving a plurality of pixels, the scan driver including: stages connected to each other through carry lines, a first stage among the stages includes: a first scan circuit configured to generate a first scan signal in response to a stage select signal, and apply the first scan signal to pixels of the same row among the plurality of pixels; and a second scan circuit electrically connected to the first scan circuit to generate a carry signal overlapping the first scan signal, and configured to provide a second scan signal to the pixels of the same row in response to the carry signal, and the carry signal is output as the stage select signal to a second stage among the stages through one of the carry lines.

Abstract: A display device according to one aspect of the present disclosure includes: a substrate including a display area and a non-display area enclosing the display area; a plurality of pixels disposed in the display area; and a gate driving unit disposed in the non-display area on both sides of the display area and including a plurality of stages. The plurality of stages includes a plurality of normal output stages and a plurality of dummy stages which does not output a signal. The plurality of dummy stages may be connected to a gate low voltage line.

Abstract: A shift register unit, a driving method thereof, and a gate driving circuit are disclosed. The shift register unit includes: an input circuit configured to receive an input signal from an input signal terminal and output the input signal to a voltage stabilizer node; a voltage-stabilizing circuit configured to input potential of the voltage stabilizer node to a pull-up node and control potential of the voltage stabilizer node; an output circuit configured to receive a clock signal from a clock signal terminal and provide an output signal to an output signal terminal based on the clock signal received under control of the potential of the pull-up node; and a control circuit configured to control potential of the output signal terminal under control of the potential of the pull-up node.

Abstract: A display device, a gate drive circuit, a shift register and a control method are disclosed. The shift register includes a first shift register unit and a second shift register unit, the first shift register unit is configured to write a first control signal to the first node, and write a first clock signal to the first signal output terminal under control of a voltage of the first node; the second shift register unit is configured to write a second clock signal to the second signal output terminal under control of the voltage of the first node; during time of a frame, the first clock signal and a first input signal provided by a first signal input terminal are pulse signals, and the second clock signal is a DC signal.

Abstract: Configurable variable-length shift register circuits include a group of flip-flops connected in a serial configuration. The plurality of flip-flops is connected to a serial data-in line and a clock line. Each flip-flop can include a data input, a clock input configured to receive a clock signal from the clock line, and a data output. The plurality of flip-flops can include a serial data-out line. The circuit includes a plurality of multiplexers connected to the plurality of flip-flops to enable a desired number of flip-flops for an application. A nonvolatile memory can be connected to the plurality of multiplexers and configured to receive a register-length indication, where the register-length indication corresponds to a selected number of flip-flops selected for enablement for a given application.

Abstract: Provided is a scan driver including a plurality of stages. Each stage includes a node controller in which a transistor having a gate connected to a first control node and a transistor having a gate connected to a second control node are coupled to each other. Accordingly, a stable scan signal is output without a separate boost capacitor.

Abstract: A detection device includes a plurality of detection elements arranged in a matrix having a row-column configuration in a detection area, a plurality of scan lines each coupled to the detection elements arranged in a first direction, a drive circuit configured to drive the scan lines, a plurality of output signal lines each coupled to the detection elements arranged in a second direction different from the first direction, and a detection circuit configured to be supplied with detection signals from the detection elements through the output signal lines.

Abstract: A semiconductor device or the like with a novel structure that can change the orientation of the display is provided. A semiconductor device or the like with a novel structure, in which a degradation in transistor characteristics can be suppressed, is provided. A semiconductor device or the like with a novel structure, in which operation speed can be increased, is provided. A semiconductor device or the like with a novel structure, in which a dielectric breakdown of a transistor can be suppressed, is provided. The semiconductor device or the like has a circuit configuration capable of switching between a first operation and a second operation by changing the potentials of wirings. By switching between these two operations, the scan direction is easily changed. The semiconductor device is configured to change the scan direction.

Abstract: A display device includes scan lines, pixels electrically connected to the scan lines, and a scan driver including stages for supplying scan signals through the scan lines to the pixels. The stages include a stage that includes the following elements: a first node setting unit for setting a voltage of a first node; a second node setting unit for setting a voltage of a second node based on the voltage of the first node; a third node setting unit for setting a voltage of a third node based on the voltage of the second node; and an output unit for outputting a scan signal based on the voltage of the third node. Each of the first and third node setting units includes an N-type transistor. The scan driver further includes a first charge pump for supplying a first bias voltage to a back-gate electrode of the N-type transistor.

Abstract: In a pulse output circuit in a shift register, a power source line which is connected to a transistor in an output portion connected to a pulse output circuit at the next stage is set to a low-potential drive voltage, and a power source line which is connected to a transistor in an output portion connected to a scan signal line is set to a variable potential drive voltage. The variable potential drive voltage is the low-potential drive voltage in a normal mode, and can be either a high-potential drive voltage or the low-potential drive voltage in a batch mode. In the batch mode, display scan signals can be output to a plurality of scan signal lines at the same timing in a batch.

Abstract: The present disclosure provides a shift register unit, a driving method, a driving circuit and a display device. The shift register unit includes a first node potential adjustment circuit, a first tank circuit, a second node control circuit, a second tank circuit, a third node control circuit, a first node control circuit, and an output circuit; the first node potential adjustment circuit changes the potential of the first node according to the adjustment clock signal under the control of the potential of the first node; the first tank circuit is used to maintain the potential of the first node; the third node control circuit controls the potential of the third isolation node and the potential of the fourth node; the second node control circuit controls the potential of the second isolation node.

Abstract: A backlight module includes at least one drive light-emitting group. The drive light-emitting group includes a drive unit provided with plurality of signal transmission channels, a plurality of light-emitting units and a plurality of line groups. The signal transmission channel is connected to the light-emitting unit through the line group. The signal transmission channel, the line group and the light-emitting unit are arranged in one-to-one correspondence. The line group includes a main transmission line and a compensation line arranged in parallel. The compensation lines of the plurality of line groups are connected through a control switch group. When there is an abnormal signal transmission channel, the control switch group is enabled to control a compensation line corresponding to the abnormal signal transmission channel to be conducted with compensation line corresponding to at least one normal signal transmission channel.

Abstract: A display device includes a display panel including pixels in a display area, scan lines disposed in the display area and electrically connected to the pixels, a gate driving circuit disposed in the display area and electrically connected to the scan lines, and clock lines disposed in the display area and electrically connected to the gate driving circuit. The gate driving circuit includes stage blocks adjacent to each other and outputting a scan signal in response to a clock signal provided through a corresponding clock line among the clock lines, and a scan signal output from a stage block among the stage blocks is supplied to scan lines of another stage block among the stage blocks.

Abstract: A matrix-array detector having: an array of pixels arranged in a matrix along rows and down columns, each pixel for generating a signal according to a physical effect; a signal generator for generating two clock signals that are phase-shifted relative to one another; and a row-addressing device including a shift register, the shift register including a plurality of stages arranged in a cascade, each stage for receiving, in alternation from one stage to another, one clock signal from the two clock signals, and delivering an intermediate output signal that takes a high value and a low value allowing the pixels of the row to be activated and to be deactivated, respectively. The signal generator is also for generating a third clock signal.

Abstract: The present disclosure provides a shift register unit, including a detection signal input sub-circuit, a display signal input sub-circuit, an output circuit, a pull-down control circuit and a signal output terminal, the output circuit includes a pull-up sub-circuit and a pull-down sub-circuit, the pull-down control circuit includes a selection sub-circuit and a plurality of pull-down control sub-circuits. The present disclosure further provides a gate driving circuit, a display panel and a driving method for driving the display panel. The shift register unit has a simple structure and a long service life.

Abstract: To suppress malfunctions in a shift register circuit. A shift register having a plurality of flip-flop circuits is provided. The flip-flop circuit includes a transistor 11, a transistor 12, a transistor 13, a transistor 14, and a transistor 15. When the transistor 13 or the transistor 14 is turned on in a non-selection period, the potential of a node A is set, so that the node A is prevented from entering into a floating state.

Abstract: The present disclosure provides a gate driving circuit, a method of driving a gate driving circuit, and a display panel. The gate driving circuit includes a plurality of driving units connected in cascade. Each driving unit includes: N shift register units; and a mode control circuit connected to the N shift register units, wherein the mode control circuit is configured to receive a control signal for the driving unit, and connect the N shift register units in one of a plurality of resolution modes under the control of the control signal.

Abstract: A gate driver includes a first shift register to supply a gate signal to a plurality of gate lines through output nodes, and a second shift register to supply the gate signal to the gate lines through output nodes. The gate signal is supplied from the first shift register to one side of an i-th gate line and supplied from the second shift register to the other side of the i-th gate line, then the gate signal is supplied from the second shift register to the other side of the i-th gate line, then the gate signal is supplied from the first shift register to one side of the i-th gate line, and then, the gate signal is supplied from the first shift register to one side of the i-th gate line and simultaneously supplied from the second shift register to the other side of the i-th gate line.

Abstract: A semiconductor device or the like with a novel structure that can change the orientation of the display is provided. A semiconductor device or the like with a novel structure, in which a degradation in transistor characteristics can be suppressed, is provided. A semiconductor device or the like with a novel structure, in which operation speed can be increased, is provided. A semiconductor device or the like with a novel structure, in which a dielectric breakdown of a transistor can be suppressed, is provided. The semiconductor device or the like has a circuit configuration capable of switching between a first operation and a second operation by changing the potentials of wirings. By switching between these two operations, the scan direction is easily changed. The semiconductor device is configured to change the scan direction.

Abstract: A reversible superconducting circuit includes two Josephson transmission lines. Inductors connect Josephson Junctions in the array. Each transmission line passes a fluxon along the Junctions. The circuit includes an interface with first and second shunt capacitors coupled to the first and second transmission lines, and a third shunt capacitor, forming a connecting circuit with the first and second shunt capacitors. The shunt capacitors include Josephson junctions in parallel. The connecting circuit receives an input fluxon and transmits an output fluxon. The circuit also includes a Josephson Junction and inductor in parallel with the third shunt capacitor, forming a storage circuit. The storage circuit stores a SFQ. The output fluxon has polarity based on the SFQ stored when the first fluxon is received. The input fluxon causes the polarity of the stored SFQ to be the same as the polarity of the input fluxon, immediately after the input fluxon is received.

Abstract: A semiconductor device or the like with a novel structure that can change the orientation of the display is provided. A semiconductor device or the like with a novel structure, in which a degradation in transistor characteristics can be suppressed, is provided. A semiconductor device or the like with a novel structure, in which operation speed can be increased, is provided. A semiconductor device or the like with a novel structure, in which a dielectric breakdown of a transistor can be suppressed, is provided. The semiconductor device or the like has a circuit configuration capable of switching between a first operation and a second operation by changing the potentials of wirings. By switching between these two operations, the scan direction is easily changed. The semiconductor device is configured to change the scan direction.

Abstract: Proposed is a gate driver and a display device having the same. The gate driver includes a plurality of stage circuits, wherein each of the plurality of stage circuits includes a shift register configured to control charging and discharging of a Q node and a QB node, and a plurality of output buffers sequentially connected to the shift register, wherein each of the output buffers includes a first transistor configured to transmit a voltage of the Q node to a Q? node, a pull-up transistor configured to output a clock signal to a gate line in response to a voltage of the Q? node, and a pull-down transistor configured to output a low-potential voltage to the gate line in response to a voltage of the QB node.

Abstract: There is provided a gate driving circuit including cascaded Gate Driver On Array (GOA) units, each GOA unit drives a row of pixels and includes a starting sub-unit, an output sub-unit and an output terminal, in the GOA unit at a first stage, the starting sub-unit is coupled with a starting signal, a first control signal, a second control signal and a constant voltage potential, and the output sub-unit is coupled with a first clock signal and a first power supply signal; in the GOA unit at an nth stage, the starting sub-unit is coupled with the starting signal, the first control signal, the second control signal and the output terminal of the GOA unit at an (n?1)th stage, the output sub-unit is coupled with the first power supply signal and the output terminal of the GOA unit at an (n+1)th stage, n is an integer greater than 1.

Abstract: A unit circuit constituting each stage of a shift register serving as a gate driver of a display device charges an internal node to an H level via a transistor T2 when an output signal G(n?4) of a preceding stage turns to the H level and sets the internal node to an L level via a transistor T3 when an output signal G(n+8) of a succeeding stage turns to the H level. Each of the unit circuits of last eight stages in the gate driver is provided with a transistor T4 including a gate terminal to which the signal G(n?4) is applied and a drain terminal connected to the internal node. A signal is applied to a source terminal of the transistor T4, the signal being at the H level during a period when the internal node of any of the last eight stages is to be set to the H level, and being the L level during the other periods. This suppresses a voltage fluctuation generated in the internal node when a stabilization circuit does not normally function.

Abstract: A display panel includes a scan driving circuit, signal pins and a first gating circuit. Signal pins include a detection signal pin and an enable signal pin. The scan driving circuit includes scan drive units disposed in a cascade manner. The first gating circuit includes a first switch unit and a second switch unit. An input terminal of the first switch unit is electrically connected to a scan signal detection terminal of an Nth-stage scan drive unit. An input terminal of the second switch unit is electrically connected to a scan signal detection terminal of a first-stage scan drive unit. An output terminal of the first switch unit and an output terminal of the second switch unit are both electrically connected to the detection signal pin. The first switch unit is configured to turn on in a forward scan detection stage and turn off in a backward scan detection stage. The second switch unit is configured to turn on in the backward scan detection stage and turn off in the backward scan detection stage.

Abstract: A gate driving circuit and a display device including the same are discussed. A signal transmitter of the gate driving circuit can include a first charge controller configured to charge a first control node in response to a voltage of a VST node, a second charge controller configured to charge a second control node using a first transistor that is turned on in response to an (N+1)th clock generated following an Nth clock, a first discharge controller configured to discharge the first control node in a charging period of the second control node, and a second discharge controller configured to discharge the second control node when the voltage of the VST node is a high voltage or in a charging period of the first control node.

Abstract: A semiconductor device including a biometric recognition function and a touch sensor or near touch sensor function is provided. The semiconductor device includes a light-emitting device and an imaging device. The imaging device includes a gate driver circuit and m rows of pixels (m is an integer more than or equal to 2). The gate driver circuit includes a plurality of first register circuits and second register circuits whose number is less than that of the first register circuits. The first register circuits are connected with each other in series and the second register circuits are connected with each other in series. The gate driver circuit has a function of operating in the first mode and the second mode. In the first mode, the first register circuits are in the on state and the second register circuits are in the off state, and in the second mode, the second register circuits are in the on state and the first register circuits are in the off state.

Abstract: A driving method, a driving circuitry and a display device are provided. The driving method is applied to a touch display panel. A shift register unit in a gate driving circuitry in the touch display panel is electrically coupled with a clock signal terminal, the clock signal terminal is used for providing a clock signal to a pull-up circuit in the shift register unit, and a display cycle includes a display time period and a touch time period. The driving method includes: within a period during which initial N rows of gate lines are turned on after entering the display time period from the touch time period in the display cycle, controlling and adjusting the clock signal to increase a falling speed of a potential of a gate drive signal outputted by the shift register unit; N is a positive integer. The phenomenon of poor horizontal stripes is improved.

Abstract: A display apparatus with low power consumption is provided. The display apparatus includes a circuit for boosting a signal voltage output from a gate driver. The signal voltage from the gate driver can be boosted and then supplied to a pixel, which is suitable for driving a display device with a high threshold voltage. Furthermore, by utilizing a boosting function, output of the gate driver can be reduced, and power consumption can also be reduced. By combination with a pixel having a boosting function of image data, a display apparatus with lower power consumption can be achieved.

Abstract: Provided are a display panel, a method for the same and a display device. In the display panel, in a same shift register unit of a shift register circuit, a pull-down module is electrically connected to a first node, a second node, a first level signal terminal, and a signal output terminal separately. The pull-down module transmits a first level signal of the first level signal terminal to the second node and the signal output terminal under the control of a potential of the first node. The pull-down module includes at least a first transistor. A gate of the first transistor is electrically connected to the first node; the pull-down control module is electrically connected to the first node and the scanning control terminal separately; and the pull-down control module controls a scanning control signal of the scanning control terminal to be transmitted to the first node.

Abstract: A display device includes: a substrate including first and second display regions and first and second non-display regions; a plurality of first pixels in the first display region; a plurality of second pixels in the second display region; a plurality of first scan stage circuits in the first non-display region, the first scan stage circuits configured to provide a scan signal to the first pixels; a plurality of second scan stage circuits in the second non-display region, the second scan stage circuits configured to provide a scan signal to the second pixels; a plurality of dummy scan stage circuits in the second non-display region, the dummy scan stage circuits being between the second scan stage circuits; and a scan bridge line in the second non-display region, the scan bridge line connecting one second scan stage circuit among the second scan stage circuits and a dummy scan stage circuit adjacent thereto.

Abstract: A shift register unit, a gate drive circuit, and a drive method are provided. The shift register unit includes a first input circuit, a second input circuit, and an output circuit. The first input circuit is configured to charge a first node in response to a first input signal to control a level of the first node; the second input circuit is configured to charge a second node in response to a second input signal to control a level of the second node; and the output circuit is configured to output an output signal to an output terminal under common control of the level of the first node and the level of the second node; the first input circuit includes a first transistor and a first capacitor, and a second electrode of the first capacitor is connected to the first electrode of the first transistor.

Abstract: Disclosed are an array substrate row drive circuit unit, a drive circuit and a liquid crystal display panel thereof. The array substrate row drive circuit unit includes a pull-up control module; a pull-up module; a pull-down module connected to the pull-up control module and the pull-up module and being configured to simultaneously pull down a pull-up control signal and a row scan signal of a current stage array substrate row drive circuit unit to a low level according to a direct current low voltage signal when receiving the row scan signal; and a voltage dividing module electrically connected to the pull-up module and being configured to increase a falling edge during pull-down when the pull-down module simultaneously pulls down the pull-up control signal and the row scan signal of the current stage array substrate row drive circuit unit to a low level.

Abstract: A semiconductor device which shifts a low-level signal is provided. In an example, a first transistor including a first terminal electrically connected to a first wiring and a second terminal electrically connected to a second wiring, a second transistor including a first terminal electrically connected to a third wiring and a second terminal electrically connected to the second wiring, a third transistor including a first terminal electrically connected to a fourth wiring and a second terminal electrically connected to a gate of the second transistor, a fourth transistor including a first terminal electrically connected to a fifth wiring, a second terminal electrically connected to a gate of the third transistor, and a gate electrically connected to a sixth wiring, and a first switch including a first terminal electrically connected to the third wiring and a second terminal electrically connected to a gate of the first transistor are included.

Abstract: A gate driving unit, a gate driving circuit, a gate driving method, and a display device are provided. The gate driving unit includes a first output circuit and a second output circuit; the second output circuit comprises a first output sub-circuit; the first output circuit is respectively electrically connected to the first node, the second node and the first gate driving signal output end and is configured to control the first gate driving signal output end to output a first gate driving signal under the control of the potential of the first node and the potential of the second node; the first output sub-circuit is respectively electrically connected to the first node, the second gate driving signal output end and the first clock signal end, and is configured to control the second gate driving signal output end to be connected to the first clock signal end.

Abstract: The present disclosure discloses a shift register, a gate driving circuit and a display device. The shift register includes a display pre-charge reset circuit, a sensing cascade circuit, a sensing pre-charge reset circuit, a pull-down control circuit and an output circuit, where the display pre-charge reset circuit, the sensing cascade circuit and the sensing pre-charge reset circuit share the same pull-down control circuit and the same output circuit, the output circuit is coupled to at least one signal output terminal, the output circuit includes output sub-circuits in one-to-one correspondence with the at least one signal output terminal, and each output sub-circuit is configured to write a driving clock signal into the corresponding signal output terminal in a display output stage and a sensing output stage in response to a control of a voltage of a pull-up node in an effective level state.

Abstract: The present disclosure provides a phase shifting device, a driving method thereof, and an antenna. The phase shifting device of the present disclosure includes: data lines, scan lines and phase shifting units. Each phase shifting unit includes: a switch sub-circuit and a phase shifter. Control terminals of the switch sub-circuits in a same row are coupled to a same scan line, first terminals of the switch sub-circuits in a same column are coupled to a same data line, and a second terminal of each switch sub-circuit is coupled to a phase shifter included in the phase shifting unit to which the switch sub-circuit belongs. Each switch sub-circuit is configured to transmit, in response to a switch control signal provided by the scan line, a data voltage signal provided by the data line to the phase shifter to drive the phase shifter.

Abstract: A shift register includes: an input unit, configured to provide an input signal to a first node; a pull-up unit, configured to provide a voltage of a first supply voltage terminal to an output terminal; a pull-up control unit, configured to provide the voltage of the first supply voltage terminal or a voltage of a second supply voltage terminal to a second node; a pull-down unit, configured to provide a third clock signal from a third clock signal terminal to the output terminal; a pull-down control unit, configured to provide the voltage of the first supply voltage terminal to the first node; a first noise reduction unit, configured to reduce electrical leakage of the input unit to the first node; and a second noise reduction unit, configured to reduce electrical leakage of the pull-down control unit to the first node.

Abstract: A shift register is provided, which includes a blanking input circuit, a blanking control circuit, a blanking pull-down circuit, and a shift register circuit, and a twenty-ninth transistor. The blanking input circuit may provide a blanking input signal to a first control node according to a second clock signal. and comprise a first transistor The blanking control circuit may provide a first clock signal to a second control node and maintain a voltage difference between the first control node and the second control node, according to a voltage of the first control node. comprise a second transistor. The blanking pull-down circuit may provide a voltage of the second control node to a pull-down node according to the a first clock signal and comprise a third transistor and a third leakage-preventative transistor. The shift register circuit may provide a shift signal via a shift signal output terminal and a first drive signal via a first drive signal output terminal according to a voltage of the pull-down node.