Abstract: A shift register circuit includes plural shift register stages for providing plural gate signals. Each shift register stage includes a driving unit, an input unit, a driving adjustment unit and a pull-down unit. The driving unit is utilized for outputting a gate signal according to a system clock and a driving control voltage. The input unit is put in use for outputting the driving control voltage according to an input control signal and a first input signal. The driving adjustment unit is employed for adjusting the driving control voltage according to a second input signal and a third input signal. The pull-down unit is used for pulling down the gate signal and the driving control voltage according to a fourth input signal.

Abstract: A method of machine control can include providing at least a system master signal, selectively synchronizing at least sub-system master signal to the system master signal based on the value of the system master signal, and carrying out at least one operation based on the value of the other master signal. For example, a machine controller may provide a system virtual master signal and synchronize one or more module virtual master signals to the system virtual master based on the system virtual master count value. One or more components of the module may operate based on the count value of the module virtual master signal. The use of an asynchronous control method may advantageously increase the flexibility of the machine. Because the operation of the components of the machine may depend on respective virtual master signals, a machine using asynchronous control methods may advantageously continue operating one component or module in the event of a fault involving other components.

Abstract: System and method for a four-slot asynchronous communication mechanism with increased throughput. The system may include a host system and a client device. The host may comprise a data structure with four (two pairs of) slots and first information indicating a status of read operations from the data structure by the host. The client may read the first information from the host. The client may read second information from a local memory. The second information may indicate a status of write operations to the data structure by the client. The client may determine a slot of the data structure to be written. The slot may be determined based on the first information and the second information and may be the slot which has not been written to more recently of the pair of slots which has not been read from most recently. The client may increment a value of a counter. The value of the counter may be useable to indicate which slot has been written to most recently.

Abstract: An asynchronous logic family of circuits which communicate on delay-insensitive flow-controlled channels with 4-phase handshakes and 1 of N encoding, compute output data directly from input data using domino logic, and use the state-holding ability of the domino logic to implement pipelining without additional latches.

Abstract: A column repair circuit uses a system of circuits that automatically stops the shifting of register contents independently of the number of bits to be shifted. The circuit is only dependent on the number of bits in a column address repair block. By adding shift register positions to one end of each shift register chain, a dedicated block of bits is used to detect the end of the shift chain without explicitly knowing the length of the chain. The shift register positions provide a hard-programmed code that can be used to stop the shifting of data automatically. The shift register positions also provide a space for hard-programmed code bits that can be examined to determine when the shift process ends. A shift chain can be controlled with a controller so long as the information is organized into groups of ‘k’ bits. The controller only requires information regarding the value of the number ‘k’ and the pre-programmed stop code in order to control any number of bits in a shift chain.

Abstract: A FIFO-register (10) according to the invention comprises a sequence of register cells (10.1, . . . ,10.m), which register cells have a data section (40) and a status section (30). Data (Din) provided at an input (20) is shifted via the data sections (40) in the register cells to an output (50). The status section (30) of each cell indicates whether the data section (40) of that cell contains valid data. The status section of a cell comprises a control unit (37) coupled to a status input (32), to a status output (33) and to a clock input (31), and generates an output clock signal (Cli), which controls charge controlling elements (35, 36) coupled to the status input and the status output and controls the data section (40). The status output (33) of a status section (30) and the status input (32?) of its successor (30?) share a common capacitive node (33).

Abstract: When a PWM signal is generated by PWM generators which are provided for the number of channels, each PWM generator outputs the PWM start schedule data showing the timing of startup of the PWM signal to the CPU. When the number of PWM signals which start at substantially the same time exceeds a predetermined number on the basis of the PWM start schedule data, the CPU outputs delay setting data with respect to a channel corresponding to a portion exceeding the predetermined number to the PWM generator as the one showing that the generation of the PWM signal is to be delayed. The PWM generator delays the PWM signal, when the delay setting data shows a delay. As a result, a multi-channel pulse width modulation apparatus which can prevent a decrease in the operational reliability due to simultaneous start of the pulse width modulation signals can be provided.

Abstract: A register is disclosed in which an applied data signal D or its complement D is used to set or reset an output RS flip-flop under control of an applied load control signal L. The load control signal is applied to a switching circuit which controls application of the data signal D or D to the set or reset input of the output flip-flop such that the data signal is only applied for a time period sufficient to cause a change in state of the output flip-flop.

Abstract: A metastable prevent circuit comprises a plurality of parallel channels, each coupled to receive and synchronize asynchronous pulses to a synchronous clock signal. A shift register is responsive to the asynchronous pulses to sequentially enable individual ones of the channels. In the case of a two-channel system, the shift register is a bistable device which enables the channels alternately.

Abstract: An asynchronous FIFO incorporates a series of interconnected cells alternately oppositely inverted to provide forward and retrograde data paths, so as to selectively establish virtual flip flops as needed at interfaces between cells. Each cell combines an inverting amplifier for data, switch structure and a binary control for the switch structure to provide the data path. The controls are interconnected in a sequence along with logic to set the state of each control according to an instruction: copy the state of your predecessor in the sequence if the states of your predecessor and successor differ, otherwise hold your present state.

Abstract: The invention relates to a device for the acquisition and the processing of N asynchronous and periodic signals, such as velocity signals, N being preferably between 1 and 8, including a set of N synchronization flip-flops (B1) followed by a set of N storage flip-flops (B2) whose output is applied to a dedicated circuit via an N-input AND gate type assembly, the N synchronization flip-flops being sample by a flip-flop system (B4) from the clock of the dedicated circuit and the N automatic flip-flops (B1) being reset from said clock by an automatic flip-flop (B3).

Abstract: A FIFO status circuit suitable to detect the full or empty status of a RAM based FIFO which is asynchronously addressable by write and read access signals. The circuit detects whether the preceding addressing of the FIFO was a read or a write operation to determine whether the FIFO is empty or full. In one form, the trailing edges of the FIFO write and read signals trigger respective pulse generators. Short duration matched pulses drive the corresponding set and reset inputs of a flip-flop. The out Q and Q outputs from the flip-flop are coupled individually to a pair of AND gates. Each AND gate is also driven by a FIFO equal signal, a signal which indicates that both the read pointer and write pointer of the FIFO memory are directed to the same address. Because the FIFO equal signal is stable before the pulses reach the flip-flop, it serves to mask metastable conditions which may arise in the flip-flop.

Abstract: A queue form of asynchronous register is disclosed with signal paths commonly carrying elements of both data and control. Binaries are intercoupled in two sequences and are individually cross coupled to register "one" bits in one sequence and "zero" bits in the other. Bits are manifest by signal level changes. Individual binaries are driven by logic to accomplish an operational rule based on the states of neighboring binaries in both sequences. Each binary in each sequence is controlled by the states of the predecessor and successor in its sequence and the predecessor and successor of its associated binary in the other sequence. Specifically, if predecessor and successor binaries in a sequence are in different states, and predecessor and successor binaries of an associated binary in the other sequence are in the same state, the state of the predecessor is to be taken.

Abstract: A FIFO shift register (100) includes a parallel data in-port (PIN) to each of its cells (101-132) and a means for managing input to determine for each cell whether it is to receive data and, if so, whether through its conventional serial in-port (SIN) or through its parallel in-port. The input manager comprises a bidirectional shift register of input manager cells arranged in one-to-one correspondence with data cells. A one-bit validity indicator stored within a given input manager cell is logically combined with asserted PUSH and PULL signals to determine the source of data for the associated data cell and its immediate successor. This arrangement not only provides greater speed by minimizing bubble-through time, but permits the FIFO shift register to be clocked. This capacity for synchronous operation permits ready VLSI implementation with concomitant advantages in economy, reliability and speed.

Abstract: A shift register which, including a plurality of cells each comprising a data latch section and a shift control section, operates without external clocks, wherein the shift control section includes a terminal for receiving a shift start control signal; a terminal for receiving a shift inhibition control signal; a shift allowance control circuit which receives signals indicating as to whether each of the particular cell and the cells adjacent thereto is in a shift operation and signals indicating as to whether each of the adjacent cells is in a state which allows the shift of the particular cell, and generates a shift allowance signal to be given to the particular cell and the adjacent cells on the basis of the states of these cells and the shift inhibition control signal; a shift control circuit which receives the shift start control signal, the output of the shift allowance control circuit, the state signals of the particular cell and the adjacent cell, and makes the data latch section to conduct a shift ope

Abstract: An interface unit for connecting a transmitting unit to a receiving unit, the transmitting being capable of transmitting data at a speed greater than the processing speed of the receiving unit. The interface includes a serially connected multistage register which receives input data from the transmitting unit at its input stage and reads out data stored in its output stage to the receiving unit. It also includes a control circuit and a counter storing a count corresponding to the quantity of data stored in the register, the counter being incremented by one each time data is added to the register and decremented by one each time data is read from the register output stage. The control circuit is composed of a decoder and write control circuit. The decoder provides a signal to the write control circuit indicative of the count in the counter. When a datum is to be received from the transmitting unit, it signals the interface through a gate circuit, this signal incrementing the memory.

Abstract: A scannable asynchronous/synchronous CMOS latch circuit that includes a first, second, and third latch element, an asynchronous latch section, and a clock control section. When operated as a synchronous latch, the first latch element operates as the "master" portion and the second latch element acts as the "slave" portion of a master/slave latch. The clock control circuit enables the clock signals to control the synchronous operation of the master/slave latch. When operated as an asynchronous latch, the clock control circuit disables the clock. The output of the asynchronous latch section is connected to the input of the first latch element. An asynchronous signal appearing on one of the inputs of the asynchronous latch section passes through the first and second latch elements and is applied to another input of the asynchronous latch section, causing it to be latched, or held. Separate outputs are provided for the asynchronous latch and the synchronous latch.

Abstract: A register circuit which is used to asynchronously monitor any data or logical function (or functions) and be able to retain the status of the monitoring until the register is interrogated whereupon the register is automatically reset and able to receive or monitor another status signal.