Multirank (i.e., Rows Of Storage Units Form A Shift Register) Patents (Class 377/67)
  • Patent number: 10276120
    Abstract: The present application discloses a pull down maintaining circuit, comprising: a first switch transistor, an input terminal is connected to a first direct current power source, and an output terminal outputting a scanning signal of the Nth level scanning line; a second switch transistor, an input terminal is connected to the first direct current power source, and an output terminal outputting a scanning electric level signal of the Nth level scanning line; a control unit for controlling the first and the second switch transistors to turn off in accordance with a low voltage outputted from the first and the second direct current power source, and the third direct current power source, and to control the first and the second switch transistors to normally turn on in accordance with a high voltage is outputted from the first and the second direct current power source, and the third direct current power source.
    Type: Grant
    Filed: January 16, 2017
    Date of Patent: April 30, 2019
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventors: Longqiang Shi, Shu-Jhih Chen
  • Patent number: 10263615
    Abstract: Methods and circuitry for driving a device through drive cycles wherein each drive cycle has a plurality of drive stages are disclosed. An example of the circuitry includes an output for coupling the circuitry to the device and a plurality of drive slices coupled in parallel to the output. Control circuitry selectively activates individual drive slices in the plurality of drive slices during each stage of a drive cycle.
    Type: Grant
    Filed: August 24, 2016
    Date of Patent: April 16, 2019
    Assignee: Texas Instruments Incorporated
    Inventors: Olivier Trescases, Johan Tjeerd Strydom, Rajarshi Mukhopadhyay
  • Patent number: 9880810
    Abstract: A single block shifter design performing arithmetic and logical shift operations on input operands of multiple types is disclosed. The shifter design may be configurable and automatically generated to support multiple partition types including at least one of 80-bit, 40-bit, and 20-bit partition type. The shifter may also be configured and automatically generated to perform rotate operations on input operands. The shifter may include two stages where the first stage includes multiple multiplexers performing shift or rotate operations by one or more shift or rotate amounts without saturation, and the second stage includes multiple multiplexers performing operations with saturation. The shifter includes an inversion block to process signed and unsigned input data. A method of automatically generating the shifter design with an electronic design tool is also disclosed.
    Type: Grant
    Filed: October 1, 2014
    Date of Patent: January 30, 2018
    Assignee: Cadence Design Systems, Inc.
    Inventors: David L. Heine, Aamir A. Farooqui
  • Patent number: 9495920
    Abstract: A shift register unit, a gate driving apparatus and a display device are configured to solve the problem that a bi-directional scan function can not be realized in the prior art.
    Type: Grant
    Filed: May 14, 2013
    Date of Patent: November 15, 2016
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Fei Yang
  • Patent number: 9299308
    Abstract: A display device includes a first-stage output circuit adapted to perform output to a first-stage output signal line as an endmost output signal line out of a plurality of output signal lines disposed in parallel to each other, and the first-stage output circuit includes a start signal line to which a start signal for applying a conducting potential sequentially to the plurality of output signal lines is applied, a first clock signal line to which a first clock signal is applied, a second clock signal line to which a second clock signal is applied, a first transistor having a source to which the first-stage output signal line is connected, and a drain to which the first clock signal line is connected, and a second transistor having a gate to which the start signal line is connected.
    Type: Grant
    Filed: February 5, 2015
    Date of Patent: March 29, 2016
    Assignee: Japan Display Inc.
    Inventors: Hiroyuki Abe, Masahiro Maki, Takayuki Suzuki
  • Patent number: 9257198
    Abstract: To provide a shift register unit, which comprises a positive control signal input terminal, a reverse control signal input terminal, a first thin film transistor, a second thin film transistor, a positive input terminal, a reverse input terminal, a pull-up module and a first reset module, a gate of the first thin film transistor is connected with the positive input terminal, a first electrode of the first thin film transistor is connected with the positive control signal input terminal, a second electrode of the first thin film transistor is connected with a pull-up node of the pull-up module, a gate of the second thin film transistor is connected with the reverse input terminal, a first electrode of the second thin film transistor is connected with the pull-up node of the pull-up module, a second electrode of the second thin film transistor is connected with the reverse control signal input terminal.
    Type: Grant
    Filed: November 20, 2014
    Date of Patent: February 9, 2016
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Yan Yan
  • Patent number: 9100014
    Abstract: Provided is a nonvolatile storage gate embedded logic circuit embedding a nonvolatile storage gate which can hold data after power supply cutoff and can cut off a power supply at the same time shifting into a standby state. The nonvolatile storage gate embedded logic circuit includes a logic calculation unit having a logic gate, and a nonvolatile storage gate having a nonvolatile storage element, a data interface control unit disposed so as to be adjoining to the nonvolatile storage element, and receiving a nonvolatile storage control signal for data read-out from the nonvolatile storage element and data write-in to the nonvolatile storage element, and a volatile storage element disposed so as to be adjoining to the nonvolatile storage element, receiving a data input signal and a clock signal, and outputting a data output signal.
    Type: Grant
    Filed: January 8, 2009
    Date of Patent: August 4, 2015
    Assignee: Rohm Co., Ltd.
    Inventors: Hiromitsu Kimura, Takaaki Fuchikami, Yoshikazu Fujimori
  • Patent number: 9007291
    Abstract: An active level shift (ALS) driver circuit and a liquid crystal display apparatus including the ALS driver circuit are disclosed. The ALS driver circuit includes an input unit configured to apply a first polarity voltage to a first node and to apply a second polarity voltage to a second node, a level compensation unit configured to adjust the voltages of the first node and the second node, and an output unit configured to alternately output a first power voltage and a second power voltage according to the adjusted voltages of the first and second nodes.
    Type: Grant
    Filed: October 20, 2011
    Date of Patent: April 14, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: Seung-Kyu Lee, Dong-Hoon Lee, Chul-Ho Kim, Kyung-Hoon Kim, Se-Hyang Kim
  • Patent number: 8982114
    Abstract: A display device includes a first-stage output circuit adapted to perform output to a first-stage output signal line as an endmost output signal line out of a plurality of output signal lines disposed in parallel to each other, and the first-stage output circuit includes a start signal line to which a start signal for applying a conducting potential sequentially to the plurality of output signal lines is applied, a first clock signal line to which a first clock signal is applied, a second clock signal line to which a second clock signal is applied, a first transistor having a source to which the first-stage output signal line is connected, and a drain to which the first clock signal line is connected, and a second transistor having a gate to which the start signal line is connected.
    Type: Grant
    Filed: October 5, 2012
    Date of Patent: March 17, 2015
    Assignee: Japan Display Inc.
    Inventors: Hiroyuki Abe, Masahiro Maki, Takayuki Suzuki
  • Publication number: 20150030116
    Abstract: A shift register is configured so that each of first and second intermediate stages includes (i) a first input terminal supplied with a clock signal, (ii) a second input terminal supplied with a clock signal different in phase from the clock signal supplied to the first input terminal, (iii) an output terminal connected to the first input terminal via an output transistor, and (iv) a setting circuit, which is connected to the second input terminal and the output transistor, for setting an electric potential of a control terminal of the output transistor, the second intermediate stage includes a control circuit which is (i) connected to the setting circuit of the second intermediate stage and (ii) supplied with a control signal, an operation period (i) starts at a time when a shift start signal supplied to an initial stage is activated and (ii) ends at a time when an output of a final stage changes from activation to inactivation, and when the clock signal supplied to the first input terminal of the second int
    Type: Application
    Filed: March 5, 2013
    Publication date: January 29, 2015
    Inventors: Satoshi Horiuchi, Shinya Tanaka, Akira Tagawa, Yasuaki Iwase, Takayuki Mizunaga, Akihisa Iwamoto
  • Publication number: 20140355733
    Abstract: A stage circuit and a scan driver, the stage circuit including a switch unit configured to selectively electrically couple a first node to one of a first input terminal and a second input terminal, a first driver coupled to the first node, to a second node, to a third node, to a first clock terminal, and to a second clock terminal, and a second driver coupled to the second node, to the third node, to a third clock terminal, and to a common terminal, and configured to output a scan signal to an output terminal.
    Type: Application
    Filed: May 13, 2014
    Publication date: December 4, 2014
    Inventors: Yong-Jae Kim, Dong-Gyu Kim, Sung-Jae Moon
  • Patent number: 8878765
    Abstract: A gate shift register and a display device using the same are disclosed. The gate shift register includes a plurality of stages that receive a plurality of gate shift clocks and sequentially output a scan pulse. A k-th stage of the plurality of stages includes a scan direction controller for converting a shift direction of the scan pulse in response to carry signals of previous stages input through first and second input terminals and carry signals of next stages input through third and fourth input terminals, a node controller for controlling charging and discharge operations of each of Q1, Q2, QB1, and QB2 nodes, a floating prevention unit for applying a low potential voltage to a gate electrode of a discharge TFT based on a voltage of the QB1 node or the QB2 node, and an output unit for outputting first and second scan pulses.
    Type: Grant
    Filed: October 27, 2010
    Date of Patent: November 4, 2014
    Assignee: LG Display Co., Ltd.
    Inventors: Hongjae Shin, Byunghyun Park, Miyoung Son
  • Publication number: 20140270050
    Abstract: An automated method is provided for designing an integrated circuit. A net list of an integrated circuit design is generated, wherein the net list includes a scan chain having a sequence of individual scan cells. A sequence of two or more individual scan cells of the scan chain is identified as a candidate for replacement by a custom shift array macro cell. The identified sequence of two or more individual scan cells is then replaced with a custom shift array macro cell that provides a functionally equivalent shift function as the replaced sequence of two or more individual scan cells. The custom shift array macro cell includes only two input pins and one output pin.
    Type: Application
    Filed: May 29, 2013
    Publication date: September 18, 2014
    Inventors: Hai Wang, Joseph Garofalo, Barry L. Bartholomew, Liu Ming Xu, Han Jun Zhang, You Xin Rao, Qin Xie
  • Publication number: 20140168050
    Abstract: Disclosed are a shift register, a gate driver and a display device, which relate the field of display technology and may eliminate the voltage coupled noise generated by a clock signal at an output terminal of the shift register effectively. The shift register comprises: a first input unit, a clock control unit, a second input unit, an inverting unit, a pulling-down unit and a first level selecting unit, a second level selecting unit, a third level selecting unit; the first input unit is connected with a first input signal terminal, the first level selecting unit and the second input unit, respectively, wherein a node at which the first input unit is connected with the second input unit is a pulling-up node, the first input unit is used for controlling a potential at the pulling-up node. The embodiments of the present disclosure may be applied to various display devices.
    Type: Application
    Filed: December 16, 2013
    Publication date: June 19, 2014
    Applicants: HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Xiaofang GU, Rui MA, Ming HU
  • Publication number: 20140133621
    Abstract: A shift register unit and a gate drive device for a liquid crystal display are disclosed. Both gate and drain of the tenth thin film transistor are connected to the source of the fifth thin film transistor, a source thereof is connected to a low voltage signal input terminal, threshold voltages of the eighth thin film transistor and the ninth thin film transistor are equal to or less than threshold voltage of the tenth thin film transistor. The shift register unit and the gate drive device for liquid crystal display provided in the present invention, could enable the thin film transistor used to suppress the noise in the shift register unit to maintain turning on, therefore it guarantees the reliability of the shift register unit.
    Type: Application
    Filed: January 23, 2014
    Publication date: May 15, 2014
    Applicants: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Guangliang SHANG
  • Publication number: 20140112429
    Abstract: A register file cell structure to enable lower voltage writes is disclosed. In one embodiment, a register file includes a state element made up of two cross-coupled inverters. Each of the inverters includes a p-channel metal oxide semiconductor (PMOS) transistor having a source terminal coupled to a virtual voltage node. One or more PMOS transistors are coupled in series between the virtual voltage node and a global voltage node. Each of the one or more PMOS transistors includes a gate terminal that is hardwired to a ground node, and thus these devices remain active when power is applied to the global voltage node. The presence of the one or more PMOS devices coupled between the virtual and global voltage nodes results in the ability to overwrite contents stored in the state element at lower voltages than otherwise attainable without the one or more PMOS devices.
    Type: Application
    Filed: October 23, 2012
    Publication date: April 24, 2014
    Applicant: APPLE INC.
    Inventors: Ajay Bhatia, Greg M. Hess, Sanjay P. Zambare
  • Publication number: 20140104153
    Abstract: A shift register unit comprises: a first transistor, a pulling-up close unit, a pulling-up start unit, a first pulling-up unit, a second pulling-up unit, a trigger unit, and an output unit. A shift register circuit, an array substrate and a display device are also provided. The shift register unit, the shift register circuit, the array substrate and the display device can reduce drift of a gate threshold voltage of a gate line driving transistor and improve operation stability of devices.
    Type: Application
    Filed: December 6, 2012
    Publication date: April 17, 2014
    Inventor: Zhanjie Ma
  • Publication number: 20140098928
    Abstract: A configuration of logic elements enables existing Serial-In-Parallel-Out (SIPO) shift registers to perform their own bit count, report the receipt of a valid transmission consisting of an expected number of bits and report the receipt of an invalid transmission consisting of greater than the expected number of bits. Logic elements additional to the foregoing enable SIPO shift registers to receive valid transmissions of varying expected numbers of bits. Special purpose integrated circuits (ICs) are disclosed which also contain the aforementioned configurations of logic elements. Newly designed SIPO shift registers which contain within them the foregoing configurations of logic elements are further disclosed. Potential messages of multiple acceptable message lengths are accommodated. Some embodiments are equipped with tri-state data outputs.
    Type: Application
    Filed: October 4, 2012
    Publication date: April 10, 2014
    Inventor: Richard C. Warner
  • Publication number: 20140085285
    Abstract: According to an embodiment, a gate shift register includes a plurality of stages cascade-connected to each other. An nth one of the stages includes: a pull-up transistor that outputs any one of gate shift clocks as an nth scan pulse of a gate high voltage in accordance with the potential of a Q node; a pull-down transistor that is connected to the pull-up transistor through an output node, and outputs a low-potential voltage as an nth scan pulse of a gate low voltage in accordance with the potential of a QB node; and a switching circuit that charges and discharges the Q node and the QB node, respectively, or vice versa in response to a set signal and a reset signal, wherein an adaptively adjusted variable high-potential voltage is applied to the QB node to correspond to a shift in the threshold voltage of the pull-down transistor.
    Type: Application
    Filed: December 10, 2012
    Publication date: March 27, 2014
    Applicant: LG DISPLAY CO., LTD.
    Inventor: Binn KIM
  • Patent number: 8675812
    Abstract: A configuration of logic elements enables existing Serial-In-Parallel-Out (SIPO) shift registers to perform their own bit count, report the receipt of a valid transmission consisting of an expected number of bits and report the receipt of an invalid transmission consisting of greater than the expected number of bits. Logic elements additional to the foregoing enable SIPO shift registers to receive valid transmissions of varying expected numbers of bits. Special purpose integrated circuits (ICs) are disclosed which also contain the aforementioned configurations of logic elements. Newly designed SIPO shift registers which contain within them the foregoing configurations of logic elements are further disclosed. Potential messages of multiple acceptable message lengths are accommodated. Some embodiments are equipped with tri-state data outputs.
    Type: Grant
    Filed: October 4, 2012
    Date of Patent: March 18, 2014
    Inventor: Richard C. Warner
  • Publication number: 20130322593
    Abstract: Discussed herein is a shift register which is capable of stabilizing an output thereof. The shift register includes a plurality of stages for sequentially outputting scan pulses in such a manner that high durations of the scan pulses partially overlap with each other. Each of the stages includes a node controller for controlling a charging duration of a set node, and an output unit for outputting a corresponding one of the scan pulses through an output terminal for the charging duration of the set node.
    Type: Application
    Filed: August 6, 2013
    Publication date: December 5, 2013
    Applicant: LG DISPLAY CO., LTD.
    Inventors: Yong-Ho JANG, Seung-Chan CHOI
  • Publication number: 20130321372
    Abstract: A shift register circuitry includes plurality stages of shift registers. An Nth stage shift register of the plurality stages of shift registers includes an input unit, an output unit, a control unit, a first pull-up unit, a second pull-up unit and a compensation circuit. The output unit is used to output an unmodified Nth stage scan signal. The input unit and the first pull-up unit are used to control the voltage level of a register control end. The control unit is used to receive a low reference voltage, a high reference voltage and the voltage level of the register control end, and control the voltage level of an output end of the control unit. The second pull-up unit is used to control the voltage level of an output end of the Nth stage shift register. The modification circuit is used to generate a modified Nth stage scan signal.
    Type: Application
    Filed: April 17, 2013
    Publication date: December 5, 2013
    Applicant: AU Optronics Corp.
    Inventors: Sen-Chuan Hung, Chun-Yen Liu
  • Patent number: 8552961
    Abstract: A shift register circuit includes plural shift register stages for providing plural gate signals. Each shift register stage includes a driving unit, an input unit, a driving adjustment unit and a pull-down unit. The driving unit is utilized for outputting a gate signal according to a system clock and a driving control voltage. The input unit is put in use for outputting the driving control voltage according to an input control signal and a first input signal. The driving adjustment unit is employed for adjusting the driving control voltage according to a second input signal and a third input signal. The pull-down unit is used for pulling down the gate signal and the driving control voltage according to a fourth input signal.
    Type: Grant
    Filed: May 13, 2011
    Date of Patent: October 8, 2013
    Assignee: AU Optronics Corp.
    Inventors: Yu-Chung Yang, Yung-Chih Chen
  • Publication number: 20130249876
    Abstract: A shift register apparatus including a first shift register cell is disclosed. The first shift register cell includes a first logic unit, a first control unit and a first output unit. The first logic unit generates a first control signal and a second control signal according to a start signal and a first setting signal. During a first period, the first control unit employs the first and second control signals to make a first clock signal update the first setting signal and the first output unit employs the first and second control signals to make a second clock signal update the first shifted signal. During a second period, the first output unit controls the first shifted signal according to the first and second control signals such that the first shifted signal does not follow the second clock signal.
    Type: Application
    Filed: March 11, 2013
    Publication date: September 26, 2013
    Applicant: INNOLUX CORPORATION
    Inventors: Sheng-Feng HUANG, Cheng-Hsiao LIN
  • Patent number: 8537963
    Abstract: An exemplary shift register is adapted for receiving a preceding-stage output signal to generate a preceding-stage supply signal and outputting an input signal as an extreme value of a current-stage output signal according to the preceding-stage supply signal. The shift register includes an active controller, a voltage boosting circuit and an output circuit. The active controller receives the preceding-stage output signal and thereby produces an active control signal. The voltage boosting circuit receives a first operating voltage, the preceding-stage supply signal and the active control signal, and uses a capacitive coupling effect to change the voltage value of the preceding-stage supply signal and thereby generates an output control signal. The output circuit is electrically coupled to the voltage boosting circuit, the active controller and the input signal and determines the time of outputting the input signal as the extreme value according to the output control signal.
    Type: Grant
    Filed: June 15, 2011
    Date of Patent: September 17, 2013
    Assignee: Au Optronics Corp.
    Inventor: Chung-Chun Chen
  • Publication number: 20130038583
    Abstract: Provided is a shift register circuit which includes: first through N-th circuit sections (1a, 1b) (N is an integer equal to or larger than 2) in each of which a plurality of shift register stages (SR1, SR2, . . . , SRn) are connected in cascade; and supply wires (10b, 10c, 10e, 10f). Each of the first through N-th circuit sections (1a, 1b) receives drive signals (CKA1, CKA2, CKB1, CKB2) for driving the shift register stages (SR1, SR2, . . . , SRn) via supply wires (10b, 10c, 10e, 10f) exclusive for the each of the first through N-th circuit sections (1a, 1b).
    Type: Application
    Filed: January 28, 2011
    Publication date: February 14, 2013
    Inventors: Junya Shimada, Shinya Tanaka, Tetsuo Kikuchi, Chikao Yamasaki, Masahiro Yoshida, Satoshi Horiuchi, Isao Ogasawara
  • Patent number: 8300761
    Abstract: A shift register circuit is provided that can decrease a power consumption caused by a clock signal and can achieve a high driving capacity. A unit shift register has a first transistor that activates an output signal when a power supply potential is provided to an output terminal. A pull-up driving circuit for driving the first transistor has a second transistor for providing a clock signal to a node connected to the gate of the first transistor and a boosting circuit for the node. When an output signal of a preceding stage is activated, the second transistor turns on. Thereafter, when the clock signal is activated, and the node is charged, the second transistor turns off. The boosting circuit increases the potential at the node when the second transistor turns off. Therefore, the first transistor can operate in non-saturation region and activate the output signal.
    Type: Grant
    Filed: March 23, 2012
    Date of Patent: October 30, 2012
    Assignee: Mitsubishi Electric Corporation
    Inventor: Youichi Tobita
  • Publication number: 20120200544
    Abstract: In a shift register that operates based on four-phase clock signals, including two-phase clock signals that are provided to odd-order stages and two-phase clock signals that are provided to even-order stages, of which phases are shifted by 90 degrees from each other, a potential of a first clock appears as a potential of a scanning signal, when a potential of a first node is at a high level, in each stage. In this configuration, the potential of the first node included in each stage is set to a high level based on a pulse of a scanning signal outputted from a pre-stage, and is set to a low level based on a pulse of a scanning signal outputted from a third stage after a stage concerned.
    Type: Application
    Filed: July 15, 2010
    Publication date: August 9, 2012
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Akihisa Iwamoto, Hideki Morii, Takayuki Mizunaga, Shinya Tanaka, Tetsuo Kikuchi, Takaharu Yamada, Satoshi Horiuchi, Chikao Yamasaki, Kei Ikuta
  • Publication number: 20120183117
    Abstract: A shift register circuit is provided that can decrease a power consumption caused by a clock signal and can achieve a high driving capacity. A unit shift register has a first transistor that activates an output signal when a power supply potential is provided to an output terminal. A pull-up driving circuit for driving the first transistor has a second transistor for providing a clock signal to a node connected to the gate of the first transistor and a boosting circuit for the node. When an output signal of a preceding stage is activated, the second transistor turns on. Thereafter, when the clock signal is activated, and the node is charged, the second transistor turns off. The boosting circuit increases the potential at the node when the second transistor turns off. Therefore, the first transistor can operate in non-saturation region and activate the output signal.
    Type: Application
    Filed: March 23, 2012
    Publication date: July 19, 2012
    Applicant: Mitsubishi Electric Corporation
    Inventor: Youichi TOBITA
  • Patent number: 8179357
    Abstract: In a semiconductor circuit a floating node is set to any voltage by utilizing a control signal applied to a refresh terminal and has a period shorter than that of a clock signal. The circuit includes first and second transistors connected between a first clock terminal and first power supply terminal, third and fourth transistors connected between the refresh terminal and the first power supply terminal, and fifth and sixth transistors connected between a second power supply terminal and the first power supply. Gates of the fourth and fifth transistors are connected to an input terminal, a gate of the third transistor is connected to a second clock terminal, a gate of the first transistor is connected to a node between the fifth and sixth transistors, gates of the second and sixth transistors are connected, and a node between the first and second transistors is connected to an output terminal.
    Type: Grant
    Filed: November 27, 2007
    Date of Patent: May 15, 2012
    Assignee: NLT Technologies, Ltd.
    Inventor: Tomohiko Otose
  • Patent number: 8175216
    Abstract: A shift register circuit is provided that can decrease a power consumption caused by a clock signal and can achieve a high driving capacity. A unit shift register has a first transistor that activates an output signal when a power supply potential is provided to an output terminal. A pull-up driving circuit for driving the first transistor has a second transistor for providing a clock signal to a node connected to the gate of the first transistor and a boosting circuit for the node. When an output signal of a preceding stage is activated, the second transistor turns on. Thereafter, when the clock signal is activated, and the node is charged, the second transistor turns off. The boosting circuit increases the potential at the node when the second transistor turns off. Therefore, the first transistor can operate in non-saturation region and activate the output signal.
    Type: Grant
    Filed: December 24, 2009
    Date of Patent: May 8, 2012
    Assignee: Mitsubishi Electric Corporation
    Inventor: Youichi Tobita
  • Publication number: 20120051494
    Abstract: A shift register circuit includes a plurality of shift registers. Each of the shift registers is configured for outputting a corresponding start-pulse signal and a corresponding driving-pulse signal. Each of the shift registers includes a pull-up circuit, a first driving circuit, a second driving circuit and a discharging circuit. The pull-up circuit is configured for charging a first node. The first driving circuit is configured for generating the corresponding start-pulse signal, and the second driving circuit is configured for generating the corresponding driving-pulse signal. The discharging circuit firstly discharges the first node before discharging an output terminal of the second driving circuit.
    Type: Application
    Filed: March 10, 2011
    Publication date: March 1, 2012
    Applicant: AU OPTRONICS CORP.
    Inventors: Yu-Chung YANG, Yung-Chih CHEN, Chih-Ying LIN, Kun-Yueh LIN
  • Patent number: 8115727
    Abstract: Systems for displaying images are provided. A representative system incorporates a digital data sampling circuit with N stage data inputs. The first stage flip-flop outputs a first output signal. The second stage flip-flop outputs a second output signal. The first stage sample latch circuit receives digital data according to a first control signal. The first stage logic circuit comprises a first converter for inverting the second output signal and generating a first inverse logic signal, and generates the first control signal according to the first output signal and the first inverse logic signal.
    Type: Grant
    Filed: May 25, 2006
    Date of Patent: February 14, 2012
    Assignee: Chimei Innolux Corporation
    Inventors: Chueh-Kuei Jan, Ching-Wei Lin, Meng-Hsun Hsieh
  • Publication number: 20120032615
    Abstract: Provided is a shift register configured by cascade connecting unit circuits each including a bootstrap circuit. In at least one example embodiment, for the unit circuits, a time period during which a transistor is in an ON state and a clock signal is high level corresponds to a clock passing period. Among transistors whose one conduction terminal is connected to a gate of the transistor, channel lengths of transistors configured such that a low-level potential is fed to gates of the transistors to turn the transistors to an OFF state in the clock passing period and that a low-level potential is applied to the conduction terminal of the transistors in the clock passing period are made longer than the channel length of the transistor. With this, it is possible to reduce a leakage current in the clock passing period, and to prevent the fluctuation of a gate potential of the transistor and dullness in an output signal from occurring.
    Type: Application
    Filed: December 25, 2009
    Publication date: February 9, 2012
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Tetsuo Kikuchi, Shinya Tanaka, Chikao Yamasaki, Junya Shimada
  • Patent number: 8089448
    Abstract: A data driver for time-division multiplexing includes a first memory cell set having first memory cells, a second memory cell set having second memory cells, and a plurality of output lines. Each first memory cell is used for generating a first data signal in response to a first sampling control signal, and for outputting the first data signal in response to a first transmitting control signal. Each second memory cell is used for generating a second data signal in response to a second sampling control signal, and for outputting the second data signal in response to a second transmitting control signal. During a first line time period, the first sampling control signal is triggered while the second transmitting control signal is triggered. During a second line time period, the first transmitting control signal is triggered while the second sampling control signal is triggered.
    Type: Grant
    Filed: February 9, 2009
    Date of Patent: January 3, 2012
    Assignee: AU Optronics Corp.
    Inventor: Chung-chun Chen
  • Publication number: 20110317803
    Abstract: An exemplary shift register circuit includes a plurality of shift registers for sequentially outputting a plurality of driving pulse signals. Among each M number of the shift registers for sequentially outputting M number of the driving pulse signals, the shift register for lastly outputting one of the M number of driving pulse signals is enabled, by (M?1) number of start pulse signals sequentially outputted from the remained (M?1) number of the shift registers, to generate the driving pulse signal. Herein, M is a positive integer greater than 2. Moreover, a circuit structure of a shift register also is provided.
    Type: Application
    Filed: March 8, 2011
    Publication date: December 29, 2011
    Applicant: AU OPTRONICS CORP.
    Inventors: Chen-Lun CHIU, Yi-Suei Liao, Ping-Lin Chen, Kuan-Yu Chen
  • Publication number: 20110286572
    Abstract: A shift register unit includes an input module for inputting a second clock signal or a third clock signal, and for inputting a frame starting signal, a first clock signal, a low voltage signal, a reset signal as well as a first signal and a second signal transmitted from a next neighboring shift register unit; a processing module for generating a gate driving signal and allowing a level of at least one of first junctions formed by at least two TFTs to be maintained at low level in a frame interval during which the second clock signal or the third clock signal inputted from the input module is maintained at low level; and an output module for transmitting the gate driving signal generated by the processing module.
    Type: Application
    Filed: May 13, 2011
    Publication date: November 24, 2011
    Applicant: BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Guangliang SHANG, Seung Woo HAN
  • Patent number: 8044894
    Abstract: After a sampling transistor is turned ON at a first timing when a control signal has risen, during a sampling period from a second timing when a video signal has risen from a reference potential to a signal potential to a third timing when the control signal has fallen and is turned OFF, the sampling transistor samples and writes the signal potential in a holding capacitance, and negatively feeds back a current flowing into a drive transistor during the sampling period to the holding capacitance and applies mobility correction of the drive transistor on the written signal potential. A signal driver adjusts the second timing for the video signal supplied to respective signal lines to correct a backward shift of the third timing due to a transmission delay along a scanning line of the control signal output from the control scanner.
    Type: Grant
    Filed: March 12, 2008
    Date of Patent: October 25, 2011
    Assignee: Sony Corporation
    Inventors: Katsuhide Uchino, Tetsuro Yamamoto
  • Publication number: 20110134107
    Abstract: A shift register, each stage thereof provided to drive a corresponding output line, includes an output transistor that drives the output line and an additional transistor of the same technology and of the same polarity as the output transistor. The additional transistor is connected in such a way as to be subject to bias conditions similar to the output transistor, such that the additional transistor's threshold voltage, identical at the start of life to that of the output transistor, drifts as quickly or more quickly as the threshold voltage of the output transistor. The additional transistor is used to adjust the precharging voltage of a gate of the output transistor to its conduction performance characteristics during the precharging and/or selection phase.
    Type: Application
    Filed: August 4, 2009
    Publication date: June 9, 2011
    Applicant: THALES
    Inventors: Hugues Lebrun, Thierry Kretz, Chantal Hordequin
  • Patent number: 7924260
    Abstract: A shift register applied on a double-frame-rate LCD is provided. The LCD includes an upper display area with c gate lines, a lower display area with d gate lines, and a gate driving circuit. The gate driving circuit includes a first shift register coupled to the corresponding x gate lines of the upper display area, a second shift register coupled to the corresponding y lines of the lower display area, and a third shift register coupled to the corresponding (c-x) gate lines of the upper display area and the corresponding (d-y) gate lines of the lower display area.
    Type: Grant
    Filed: February 12, 2008
    Date of Patent: April 12, 2011
    Assignee: AU Optronics Corp.
    Inventors: Ming-Hung Tu, Chih-Hsiang Yang
  • Patent number: 7889831
    Abstract: A column repair circuit uses a system of circuits that automatically stops the shifting of register contents independently of the number of bits to be shifted. The circuit is only dependent on the number of bits in a column address repair block. By adding shift register positions to one end of each shift register chain, a dedicated block of bits is used to detect the end of the shift chain without explicitly knowing the length of the chain. The shift register positions provide a hard-programmed code that can be used to stop the shifting of data automatically. The shift register positions also provide a space for hard-programmed code bits that can be examined to determine when the shift process ends. A shift chain can be controlled with a controller so long as the information is organized into groups of ‘k’ bits. The controller only requires information regarding the value of the number ‘k’ and the pre-programmed stop code in order to control any number of bits in a shift chain.
    Type: Grant
    Filed: December 12, 2007
    Date of Patent: February 15, 2011
    Assignee: ProMOS Technologies Pte. Ltd.
    Inventor: Christopher M. Mnich
  • Patent number: 7889832
    Abstract: Disclosed is a shift register which includes first transistor connected between a first clock signal terminal and an output terminal, a second transistor with a gate connected to an input terminal and a source connected to a gate of the first transistor, a third transistor with a gate connected to a second clock signal terminal, an inverter with an input connected to the input terminal, a fourth transistor cascode connected to the third transistor with a gate connected to an output of the inverter, a fifth transistor connected between the gate of the first transistor and a power supply terminal, a sixth transistor connected between the fourth transistor and the power supply terminal with a gate connected to the input terminal, and a seventh transistor connected between the output terminal and the power supply terminal, the fifth and seventh transistors having gates connected in common to a connection node of the fourth and the sixth transistors.
    Type: Grant
    Filed: May 22, 2009
    Date of Patent: February 15, 2011
    Assignee: NEC LCD Technologies, Ltd.
    Inventors: Tomohiko Otose, Masamichi Shimoda
  • Publication number: 20110002438
    Abstract: Disclosed is a dual shift register that includes a first shift register configured to include a plurality of stages which sequentially output scan pulses using at least two clock signals with sequential and circular phases, and a second shift register configured to a plurality of stages which form pair with the respective stages of the first shift register and sequentially output the scan pulses using at least two clock signals. Each stage includes: a scan direction controller configured to respond to the scan pulses from previous and next stages and to selectively output forward and reverse direction voltages with opposite electric potentials to each other; and an output portion configured to respond to the output signal of the scan direction controller, to generate two sequential scan pulses using two of the at least two clock signals, and to distribute the sequential scan pulses to the previous and next stages.
    Type: Application
    Filed: July 1, 2010
    Publication date: January 6, 2011
    Inventor: Hong Jae KIM
  • Patent number: 7852309
    Abstract: Provided is a scan driver that supplies a scan signal to an organic light emitting display device (OLED). The scan driver includes transistors of the same conductivity type. To generate individual scan signals, the scan driver includes samplers, each of which samples an input signal in synchronization with a clock signal or an inverted clock signal; and an OR gate and a NAND gate, each of which performs a logical operation on output signals of adjacent samplers and generates a scan signal. The samplers, the OR gate and the NOR gate include transistors of the same conductivity type.
    Type: Grant
    Filed: July 20, 2006
    Date of Patent: December 14, 2010
    Assignee: Samsung Mobile Display Co., Ltd.
    Inventor: Bo-Yong Chung
  • Patent number: 7800575
    Abstract: The present invention provides a display device which includes a drive circuit having a CMOS shift register circuit constituted of a simple CMOS circuit. A drive circuit includes a shift register circuit, and the shift register circuit includes n(n?2) pieces of basic circuits which are connected vertically in multiple stages.
    Type: Grant
    Filed: February 5, 2007
    Date of Patent: September 21, 2010
    Assignee: Hitachi Displays, Ltd.
    Inventors: Takayuki Nakao, Hideo Sato, Masahiro Maki, Toshio Miyazawa
  • Patent number: 7774674
    Abstract: The LDPC decoder includes a processor for updating messages exchanged iteratively between variable nodes and check nodes of a bipartite graph of the LDPC code. The decoder architecture is a partly parallel architecture clocked by a clock signal. The processor includes P processing units. First variable nodes and check nodes are mapped on the P processing units according to two orthogonal directions. The decoder includes P main memory banks assigned to the P processing units for storing all the messages iteratively exchanged between the first variable nodes and the check nodes. Each main memory bank includes at least two single port memory partitions and one buffer the decoder also includes a shuffling network and a shift memory.
    Type: Grant
    Filed: March 2, 2006
    Date of Patent: August 10, 2010
    Assignee: Stmicroelectronics N.V.
    Inventors: Norbert Wehn, Frank Kienle, Torben Brack
  • Publication number: 20100166136
    Abstract: A shift register circuit is provided that can decrease a power consumption caused by a clock signal and can achieve a high driving capacity. A unit shift register has a first transistor that activates an output signal when a power supply potential is provided to an output terminal. A pull-up driving circuit for driving the first transistor has a second transistor for providing a clock signal to a node connected to the gate of the first transistor and a boosting circuit for the node. When an output signal of a preceding stage is activated, the second transistor turns on. Thereafter, when the clock signal is activated, and the node is charged, the second transistor turns off. The boosting circuit increases the potential at the node when the second transistor turns off. Therefore, the first transistor can operate in non-saturation region and activate the output signal.
    Type: Application
    Filed: December 24, 2009
    Publication date: July 1, 2010
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Youichi TOBITA
  • Publication number: 20090251443
    Abstract: Disclosed herein is a shift register circuit that is formed on an insulating substrate with thin film transistors having channels of the same conductivity type and includes shift stages, each of the shift stages including: a first thin film transistor; a second thin film transistor; a 3(1)-th thin film transistor; a 3(2)-th thin film transistor; a 4(1)-th thin film transistor; a 4(2)-th thin film transistor; a fifth thin film transistor; and a sixth thin film transistor.
    Type: Application
    Filed: February 24, 2009
    Publication date: October 8, 2009
    Applicant: Sony Corporation
    Inventor: Seiichiro Jinta
  • Patent number: 7529333
    Abstract: A shift register includes first and second stages for sequentially outputting scan pulses to drive first and second gate lines. One of the first and second stages includes a pull-up switching device connected to an enabling node of the one of the first and second stages; a first pull-down switching device connected to a first disabling node of the one of the first and second stages; a second pull-down switching device connected to a second disabling node of the one of the first and second stages; and a node controller. The node controller of the first stage controls the logic state of each of the enabling node of the first stage, the first disabling node of the first stage and the first disabling node of the second stage. The node controller of the second stage controls the logic state of each of the enabling node of the second stage, the second disabling node of the second stage and the second disabling node of the first stage.
    Type: Grant
    Filed: October 26, 2006
    Date of Patent: May 5, 2009
    Assignee: LG Display Co., Ltd.
    Inventors: Binn Kim, Hae Yeol Kim, Hyung Nyuck Cho, Soo Young Yoon, Seung Chan Choi, Min Doo Chun, Yong Ho Jang
  • Patent number: RE46141
    Abstract: A semiconductor device includes a power-supply control portion and a latch portion. The power-supply control portion supplies power to an internal circuit in response to an input signal synchronized with rising of clock. The latch portion latches the input signal in synchronization with falling of the clock and supplies the latched input signal to the internal circuit.
    Type: Grant
    Filed: March 12, 2014
    Date of Patent: September 6, 2016
    Assignee: PS4 Luxco S.a.r.l.
    Inventors: Hideyuki Yoko, Ryuuji Takishita