Abstract: A driving device of a liquid crystal display (LCD) utilized for preventing noises of a clock signal from causing error operation of a shift register is disclosed. The driving device includes a shift register, a reception terminal, a noise elimination circuit and a control signal generation circuit. The reception terminal is utilized for receiving a first clock signal. The noise elimination circuit is coupled to the reception terminal, and is utilized for eliminating noises of the first clock signal and delaying the first clock signal for a preset time to generate a second clock signal. The control signal generation circuit is coupled to the reception terminal, the noise elimination circuit and the shift register, and is utilized for generating a first control signal and a second control signal to control the shift register.

Abstract: A sensor scan driver may include a shift register unit for driving photodiodes, a transmission gate unit for changing a voltage range of sensor scan signals generated by the shift register unit, and a buffer unit for supplying the sensor scan signals supplied from the transmission gate unit to the photodiodes, wherein the transmission gate unit includes first and second transmission gates, each including an electrode adapted to receive an output signal of the shift register unit, another electrode adapted to receive the inverted output signal of the shift register unit, an input terminal coupled to first and second power sources, respectively, and an output terminal coupled to an output terminal of the transmission gate unit.

Abstract: A shift register circuit includes plural shift register stages for providing plural gate signals. Each shift register stage includes a driving unit, an input unit, a driving adjustment unit and a pull-down unit. The driving unit is utilized for outputting a gate signal according to a system clock and a driving control voltage. The input unit is put in use for outputting the driving control voltage according to an input control signal and a first input signal. The driving adjustment unit is employed for adjusting the driving control voltage according to a second input signal and a third input signal. The pull-down unit is used for pulling down the gate signal and the driving control voltage according to a fourth input signal.

Abstract: A display apparatus includes a gate driver which sequentially outputs a gate signal at a high state in response to a gate control signal and a data driver which converts image data into a data signal in response to a data control signal. The display apparatus further includes a display panel which includes a plurality of gate lines which sequentially receive the gate signal, a plurality of data lines which receive the data signal and a plurality of pixels connected to the gate and data lines and which receive the data signal in response to the gate signal to display an image. The polarity of the data signal is inverted after the gate signal transitions to a low state.

Abstract: A driving circuit applied in an electronic display apparatus is provided. The driving circuit includes a first exchange circuit and a first buffer. The first buffer includes first and second input stages, a second exchange circuit and first and second output stages. The first exchange circuit selectively couples a first input signal and a first output signal outputted from the first output stage to one of the first and the second input stages; and selectively couples a second input signal and a second output signal outputted from the second output stage to the other of the first and the second input stages. The second exchange circuit selectively couples the first input stage to one of the first and the second output stages and selectively couples the second input stage to the other of the first and the second output stages.

Abstract: A solid-state image-capturing device which has built in an image-capturing area including a light receiving element provided on a semiconductor substrate, a substrate bias circuit, and a clamp circuit for receiving output of the substrate bias circuit and applying the output of the substrate bias circuit to the semiconductor substrate in accordance with a substrate pulse, comprises a substrate bias control circuit for controlling so as to reduce an electric current of the clamp circuit during a predetermined period.

Abstract: In one embodiment, a phase error signal generated by a phase detector is equalized to compensate for the distortion in the phase error signal due to finite circuit speeds. The equalization may be based on suppressing the low frequency components of the phase error signal. For example, the amplitude of the phase error signal may be reduced when the amplitude of the phase error signal is not changing.

Abstract: A method forms a feature pattern on a substrate by exposing the substrate, using a mask having a pattern of features thereon, with illumination having a first set of settings. The substrate is exposed a second time, using the same mask having the pattern of features thereon, with illumination having a second set of settings. The mask having the pattern of features thereon remains stationary between the two illumination exposures of the substrate.

Abstract: To reduce a circuit area of a data line driving circuit. The data line driving circuit includes a plurality of circuit blocks. A circuit block has shift register unit circuits, logical operation unit circuits and a control unit circuit. The control unit circuit specifies the operation period of the corresponding circuit block on the basis of the input and output signals of the shift register unit circuits and supplies a clock signal and an inverted clock signal to the shift register unit circuit.

Abstract: A shift-register circuit comprises an inverter and first to fourth transistors. The first transistor includes a gate coupled to an inverse clock signal, and a first source/drain coupled to a signal output from a previous-stage shift-register unit. The inverter includes a first input terminal coupled to the first source/drain of the first transistor. The second transistor includes a gate coupled to a second source/drain of the first transistor, a first source/drain coupled to a clock signal, and a second source/drain coupled to an output terminal. The third transistor includes a gate coupled to a first output terminal of the inverter, a first source/drain coupled to the output terminal, and a second source/drain coupled to a first voltage. The fourth transistor includes a gate coupled to a signal output from a next-stage shift-register unit, a first source/drain coupled to the output terminal, and a second source/drain coupled to the first voltage.

Abstract: Microprocessor with registered clock counting for at a predetermined count producing a command signal of adjustable shape, and a hierarchical interrupt system for use therewith.A microprocessor comprises registered counting means that counts clock pulses. Upon attainment of a predetermined count it generates a command signal. Furthermore, it has a presettable input section that recurrently receives a variable preset count for downcounting, a secondary count section that is fed by said command signal output for counting successive command signals and under control of attainment of a predetermined count generates a secondary command signal on a secondary output. Next, a programmable registered pulse shaper mechanism under control of said secondary command signal executes serial shifting and outputs a shaped version of the secondary command signal. The above counting means is also associated to a parametrizeable interrupt priority mechanism.

Abstract: A signal transfer circuit for dynamic action with boot strap effect is formed with an inputting transistor Tr.sub.11 and a driving transistor Tr.sub.12 for driving a load Z.sub.1. To a gate electrode of a resetting transistor Tr.sub.13, a positive voltage V.sub.1 and a negative voltage V.sub.2 are alternately applied at 50% of duty ratio in synchronism with a shift pulse by transistors Tr.sub.15 and Tr.sub.16 connected in series between the positive voltage V.sub.1 and the negative voltage V.sub.2 and pulses .PHI..sub.1R and .PHI..sub.2R which are synchronous with shift pulses .PHI..sub.1 and .PHI..sub.2. When an output Q.sub.1 is HIGH level, a transistor Tr.sub.14 becomes conductive to force a gate voltage of the transistor Tr.sub.13 to 0 to release resetting.