With Feedback Patents (Class 377/72)
  • Patent number: 10026496
    Abstract: A shift register unit and a method for driving the shift register unit, a gate drive circuit and a display device are provided. The shift register unit includes an inputting unit, an outputting unit, a reset unit, a first control unit and a second control unit, a first node, a second node, a third node, a shift signal outputting terminal and multiple inputting terminals. A width of a shift pulse output by the shift register unit may be adjusted by adjusting a width of a shift pulse input to the shift register unit, and the output shift pulse and the input shift pulse have an identical width.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: July 17, 2018
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Zhanjie Ma
  • Patent number: 9397663
    Abstract: An Integrated Circuit (IC) includes signal distribution circuitry and protection circuitry. The signal distribution circuitry is configured to distribute a high-fanout signal across the IC. The protection circuitry includes a plurality of logic stages and detection circuitry. The logic stages are configured to receive multiple instances of the signal that are sampled at multiple sampling points in the signal distribution circuitry. The logic stages are interconnected to drive one another in accordance with a given topology so as to propagate abnormalities indicative of faults occurring in the signal distribution circuitry. The detection circuitry is configured to detect a fault in the signal distribution circuitry in response to an abnormality propagating in the plurality of logic stages.
    Type: Grant
    Filed: June 28, 2015
    Date of Patent: July 19, 2016
    Assignee: WINBOND ELECTRONICS CORPORATION
    Inventors: Nir Tasher, Valery Teper, Leonid Azriel
  • Patent number: 9318064
    Abstract: A shift register includes shift register units, in which at least one shift register unit is coupled to a forestage shift register unit and a post-stage shift register unit, where the at least one shift register unit includes a signal input circuit, a signal output circuit, a pull down circuit and a switching circuit. The signal input circuit electrically coupled to the forestage shift register unit can receive a logic signal from the forestage shift register. The signal output circuit is electrically coupled to the signal input circuit via a control signal terminal and is electrically coupled to the post-stage shift register unit. The signal output to circuit can receive a first clock signal. The pull down circuit is electrically coupled to or electrically isolated from the control signal terminal through the switching circuit.
    Type: Grant
    Filed: October 26, 2012
    Date of Patent: April 19, 2016
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Pei-Hua Chen, Yu-Hsin Ting, Chung-Lin Fu, Tsao-Wen Lu, Nan-Ying Lin, Wei-Chun Hsu
  • Patent number: 8914695
    Abstract: Methods and apparatuses are described for decompressing and routing test data. Some embodiments feature an integrated circuit (IC) that includes two or more shift registers configured to shift in the test data. Each of the two or more shift registers can include two or more sequential elements configured such that a scan chain in the set of scan chains receives inputs from at most one sequential element in each of the two or more shift registers. At least one shift register in the two or more shift registers can be configured as a circular shift register. The IC can also include a logic network coupled between the two or more shift registers and the set of scan chains such that the set of scan chains receives the decompressed test data from the two or more shift registers via the logic network.
    Type: Grant
    Filed: May 17, 2011
    Date of Patent: December 16, 2014
    Assignee: Synopsys, Inc.
    Inventor: Emil I. Gizdarski
  • Patent number: 8773346
    Abstract: A driving device of a liquid crystal display (LCD) utilized for preventing noises of a clock signal from causing error operation of a shift register is disclosed. The driving device includes a shift register, a reception terminal, a noise elimination circuit and a control signal generation circuit. The reception terminal is utilized for receiving a first clock signal. The noise elimination circuit is coupled to the reception terminal, and is utilized for eliminating noises of the first clock signal and delaying the first clock signal for a preset time to generate a second clock signal. The control signal generation circuit is coupled to the reception terminal, the noise elimination circuit and the shift register, and is utilized for generating a first control signal and a second control signal to control the shift register.
    Type: Grant
    Filed: October 1, 2013
    Date of Patent: July 8, 2014
    Assignee: NOVATEK Microelectronics Corp.
    Inventors: Tung-Shuan Cheng, Yueh-Hsiu Liu, Kai-Shu Han
  • Patent number: 8736539
    Abstract: A driver circuit includes first to third transistors, a first circuit, and a second circuit. In the first transistor, a first terminal is electrically connected to a second wiring, a second terminal is electrically connected to a first wiring, and a gate is electrically connected to the second circuit and a first terminal of the third transistor. In the second transistor, a first terminal is electrically connected to the first wiring, a second terminal is electrically connected to a sixth wiring, a gate is electrically connected to the first circuit and a gate of the third transistor. A second terminal of the third transistor is electrically connected to the sixth wiring. The first circuit is electrically connected to a third wiring, a fourth wiring, a fifth wiring, and the sixth wiring. The second circuit is electrically connected to the first wiring, the second wiring, and the sixth wiring.
    Type: Grant
    Filed: January 16, 2013
    Date of Patent: May 27, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Atsushi Umezaki
  • Publication number: 20140079175
    Abstract: A shift register, a driving apparatus and a display. The shift register comprises: an evaluating unit for receiving a second clock signal and outputting an output signal to a signal output terminal under a control of an input signal; a reset controlling unit, a first terminal of which being connected to the evaluating unit and receiving the input signal, a second terminal of which receiving a first clock signal, a third terminal of which receiving a low level signal, for inputting a control signal to a reset unit under controls of the input signal and the first clock signal; the reset unit for receiving a high level signal and resetting the signal output terminal under a control of the control signal input by the reset controlling unit. When the shift register evaluates the output terminal, the gate of the reset transistor (4) is charged rapidly, which renders that the reset transistor (4) is turned off in time.
    Type: Application
    Filed: November 30, 2012
    Publication date: March 20, 2014
    Applicant: BOE Technology Group Co., Ltd.
    Inventor: Zhongyuan Wu
  • Patent number: 8614700
    Abstract: A voltage level shifter formed by single-typed transistors comprises two input terminals, two power supply terminals, a plurality of thin-film transistors, and an output terminal. Another voltage level shifter formed by single-typed transistors comprises two input terminals, an output terminal, two power supply terminals, two input units, a first thin-film transistor, a disable unit, a feedback unit, and a second thin-film transistor. The voltage level shifters are formed by single-typed TFTs. When integrating the voltage level shifters into a substrate of a TFT display, the manufacturing processes are simplified. Besides, power is saved.
    Type: Grant
    Filed: May 3, 2011
    Date of Patent: December 24, 2013
    Assignee: AU Optronics Corp.
    Inventor: Jian-Shen Yu
  • Patent number: 8593378
    Abstract: An organic light emitting display device capable of displaying an image of uniform brightness. A scan driver drives scan lines and light emitting control lines that are formed parallel to each other. A data driver drives data lines formed at a direction intersecting the scan lines and the light emitting control lines, and pixels are disposed to be coupled with the scan lines, the light emitting control lines, and the data lines. An auxiliary line is formed parallel to the data lines. One side of the auxiliary line is coupled with a reference power supply and another side of the auxiliary line is coupled with a current source. Connectors are disposed at crossing areas of the auxiliary line and the scan lines. A voltage transfer unit is coupled with the connectors and transfers a voltage supplied to the connectors to the data driver.
    Type: Grant
    Filed: July 20, 2006
    Date of Patent: November 26, 2013
    Assignee: Samsung Display Co., Ltd.
    Inventors: Do Hyung Ryu, Bo Yong Chung, Oh Kyong Kwon
  • Patent number: 8558779
    Abstract: A display device comprises a driver circuit having a shift register circuit having a level conversion function is provided with a simple circuit configuration of first, second, and third basic circuits connected in tandem at multistages. A common clear signal is supplied to a control electrode of a third transistor of each basic circuit, a first clock is supplied to a control electrode of a first transistor of each of the first and third basic circuits, a second clock different in phase from the first clock is supplied to a control electrode of a first transistor of the second basic circuit, outputs of the first and second basic circuit are respectively supplied to control electrodes of second transistors of the second and third basic circuits, and an inversion output of the third basic circuit is supplied to a control electrode of a fourth transistor of the first basic circuit.
    Type: Grant
    Filed: July 24, 2012
    Date of Patent: October 15, 2013
    Assignees: Hitachi Displays, Ltd., Panasonic Liquid Crystal Display Co., Ltd.
    Inventors: Hideo Sato, Shigeyuki Nishitani, Takayuki Nakao, Masahiro Maki
  • Patent number: 8552961
    Abstract: A shift register circuit includes plural shift register stages for providing plural gate signals. Each shift register stage includes a driving unit, an input unit, a driving adjustment unit and a pull-down unit. The driving unit is utilized for outputting a gate signal according to a system clock and a driving control voltage. The input unit is put in use for outputting the driving control voltage according to an input control signal and a first input signal. The driving adjustment unit is employed for adjusting the driving control voltage according to a second input signal and a third input signal. The pull-down unit is used for pulling down the gate signal and the driving control voltage according to a fourth input signal.
    Type: Grant
    Filed: May 13, 2011
    Date of Patent: October 8, 2013
    Assignee: AU Optronics Corp.
    Inventors: Yu-Chung Yang, Yung-Chih Chen
  • Patent number: 8497834
    Abstract: A signal output circuit of the present invention is provided in a unit stage of a shift register. The signal output circuit includes a set-reset flip-flop, and a signal generation circuit for generating an output signal by loading or blocking a clock signal in accordance with a signal inputted thereto. The signal output circuit is arranged such that: the signal generation circuit receives a signal outputted from the flip-flop and the output signal fed back to the signal generating circuit; and the output signal is fed back to a reset input of the flip-flop. This makes it possible to achieve a reduction in the area of the circuit and a simplification of the circuit.
    Type: Grant
    Filed: November 12, 2012
    Date of Patent: July 30, 2013
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Etsuo Yamamoto, Yuhichiroh Murakami, Eiji Matsuda
  • Patent number: 8344988
    Abstract: A signal output circuit of one embodiment of the present invention is provided in a unit stage of a shift register. The signal output circuit includes a set-reset flip-flop, and a signal generation circuit for generating an output signal by loading or blocking a clock signal in accordance with a signal inputted thereto. The signal output circuit is arranged such that: the signal generation circuit receives a signal outputted from the flip-flop and the output signal fed back to the signal generating circuit; and the output signal is fed back to a reset input of the flip-flop. This makes it possible to achieve a reduction in the area of the circuit and a simplification of the circuit.
    Type: Grant
    Filed: July 13, 2006
    Date of Patent: January 1, 2013
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Etsuo Yamamoto, Yuhichiroh Murakami, Eiji Matsuda
  • Patent number: 8345028
    Abstract: A driving circuit applied in an electronic display apparatus is provided. The driving circuit includes a first exchange circuit and a first buffer. The first buffer includes first and second input stages, a second exchange circuit and first and second output stages. The first exchange circuit selectively couples a first input signal and a first output signal outputted from the first output stage to one of the first and the second input stages; and selectively couples a second input signal and a second output signal outputted from the second output stage to the other of the first and the second input stages. The second exchange circuit selectively couples the first input stage to one of the first and the second output stages and selectively couples the second input stage to the other of the first and the second output stages.
    Type: Grant
    Filed: August 5, 2010
    Date of Patent: January 1, 2013
    Assignee: Raydium Semiconductor Corporation
    Inventors: Chih-Chuan Huang, Yu-Lung Lo, Hsin-Yeh Wu
  • Patent number: 8289261
    Abstract: A gate driving circuit that may be capable of improving driving margin and maintaining reliability even after long use, and a display device having the gate driving circuit. The gate driving circuit includes a shift register having a plurality of stages dependently connected to one another, wherein each stage includes a pull-up unit outputting a first clock signal as a gate signal in response to a signal of a first node, to which a first input signal is applied, a pull-down unit discharging the gate signal to a gate-off voltage in response to a second input signal, a discharging unit discharging the signal of the first node to the gate-off voltage in response to the second input signal, and a holding unit maintaining the signal of the first node at the gate-off voltage in response to a delay signal of the first clock signal.
    Type: Grant
    Filed: July 22, 2009
    Date of Patent: October 16, 2012
    Assignee: Samsung Display Co., Ltd.
    Inventors: Min-Cheol Lee, Yong-Soon Lee
  • Patent number: 8275089
    Abstract: It discloses a shift register and a gate line driving device, relating to the technology field for a liquid crystal display, it is made to reduce the switching on errors for gate lines and improve the quality of the image. Said shift register includes: a first thin film transistor, a second thin film transistor, a third thin film transistor, a storage capacitor, a feedback module, and a switch module, wherein said feedback module is used to receive a trigger signal of the feedback module of the previous stage and a clock signal in order to pull up the level of the first node Qa as a pull up node, and to output a feedback signal to the shift register of the previous stage and output a trigger signal to the feedback module of the next stage, said switch module is used to maintain the output terminal of the shift register of the present stage at a low level when the shift register of the present stage does not operate. An embodiment of the present invention is applied to a liquid crystal display panel.
    Type: Grant
    Filed: September 22, 2010
    Date of Patent: September 25, 2012
    Assignee: Beijing Boe Optoelectronics Technology Co., Ltd.
    Inventor: Ming Hu
  • Patent number: 8266194
    Abstract: A system comprising a feedback shift-register having L serially connected stages, and a non-linear feedback sub-system to receive input from stage n and 2n+1, and including a first AND gate having a first and second input operationally connected to the output of stage n and 2n+1, respectively, the sub-system having an output based on a value of an output of the first AND gate, a bit generator operative to generate bits, and an XOR gate having a first and second input, an output of the bit generator being operationally connected to the first input of the XOR gate, the output of the sub-system being operationally connected to the second input of the XOR gate, the output of the XOR gate being operationally connected to the input of the first stage of the shift-register. Related apparatus and methods are also described.
    Type: Grant
    Filed: June 26, 2008
    Date of Patent: September 11, 2012
    Assignee: NDS Limited
    Inventor: Uri Kaluzhny
  • Patent number: 8259055
    Abstract: A display device comprises a driver circuit having a shift register circuit having a level conversion function is provided with a simple circuit configuration of first, second, and third basic circuits connected in tandem at multistages. A common clear signal is supplied to a control electrode or a third transistor of each basic circuit, a first clock is supplied to a control electrode of a first transistor of each of the first and third basic circuits, a second cock different in phase from the first clock is supplied to a control electrode of a first transistor of the second basic circuit, outputs of the first and second basic circuit are respectively supplied to control electrodes of second transistors of the second and third basic circuits, and an inversion output of the third basic circuit is supplied to a control electrode of a fourth transistor of the first basic circuit.
    Type: Grant
    Filed: February 7, 2007
    Date of Patent: September 4, 2012
    Assignees: Hitachi Displays, Ltd., Panasonic Liquid Crystal Display Co., Ltd.
    Inventors: Hideo Sato, Shigeyuki Nishitani, Takayuki Nakao, Masahiro Maki
  • Patent number: 8217866
    Abstract: A data driving circuit capable of displaying images having uniform brightness. The present invention provides a data driving circuit of a display device having: at least one current sinking unit for controlling a predetermined current to flow in a data line; at least one voltage generating unit for resetting voltage values of enhancement voltages using a compensation voltage generated when the predetermined current flows; at least one digital-analog converter for selecting as a data signal one of the enhancement voltages to correspond to a digital value of externally supplied data; at least one boosting unit for boosting a voltage value of the data signal; and at least one switching unit for providing the data line with the boosted data signal.
    Type: Grant
    Filed: July 20, 2006
    Date of Patent: July 10, 2012
    Assignees: Samsung Mobile Display Co., Ltd., IUCF-HYU (Industry-University Cooperation Foundation Hanyang University)
    Inventors: Do Hyung Ryu, Bo Yong Chung, Oh Kyong Kwon
  • Patent number: 8184034
    Abstract: A code sequence generator (20) comprising a memory (22), a feedback logic network (24) and an output logic network (26) which is configured to perform a logic function on the contents of elements (26) of the memory (22) to generate bits of the code sequence, wherein the code sequence generator (20) outputs a plurality of bits of the code simultaneously.
    Type: Grant
    Filed: July 21, 2008
    Date of Patent: May 22, 2012
    Assignee: Cambridge Silicon Radio Limited
    Inventor: Andrew Papageorgiou
  • Patent number: 8116424
    Abstract: An exemplary shift register includes a plurality of shift register units, each of which includes an output circuit, an input circuit, and a logic circuit. The output circuit includes a clock transistor, a voltage stabilizing transistor, and an input circuit for receiving signals output by a previous shift register unit. The logic circuit receives signals output by the input circuit. When the input circuit outputs signals to switch on the clock transistor, the logic circuit outputs a low level voltage signal to shut off the voltage stabilizing transistor. Thus, the output circuit outputs signals via the clock circuit. On the other hand, when the input circuit outputs signals to shut off the clock transistor, the logic circuit outputs a high level voltage signal to turn on the voltage stabilizing transistor, so as to maintain the output circuit to output low level voltage signal.
    Type: Grant
    Filed: September 15, 2008
    Date of Patent: February 14, 2012
    Assignee: Chimei Innolux Corporation
    Inventors: Chien-Hsueh Chiang, Sz-Hsiao Chen
  • Patent number: 8094117
    Abstract: A display apparatus comprises a shift register array. The shift register array comprises a plurality of shift registers. At least one shift register comprises a first transistor, a second transistor, a third transistor, and a driving circuit. The gate and the first electrode of the first transistor receive an input signal. The gate of the second transistor is coupled to the second electrode of the first transistor. The second electrode of the second transistor generates an output signal. The first electrode of the second transistor receives a clock signal. The third transistor is used to pull down a voltage level at the gate of the second transistor. The driving circuit determines an on/off status of the third transistor in response to the input signal and the output signal.
    Type: Grant
    Filed: September 1, 2010
    Date of Patent: January 10, 2012
    Assignee: Au Optronics Corp.
    Inventors: Chih Yuan Chien, Yu Ju Kuo, Ming Sheng Lai, Kuo Hsing Cheng
  • Patent number: 8031252
    Abstract: A solid-state image-capturing device which has built in an image-capturing area including a light receiving element provided on a semiconductor substrate, a substrate bias circuit, and a clamp circuit for receiving output of the substrate bias circuit and applying the output of the substrate bias circuit to the semiconductor substrate in accordance with a substrate pulse, comprises a substrate bias control circuit for controlling so as to reduce an electric current of the clamp circuit during a predetermined period.
    Type: Grant
    Filed: September 15, 2009
    Date of Patent: October 4, 2011
    Assignee: Sony Corporation
    Inventors: Masahiro Segami, Kenji Nakayama, Isao Hirota
  • Patent number: 8031160
    Abstract: A flat display apparatus comprising a shift register array is provided. The shift register array comprises a plurality of shift registers. At least one of these shift registers comprises a shift register unit, a first TFT, and a second TFT. The shift register unit is configured to receive an activation signal and comprises a first output terminal and a second output terminal. The gate of the first TFT is coupled to the first output terminal. The second electrode of the first TFT receives a clock signal. The gate of the second TFT is coupled to the first electrode of the first TFT. The second electrode of the second TFT is coupled to the second electrode of the first TFT. The first electrode of the second TFT is coupled to the second output terminal.
    Type: Grant
    Filed: July 13, 2007
    Date of Patent: October 4, 2011
    Assignee: AU Optronics Corp.
    Inventors: Jing Ru Chen, Lee Hsun Chang, Shyh-Feng Chen, Chun-Jong Chang, Yung-Tse Cheng
  • Patent number: 7995049
    Abstract: A voltage level shifter formed by single-typed transistors comprises two input terminals, two power supply terminals, a plurality of thin-film transistors, and an output terminal. Another voltage level shifter formed by single-typed transistors comprises two input terminals, an output terminal, two power supply terminals, two input units, a first thin-film transistor, a disable unit, a feedback unit, and a second thin-film transistor. The voltage level shifters are formed by single-typed TFTs. When integrating the voltage level shifters into a substrate of a TFT display, the manufacturing processes are simplified. Besides, power is saved.
    Type: Grant
    Filed: August 1, 2006
    Date of Patent: August 9, 2011
    Assignee: Au Optronics Corp.
    Inventor: Jian-Shen Yu
  • Publication number: 20110191650
    Abstract: The present invention relates to a cyclic shift device, a cyclic shift method, an LDPC decoding device, a television receiver, and a reception system, whereby reduction in size of a device can be realized. With a cyclic shift device 33 including a barrel shifter 61 for performing cyclic shift with M pieces of input data as objects, in the event of cyclically shifting parallel data made up of N pieces of input data smaller than M pieces of input data by shift amount k less than N, a selecting circuit 62 selects and outputs first through N?k'th shift data #1 through #N?k that the barrel shifter 61 outputs, as first through N?k'th output data #1 through #N?k, and selects and outputs N?k+1+(M?N) through N+(M?N)'th shift data #M?k+1 through #M that the barrel shifter 61 outputs, as N?k+1 through N'th output data #N?k+1 through #N. The present invention may be applied to a case for performing cyclic shift.
    Type: Application
    Filed: October 8, 2009
    Publication date: August 4, 2011
    Inventor: Takashi Yokokawa
  • Patent number: 7941435
    Abstract: Techniques are provided for generating a hash value for searching for substrings in a data stream without reading more than one element (e.g. one byte) at a time. According to one technique, a before a next element is added to an old hash value, the old hash value is circularly shifted one or more bits. The first original element is shifted a number of bits and XOR'ed against the old hash value. The next element is added to the old hash value. In one embodiment, an entry value is retrieved for each element from an index table and the XOR and shift operations are performed on the entry values. According to another technique, each Linear Feedback Shift Register (LFSR) of a plurality of LFSRs read in one element at a time beginning at different offsets. Each LFSR uses the same state machine. The result of reading a number of elements into an LFSR is used as the hash value.
    Type: Grant
    Filed: August 1, 2006
    Date of Patent: May 10, 2011
    Assignee: Cisco Technology, Inc.
    Inventors: Jung-Hong Kao, Mete Yilmaz, Jungfu Tsao, Shoujung Jimmy Tsao, Mick Henniger
  • Publication number: 20110103541
    Abstract: A frequency divider having a plurality of programmable latches connected in a feedback shift register configuration. A programmable latch of said plurality of latches comprises a program input to receive a program signal configured to select a polarity of the programmable latch among two opposite polarities. The frequency divider having a configuration module structured to provide at least the program signal to the program input to modify a divisor parameter of the frequency divider.
    Type: Application
    Filed: October 30, 2009
    Publication date: May 5, 2011
    Applicant: STMICROELECTRONICS DESIGN & APPLICATION GMBH
    Inventor: Sebastian Zeller
  • Patent number: 7924259
    Abstract: A display apparatus comprises a shift register array. The shift register array comprises a plurality of shift registers. At least one shift register comprises a first transistor, a second transistor, a third transistor, and a driving circuit. The gate and the first electrode of the first transistor receive an input signal. The gate of the second transistor is coupled to the second electrode of the first transistor. The second electrode of the second transistor generates an output signal. The first electrode of the second transistor receives a clock signal. The third transistor is used to pull down a voltage level at the gate of the second transistor. The driving circuit determines an on/off status of the third transistor in response to the input signal and the output signal.
    Type: Grant
    Filed: March 7, 2007
    Date of Patent: April 12, 2011
    Assignee: Au Optronics Corp.
    Inventors: Chih-Yuan Chien, Yu Ju Kuo, Ming Sheng Lai, Kuo Hsing Cheng
  • Patent number: 7791582
    Abstract: A shift register includes a signal generating circuit for generating an output signal at an output end of the shift register according to a first clock signal while the signal generating circuit is turned on; a driving circuit, electrically coupled to the signal generating circuit, for generating a driving signal to control the signal generating circuit according to an input signal received from an input end of the shift register; a feedback circuit, electrically coupled to a next stage shift register, for transmitting a control signal while the feedback circuit is turned on by the next stage shift register; and a control switch, electrically coupled to the signal generating circuit and the feedback circuit, for turning off the signal generating circuit while the control switch is turned on by the control signal from the feedback circuit.
    Type: Grant
    Filed: May 11, 2006
    Date of Patent: September 7, 2010
    Assignee: AU Optronics Corp.
    Inventors: Lee-Hsun Chang, Yu-Wen Lin, Chun-Ching Wei, Wei-Cheng Lin
  • Patent number: 7734969
    Abstract: Feedback shift register control circuit including a checking circuit having an input being coupled to a seed input of a feedback shift register or to an internal node of the feedback shift register, the checking circuit configured to be responsive to a signal at the input indicating that the feedback shift register is in a not-allowed state, or is going to assume a not-allowed state to output an exception signal; and a gate circuit being coupled to the seed input or the feedback shift register and configured to be responsive to the exception signal to change the state of the feedback shift register or seed the feedback shift register such that the feedback shift register assumes an allowed state.
    Type: Grant
    Filed: October 30, 2007
    Date of Patent: June 8, 2010
    Assignee: Infineon Technologies AG
    Inventors: Rainer Goettfert, Stefan Rueping
  • Patent number: 7697656
    Abstract: It is provided a method of controlling a shift register in which a plurality of transfer unit circuits, each having a storage unit and a writing unit, are connected in series. The storage unit has a hold gate and stores a logical level of a pulse when the hold gate is in an active state, and the writing unit has a writing gate and stores a pulse in the storage unit when the writing gate is in an active state.
    Type: Grant
    Filed: January 3, 2006
    Date of Patent: April 13, 2010
    Assignee: Seiko Epson Corporation
    Inventor: Shigenori Katayama
  • Patent number: 7681097
    Abstract: A test system employing a test controller compressing data, a data compressing circuit and a test method are provided. The test system includes a tester, a device under test (DUT), and a test controller receiving a first clock signal and serial data bits output from the DUT, compressing the serial data bits by m bits (m?4) in response to a second clock signal to generate a signature signal, and outputting the signature signal to the tester. The tester compares a computed signature signal to a 1-bit signature signal to determine whether the DUT is operating poorly or not.
    Type: Grant
    Filed: July 16, 2007
    Date of Patent: March 16, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Hwan-wook Park
  • Publication number: 20100054391
    Abstract: A technique for allowing a linear feedback shift register (LFSR), and particularly a Galois LFSR, to be advanced forward by an amount m (i.e. as if the register had undertaken m input/output cycles), without actually having to undertake m input/output cycles is described. This is useful for example in the communications domain by allowing the shift register to be able to jump to a particular scrambling code. In particular, an embodiment provides an apparatus which is able to control the advance of a LFSR by feeding into the LFSR a data word obtained from the polynomial multiplication of two predetermined data words which are looked up from one or more tables in dependence on an advance amount, being the number of steps the LFSR is to advance. The state of the LFSR after the data word has been fed into the LFSR is then the same state the LFSR would be in if it had actually been advanced by the advance amount.
    Type: Application
    Filed: September 3, 2008
    Publication date: March 4, 2010
    Inventor: Jonathan Graham THACKRAY
  • Publication number: 20100036899
    Abstract: A system comprising a feedback shift-register having L serially connected stages, and a non-linear feedback sub-system to receive input from stage n and 2n+1, and including a first AND gate having a first and second input operationally connected to the output of stage n and 2n+1, respectively, the sub-system having an output based on a value of an output of the first AND gate, a bit generator operative to generate bits, and an XOR gate having a first and second input, an output of the bit generator being operationally connected to the first input of the XOR gate, the output of the sub-system being operationally connected to the second input of the XOR gate, the output of the XOR gate being operationally connected to the input of the first stage of the shift-register. Related apparatus and methods are also described.
    Type: Application
    Filed: June 26, 2008
    Publication date: February 11, 2010
    Inventor: Uri Kaluzhny
  • Publication number: 20090257547
    Abstract: An LFSR module is configured according to a characteristic polynomial for generating an output stream according to an input stream. The LFSR module has several LFSRs coupled together and an output generator. Each LFSR respectively receives a sub-input stream and at least one feedback stream, and respectively generates a sub-output stream and a feedback stream according to the received sub-input stream and the received at least one feedback stream, wherein the sub-input stream is generated according to the input stream, and at least one of the received feedback streams is generated by another LFSR. The output generator generates the output stream according to a plurality of inputs, wherein some of the inputs are the sub-output streams of the LFSRs.
    Type: Application
    Filed: April 11, 2008
    Publication date: October 15, 2009
    Applicant: MEDIATEK INC.
    Inventor: Shang-Nien Tsai
  • Publication number: 20090110137
    Abstract: Feedback shift register control circuit including a checking circuit having an input being coupled to a seed input of a feedback shift register or to an internal node of the feedback shift register, the checking circuit configured to be responsive to a signal at the input indicating that the feedback shift register is in a not-allowed state, or is going to assume a not-allowed state to output an exception signal; and a gate circuit being coupled to the seed input or the feedback shift register and configured to be responsive to the exception signal to change the state of the feedback shift register or seed the feedback shift register such that the feedback shift register assumes an allowed state.
    Type: Application
    Filed: October 30, 2007
    Publication date: April 30, 2009
    Applicant: Infineon Technologies AG
    Inventors: Rainer Goettfert, Stefan Rueping
  • Patent number: 7489758
    Abstract: A shift register apparatus and a shift register thereof are provided. The shift register includes an input unit, a feedback unit, an output unit, and a reset unit. The shift register is made of MOS transistors, BJTs, or other switching transistors. In the present invention, an input signal is registered and shifted through specific couplings between foregoing units with two clock signals having different pulse durations.
    Type: Grant
    Filed: June 6, 2007
    Date of Patent: February 10, 2009
    Assignee: Hannstar Display Corporation
    Inventor: Gen-Chi Lan
  • Patent number: 7450681
    Abstract: A shift register includes a signal generating circuit for generating an output signal at an output end of the shift register in response to a clock signal while the signal generating circuit is turned on, a driving circuit electrically coupled to the signal generating circuit for controlling the signal generating circuit in response to an input signal received from an input end of the shift register, a primary reset circuit electrically coupled to the signal generating circuit for turning off the signal generating circuit and resetting the output signal from the output end, and a feedback circuit electrically coupled to the output end and the major reset circuit for controlling the primary reset circuit in response to the output signal and the clock signal.
    Type: Grant
    Filed: July 10, 2006
    Date of Patent: November 11, 2008
    Assignee: AU Optronics Corp.
    Inventors: Chun-Ching Wei, Wei-Cheng Lin, Shih-Hsun Lo, Yang-En Wu
  • Publication number: 20080253501
    Abstract: A shift register apparatus and a shift register thereof are provided. The shift register includes an input unit, a feedback unit, an output unit, and a reset unit. The shift register is made of MOS transistors, BJTs, or other switching transistors. In the present invention, an input signal is registered and shifted through specific couplings between foregoing units with two clock signals having different pulse durations.
    Type: Application
    Filed: June 6, 2007
    Publication date: October 16, 2008
    Applicant: HANNSTAR DISPLAY CORPORATION
    Inventor: Lan Gen-Chi
  • Publication number: 20080244274
    Abstract: Multi-valued or n-state with n=2p Linear Feedback Shift Registers (LFSRs) in binary form are provided for scramblers, descramblers and sequence generators using addition and multiplication functions over a Finite Field GF(n) in binary form. N-state switching functions in an LFSR are implemented by using implementations of reversible binary functions. LFSRs may be in Fibonacci or in Galois configuration. N-state LFSR based sequence generators in binary form for generating an n-state maximum length sequence in binary form are also provided. A method for simple correlation calculation is provided. Communication systems and data storage systems using the LFSRs are also disclosed.
    Type: Application
    Filed: June 12, 2008
    Publication date: October 2, 2008
    Inventor: Peter Lablans
  • Patent number: 7430268
    Abstract: A disable circuit for using in a dynamic shift register unit comprising: a first input, a second input, an output, a first reference line for receiving a first supply voltage, a second reference line for receiving a second supply voltage, and six transistors. The disable circuit is capable of being coupled with a dynamic shift register unit having an input for receiving an input pulse and an output for outputting a shifted pulse. The disable circuit generates an output signal during an input pulse period or an output pulse period for the dynamic shift register unit, wherein the input pulse period and the output pulse period are responsive to a first input pulsed signal from the first input and a second input pulsed signal from the second input, respectively.
    Type: Grant
    Filed: January 5, 2006
    Date of Patent: September 30, 2008
    Assignee: Au Optronics Corporation
    Inventor: Jian-Shen Yu
  • Patent number: 7184013
    Abstract: A semiconductor circuit system includes a first signal line and n circuit sections (n is an integer equal to or more than 2), each of which has an input terminal and an output terminal. The input terminals of predetermined k ones (k is an integer satisfying 2?k<n) of the n circuit sections are connected to the first signal line, and the output terminal of a m-th one (1?m?n?k) of the n circuit sections is connected to the input terminal of a (m+k)-th one of the n circuit sections.
    Type: Grant
    Filed: June 29, 2001
    Date of Patent: February 27, 2007
    Assignee: NEC Electronics Corporation
    Inventor: Yoshinori Uchiyama
  • Patent number: 7133017
    Abstract: A shift register includes plural stages of flip-flops. The last-stage flip-flop Fn and the flip-flop Fn?1 that is the preceding flip-flop thereof are reset by inputting thereto an output signal from the last-stage flip-flop. A delaying means is provided, between an output terminal Q of the last-stage flip-flop for outputting the output signal and an input terminal R of the last-stage flip-flop for receiving the output signal, for delaying an input of the output signal to the input terminal R. The flip-flop Fn is reset at same time or after the preceding flip-flop Fn?1 is reset. With this arrangement, it is possible to prevent malfunctions of circuits due to a failure to reset the flip-flops.
    Type: Grant
    Filed: March 14, 2003
    Date of Patent: November 7, 2006
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Shunsuke Hayashi, Seijirou Gyouten, Hajime Washio, Eiji Matsuda, Sachio Tsujino, Yuichiro Murakami
  • Patent number: 6785389
    Abstract: A bitstream generator including a plurality of linear feed shift registers (LFSRs) operative to generate a bit stream and including: at least a first LFSR operative, when assigned as a generator during a first time period including at least one clock cycle, to provide an output bit in each clock cycle within the first time period, and at least a second LFSR operative, when assigned as an assignor during the first time period, to provide in each clock cycle an output bit for determining assignments of at least some of the plurality of LFSRs for a second time period following the first time period, the assignments including assignment as a generator, and assignment as an assignor, and a first combiner operative to combine output bits from all of the at least a first LFSR being assigned as generators thereby to produce during each clock cycle a single output bit which is provided to the bit stream. Related apparatus and methods are also provided.
    Type: Grant
    Filed: October 18, 2000
    Date of Patent: August 31, 2004
    Assignee: NDS Limited
    Inventors: Yaron Sella, Aviad Kipnis
  • Patent number: 6778627
    Abstract: A shift-register circuit. The PMOS transistor includes a first gate for receiving an inverted output signal output from a previous stage shift-register unit, a first source for receiving an output signal from the previous stage shift-register unit, and a first drain. The first NMOS transistor includes a second gate coupled to the first drain, a second drain coupled to the clock signal and a second source. The capacitor is coupled between the second gate and the second source. The second NMOS transistor includes a third gate coupled to the first source, a third drain coupled to the second source and a third source coupled to the ground level. The third NMOS transistor includes a fourth gate coupled to an output of a next stage shift-register unit, a fourth drain coupled to a connection point of the second gate and the capacitor and a fourth source coupled to the ground level.
    Type: Grant
    Filed: April 10, 2003
    Date of Patent: August 17, 2004
    Assignee: AU Optronics Corp.
    Inventor: Jian-Shen Yu
  • Patent number: 6771249
    Abstract: A circuit and method for producing a walking one pattern in a shift register. The circuit comprises a shift register and a NOR gate. The NOR gate output is connected to the data input of the shift register, and the data output of each of said register stages is connected to a respective one of the NOR gate inputs.
    Type: Grant
    Filed: June 1, 1999
    Date of Patent: August 3, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Glen Hush, Jake Baker, Tom Voshell
  • Patent number: 6442579
    Abstract: A low power linear feedback shift register includes an ordered set of register steps including memory devices. Enabling devices enable a single current memory device at every shift operation. Each register step includes a lower power memory device consuming a minimum amount of power when disabled, and a feedback device, an output terminal thereof being connected to an input terminal of the memory device, the feedback device having first and second input terminals connected to an output terminal of the memory device and an output terminal of a second subsequent memory device, respectively, in the set. The output terminal of each memory device is connected to a selection device, selecting at every shift operation the output terminal of a first subsequent memory device following the current memory device being enabled at the current shift operation.
    Type: Grant
    Filed: May 13, 1999
    Date of Patent: August 27, 2002
    Assignee: Telefonaktiebolaget LM Ericsson
    Inventor: Mattias Hansson
  • Patent number: 6381295
    Abstract: An apparatus that performs a left shift operation includes a shifter unit that contains the value to be shifted, a flag having an input coupled to the left-most bit of the shifter unit for receiving sign bit information for the value to be shifted, an overflow detector having inputs coupled to the shifter unit and the flag for determining the existence of an overflow condition, and a shift counter having outputs coupled to the shifter unit and the overflow detector.
    Type: Grant
    Filed: April 13, 2001
    Date of Patent: April 30, 2002
    Assignee: Windbond Electronics Corp.
    Inventor: Rehn-Lieh Lin
  • Patent number: 6097889
    Abstract: According to the present invention, an LFSR (300) has a propagation path (30) of serially coupled stages (65) and gates (80-3, 80-4), a feedforward path (10) of gates (80-1) and a feedback path (20) of gates (80-2). Depending on control signals (P, B, M), the gates (80-1, 80-2, 80-3, 80-4) are either active gates and operate as xor-gates or passive gates and operate as transfer gates. Feedforward and feedback signals are derived from input and output signals and can be supplied to any stage (65), so that characteristic polynomials of the input-output function are variable. The LFSR can fully or partly operate as a TYPE 1 or TYPE 2 LFSR which enables the execution of different algorithms on one hardware base.
    Type: Grant
    Filed: June 23, 1997
    Date of Patent: August 1, 2000
    Assignee: Motorola, Inc.
    Inventors: Moshe Tarrab, Eytan Engel, Eli Borowitz, Leonid Belotserkovsky