Abstract: A digital shift register contains a succession of master-slave flipflops (M/S) which are controlled by a clock signal (H), and also comprises, at least between two master-slave flipflops (M/S), a switching device (C) which enables selection of a serial loading mode or a parallel loading mode for the preceding flipflop. The switching device (C) contains a differential stage (Cs) which is used in the serial mode and which is composed of a pair of transistors (T1, T2), and a differential stage (Cp) which is used in the parallel mode and which consists of at least two differential pairs of transistors (T3, T4 and T3', T4') which are connected in parallel, only a part of the transistors of the output branch (T4') being connected to the input of the flipflop which succeeds the switching device, so that saturation of the input transistor (Te) of this flipflop (M/S) in the parallel loading mode is avoided.

Abstract: A system of encoding a plurality of logic paths. A number of logic paths are subdivided into groups of N, N being greater than one. Each group of N logic paths is encoded such that an assertion of a given combination of the N logic paths results in a predetermined one out of 2.sup.N signal lines being asserted. Simultaneous assertion of more than one of the 2.sup.N signal lines is defined as an invalid state. A simultaneous non-assertion of all of the 2.sup.N signal lines enables precharging of the signal lines for dynamic operation. 1-of-2.sup.N encoding enables transmission of N variables by firing one out of N wires (rather than every wire, as in static logic, or one out of two wires, as in mousetrap logic). Signal degradation due to noise and coupling is reduced. In a multiplexer, 1-of-2.sup.N encoding reduces the load on the multiplexer's shift lines. Several 1-of-2.sup.

Abstract: A shift register, circular pointer or ring counter presents a reduced capacitive load on the clock and shift signals used to control it. The device is constructed using one or more enhanced data cells. Each data cell has a data input, a data output, a clock input and a shift input. The data output of each cell is coupled to the data input of an adjacent cell. At least one pass-AND gate is provided for each cell. The pass-AND gate has a switching input and a switched input. The switching input operates to toggle the input capacitance of the switched input between a larger and a smaller value. The logical OR of the data input and data output of each cell is used to drive the switching input of the associated pass-AND gates for that cell. The switched input of the pass-AND gate is adapted to be coupled to the clock (or shift) signal, and the output of the pass-AND gate is coupled to the clock (or shift) input of the data cell.

Abstract: The present invention describes a circuit (10) and associated method of operation for implementing bit reversals and shifts of an input data. The circuit (10) includes a plurality of input lines (12), a plurality of output lines (14), a plurality of shifting transistors (16), a plurality of bit reversal transistors (20), control lines (18) and (22) for each, and a controller (24). The plurality of shifting transistors (16) operably couple the input lines (12) to the output lines (14) such that the controller (24) may selectively operate the shifting transistors (22) to produce shifted outputs of the input data D.sub.0 through D.sub.3 on the output lines (14). The controller (24) selectively operates the bit reversal transistors (20) to produce a bit reversed representation of the input data on the output lines (14). Precharge circuit (30) precharges the output lines (14) so that they may be statically driven. The circuit (10) may include multiplexors (25), (26), and (27) to enable arithmetic shifts.

Abstract: A feedback shift register for generating digital signals representing pseudo-random number sequences has n-stages and exclusive OR-circuits in the feedback logic, as well as a clock-pulse generator. To be able to generate digital signals, which are well suited for a further digital processing, the clock-pulse generator (17) is linked with the n-stages (11, 12, 13, 14, 15) of the shift register (10) via a controllable gate circuit (18), which blocks one clock pulse of 2.sup.n clock pulses (CLK) of the clock-pulse generator (17) in each case.

Abstract: A circuitry with a pseudorandom noise generative function has a shift register for converting serial data into parallel data, an exclusive OR gate electrically connected to the shift register for fetching outputs from the shift register, the exclusive OR gate supplying exclusive ORed data to the shift register for use in generating a pseudorandom noise and a switch electrically connected to a data line transmitting serial digital data to be processed therein and an output of the exclusive OR gate for fetching the digital data and the exclusive ORed data respectively to select the serial digital data or the exclusive ORed data in response to a selective signal, the switch being electrically connected to the shift register for supplying the serial digital data or the exclusive ORed data to the shift register, thereby selecting a normal processing mode for the digital data or a pseudorandom noise generative mode for the exclusive ORed data.

Abstract: A decoding circuit for 2T encoded binary signals, comprises: a data input terminal; a first D-type flip flop having an input coupled to the input terminal; a first exclusive OR gate having inputs coupled to the input terminal and an output of the first D-type flip flop; a shift register having an input coupled to an output of the exclusive OR gate; a second D-type flip flop having an input coupled to the shift register; and, a second exclusive OR gate having inputs coupled to an output of the second D-type flip flop and to a tap of the shift register, the second exclusive OR gate having an output at which decoded input signals are reconstituted. The second D-type flip flop may be a constituent stage of the shift register, the inputs of the second exclusive OR gate being coupled to adjacent taps of the shift register. At least one of the adjacent taps is the output of the constituent stage formed by the second D-type flip flop.

Abstract: A multifunction data storage register is provided having at least one first register cell having a first input multiplexer for selecting between two input signals responsive to one or more control signals and having a first output signal, a first input exclusive not OR circuit having a first input connected to said first output signal of said first input multiplexer and a second input connected to a cell output signal and having a third output signal, a first shift register latch having an input connected to said third output signal of said first input exclusive not OR circuit and having a fourth output signal, a first output exclusive not OR circuit having a first input connected to said fourth output signal of said first shift register latch and a second input connected to a feedback signal and having a fifth output signal, and a first output multiplexer for selecting between said fifth output signal and said fourth output signal responsive to said one or more control signals and having a first cell output

Abstract: A method and apparatus as provided that simplifies the software required for modifying the contents of a register. By adding one gate to the register, a single command can be written to the register to modify the states of multiple bits. The system reduces software overhead significantly when multiple registers must be modified.

Abstract: A self resetting CMOS (SRCMOS) circuit operates with a variable clock cycle. Circuit oscillation is avoided in either long or short clock cycles. At the same time, the circuit eliminates overlapping currents by incorporating a ground interrupt device. The reset generation path is optimized to provide a fast and narrow reset pulse. In addition, the circuit saves power.

Abstract: A emitter coupled logic circuit is reduced in circuit scale, while maintaining the speed of shift registers and compatibility with analog circuits. When data held in the first self-holding circuit section 41 or the second self-holding section 42 is deleted, the threshold voltage VTH applied to the base electrodes of the first and third transistors Q41 and Q43 is set outside the logical amplitude. When data is transferred, also, the threshold voltage VTH is set at a value intermediate to the logical amplitude. Because of this the data held in the first and second self-holding circuit sections can be reliably deleted without an increase in the number of elements.

Abstract: Address pointers (11, 12, 13, 14) include flip-flop circuits and flip-flop circuits including data through circuits. A control circuit (10) controls the flip-flop circuits such that the data through circuits of unnecessary flip-flop circuits cause data to pass through to prevent the flip-flop circuits from selecting unnecessary memory cells (7). The control circuit (10) generates control signals in selection signal producing means including fuses and the like and a decoding portion. Since the decoding portion decodes a flip-flop selection signal, the number of fuses is reduced. This achieves a semiconductor memory comprising address parts for memory cell selection and redundancy circuits which has a reduced area for provision of the fuses for providing redundancy to the semiconductor memory.

Abstract: A driver circuit comprising an output level selection circuit and a shift register is disclosed. The output level selection circuit has driving terminals, potential level input terminals and data input terminals, and an output signal having one of the different potential levels from the driving terminals in response to the data signals. The shift register includes an input terminal, an output terminal, a control terminal, a control circuit, a first shift circuit, and a second shift circuit. The first shift circuit has an input coupled to the input terminal of the shift register and the control circuit, and an output coupled to the control circuit. The second shift circuit has an input coupled to the control circuit and an output coupled to the output terminal of the shift register.

Abstract: A register control circuit has a plurality of registers, a control circuit for producing clock signals, and a logic circuit for producing latch clocks based on a reset signal and the clock signals. A shift data is inputted to a first one of the plurality of registers through a 2-input AND gate. The latch clocks are forced to become active simultaneously under a state in which an input to the first stage register being controlled to "0". The shift register is initialized in such a way that a "0" input is sequentially transferred from the first stage register to the final stage register. The shift register can be formed without the need of registers having reset inputs and initialized speedily, while keeping the increase in the device elements at the minimum.

Abstract: A shift register circuit includes a first two-input NOR circuit to which a first data signal and a selection signal are input, a second two-input NOR circuit to which a first reverse data signal having an opposite phase from the first data signal and the selection signal are input, a third two-input NOR circuit to which a second data signal and a reverse selection signal having an opposite phase from the selection signal are input, a fourth two-input NOR circuit to which a second reverse data signal having an opposite phase from the second data signal and the reverse selection signal are input, a first three-input NOR circuit to which output signals from the first and third two-input NOR circuits and the clock signal are input, and a second three-input NOR circuit to which output signals from the second and fourth two-input NOR circuits and the clock signal are input.

Abstract: A scan flip-flop cell including a flip-flop, a feed-back path by which the output of the flip-flop can be controllably held, and a latch in the feedback path that allows the cell to store two bits of data simultaneously.

Abstract: A phase lock loop operates independent of temperature and process variation by digitally loading a VCO until reaching the desired operating frequency. The VCO reaches a high output frequency even under worst case processing by controlling multiple current mirrors to increase inverter switching current without slowing the response of the VCO to changes in loop node voltage. An Initialize-to-VDD circuit sets the loop node voltage to V.sub.DD so that the load control circuit need only increase loading to slow down the VCO to the desired operating frequency. A frequency range detector monitors the output frequency of the VCO and passes control signals to a load control circuit to activate digital loads and slow down the VCO to the desired operating frequency.

Abstract: The horizontal synchronous signal and the vertical synchronous signal included in a composite synchronous signal which is output from one TV camera are separated from the composite synchronous signal. A plurality of TV cameras are controlled on the basis of the horizontal synchronous signal and the vertical synchronous signal so as to produce synchronized video signals from the plurality of TV cameras. These synchronized video signals are easy to compound. In the blanking period of the vertical synchronous signal, the rise period of the synchronous signal is 1/2 of the period of the vertical synchronous signal. Pulses are eliminated alternately in the blanking period by a half killer circuit including a counter and a decoder and having a simple structure, thereby generating a horizontal synchronous signal appropriate for driving the TV cameras.

Abstract: The input nodes and output nodes of a plurality of storing circuits for storing plural-bit data are connected to one another to constitute a shift register. Each of the plurality of storing circuits includes a selection circuit for selecting 1-bit data from the plural-bit data according to a selection signal, a first latch circuit for latching the 1-bit data selected by the selection circuit in synchronism with a first clock signal, and a number of second latch circuits, which number corresponds to the number of bits of input data, for latching an output of the first latch circuit in synchronism with a plurality of second clock signals having phases different from that of the first clock signal. Data sequentially selected by the selection circuit is latched into the first latch circuit and then sequentially latched into the second latch circuit in a time-sharing fashion.

Abstract: A data link controller receiver is disclosed that includes a series of shift registers and a bit counter that counts the number of received bits. When an end of frame character is received, the value in the bit counter which represents the bit residue is supplied to a bit adjustment counter. The bit adjustment counter is employed to control the operation of the shift register containing the bit residue during a byte adjust operation, in a manner which enables the shift register containing the bit residue to be clocked until the value in the bit adjustment counter is indicative of the number of bits in a defined byte. Accordingly, the bit residue is serially shifted until the least significant bit of the shift register is filled. In addition, a mechanism is provided for loading zeros into the shift register during the byte adjust operation.

Abstract: A system for masking bits in a configuration. The system has a bus with first and second sets of bit lines. A line from the first set is paired with aline from the second set; the paried lines are coupled to each cell in the configuration register. A logic circuit is connected to each register cell and the corresponding paired lines. Depending upon the state of the bit signal of the second set bit line, the logic circuit passes the bit signal on the first set bit line for loading into the register cell or reloads the bit line signal already in the register cell. In this manner, masking operations in the configuration register can be performed very quickly.

Abstract: The present invention discloses a method of simulating the state of a TYPE I Linear Feedback Shift Register (LFSR) with information available as a result of a TYPE II LFSR implementation. This is accomplished by clocking a TYPE II LFSR to produce an output sequence. This sequence, or at least a portion thereof, is then stored in a storage medium, such as, for example, a shift register. Cascading a TYPE II LFSR output sequence into a shift register of length N, where N is the number of stages employed by the TYPE II LFSR, is the exact equivalent of a TYPE I LFSR. Accordingly, the shift register's contents will contain data corresponding to the state of a TYPE I LFSR.

Abstract: A serial access memory circuit provided with an improved serial addressing circuit which can be fabricated with a reduced number of elements, is disclosed. The memory circuit comprises a memory array of N columns to be serially accessed, and a serial selection circuit including a shift register of N/K stages, a control circuit generating K output signals and a gate circuit receiving output signals of N/K stages of the shift register and K output signals of the control circuit and generating N output signals.

Abstract: A register is disclosed in which an applied data signal D or its complement D is used to set or reset an output RS flip-flop under control of an applied load control signal L. The load control signal is applied to a switching circuit which controls application of the data signal D or D to the set or reset input of the output flip-flop such that the data signal is only applied for a time period sufficient to cause a change in state of the output flip-flop.

Abstract: In the present invention, a reprogrammable control circuit is disclosed. The reprogrammable control circuit comprises a single-bit register for serially receiving an input bit signal and providing a control signal. The control signal represents the state of the bit stored in the register. A transmission gate means receives the control signal from the single-bit shift register and an input signal and provides an output signal therefrom. The control signal of the bit shift register is used to control the transmission of the input signal to the output signal. A plurality of reprogrammable control circuit which comprises a plurality of bit shift registers, each having a transmission gate means associated therewith is also disclosed. The reprogrammable control circuit can be used in an improved PLA, improved RAM, improved RCIM, improved ALU, improved counter, improved CAM, PCN to improve the reliability of routing signals and power, and to preserve the states of flip-flops.

Abstract: A digital sequencing apparatus produces a series of contiguous enable gates or strobe signals. The apparatus includes an even number, and at least two alternating stages of cross-coupling NOR gates alternating with cross-coupled NAND gates where one of the cross-coupled NOR gates in each stage has a merged AND gate at one input and one of the NAND gates in each stage has a cross-coupled OR gate at one input. This apparatus produces contiguous enable gates in response to complementary clock inputs to each of the stages upon the input of a start signal to the first two stages of the apparatus.

Abstract: A semiconductor integrated circuit comprises a three-valued logic circuit connected to receive an output signal of a logic circuit to receive at one input a control clock signal and at the other input an input signal, and a flip-flop circuit composed of a clocked inverter to receive the output signal of the three-valued logic circuit, and another inverter.

Abstract: A drive circuit for producing scanning pulses to successively select row or column conductors of a matrix display device of the type having an active element provided for each display element in the matrix, the drive circuit comprising a shift register made up of a set of cascade-connected master-slave flip-flops, with both the master outputs and the "slave" outputs being utilized to form the scanning pulses. The number of flip-flop stages required is reduced by 1/2, by comparison with prior art drive circuits using master-slave flip-flops, and the frequency of the clock pulse signal required to drive the shift register is 1/2 of that required in the case of a prior art circuit.

Abstract: A logic circuit having a test data loading function, comprising at least one J-K flip-flop. Each J-K flip-flop includes a test data latching logic circuit. In response to an enable signal, test data is selected in place of the usual J and K input data to be latched. In a complex logic circuit including such flip-flops, a test can be effected in a short time.

Abstract: A shift register stage (20) for LSI and VLSI circuits is disclosed and includes a first latching circuit (21) responsive to a data input and for providing a first data output; control circuitry (23) responsive to the first data output and to a parallel data input for providing as a controlled data output a replica of the first data output or a replica of the parallel data input as a function of a control signal; a second latching circuit (25) responsive to the controlled data output and for providing a second data output; and a third latching circuit (27) responsive to the second data output and for providing a third data output. Also disclosed is a shift register (30) for LSI and VLSI circuits which advantageously utilizes the foregoing shift register stage of the invention and which provides for AC or delay testing of an integrated circuit which includes two of such shift registers (30, 60) and a logic network (50) interposed therebetween.

Abstract: A serial-to-parallel converter receiving a clock signal and continuous serial stream of input data, each having TTL logic levels, produces parallel outputs for driving current switches of a digital-to-analog converter (DAC). The data and clock signals each are converted to ECL logic levels by a pair of emitter-coupled differential lateral PNP transistors having their collectors coupled to a pair of NPN current mirror circuits, the outputs of which drive the bases and emitters of a pair of NPN emitter follower transistors, resulting in very high bandwidth operation. Master-slave ECL shift register bit outputs are directly coupled, without emitter followers, to ECL inputs of output latches that drive the DAC current switches, resulting in substantially reduced power consumption and chip area.

Abstract: A serial input/output device includes a CMOS shift register having a plurality of D-type flip-flops. A detection circuit is associated with the CMOS shift register in order to detect whether the transfer data exists in the CMOS shift register. A gate circuit is provided for applying a transfer clock signal to the CMOS shift register only when the transfer data exists in the CMOS shift register, thereby minimizing the power consumption.

Abstract: A variable frequency divider which includes a feedback shift register having a feedback gate of NOR type, a delay shift register for delaying output data from the feedback shift register by one clock, a control shift register having a control gate of AND type, a feedback circuit for feeding output data from the delay shift register and from the control shift register back to the feedback gate, and an expander which receives output data from the feedback shift register and produces a control signal according to said frequency dividing input and a frequency division ratio instruction signal. The control gate receives output data from the delay shift register and the control signal.

Abstract: A CMOS LSI or VLSI integrated circuit chip includes a shift register circuit that provides internal delay testing capability. The shift register circuit is disposed around the periphery of the chip and includes a large number of serially connected stages. One mode of operation allows a data signal to pass through the shift register circuit at a speed limited only by the propagation delays associated with the individual stages thereof. In this mode of operation, one net inversion is introduced into the data path and the output of a final stage of the shift register circuit is coupled to the input of a first stage of the shift register circuit, thereby creating a ring oscillator. The period of oscillation of this ring oscillator represents a measure of the average propagation delay times associated with the various circuit elements employed within the LSI or VLSI circuitry. Such delay measurements can readily be made at any level of packaging or system operation.

Abstract: A pulse detection circuit, is used for detecting pulses contained in output signals derived from an encoder. An encoder, such as rotary encoder, converts a physical quantity like spatial position, displacement or length into an electric signal. This detection circuit achieves high definition in terms of the rotational angle of the encoder shaft. It does so by positively utilizing four different combinations of modes, obtained for one period of the encoder output signals, which had hitherto been treated in one count. It thereby avoids erroneous counting of the pulses contained in the encoder output signals, even if chatterings are incidentally included in the encoder output signals and if the phase relation between the two signals is temporarily inverted. The circuit thus performs pulse detection with a very high accuracy.

Abstract: A shift register circuit for converting a form of a datum with N bits comprises a shift register with a bit capacity of at least N+1 bits. Each bit of the shift register is set so as to become a predetermined logic condition by a setting means. At this time, the supply of shift pulses to the shift register is begun, so that the data in the shift register is shifted and predetermined data are input in sequence. A detecting means detects whether or not the shift register has carried out the shift operations by the predetermined times on the basis of the logical condition of the predetermined bit or bits in the shift register. When the detecting means detects that the shift operations have been carried out by the predetermined times, the supply of the shift pulses to the shift register is stopped. This shift register circuit can be used for a parallel to serial converter or a serial to parallel converter.

Abstract: A register circuit which is used to asynchronously monitor any data or logical function (or functions) and be able to retain the status of the monitoring until the register is interrogated whereupon the register is automatically reset and able to receive or monitor another status signal.

Abstract: A logical circuit which is capable of serving not only as a shift register but also as counter, comprises a cascade-connection of flip-flops of the same number as the number of bits required. The flip-flops have an input connected to a logical gate group composed of gates which are opened and closed by a shift signal and a count signal. The logical circuit does not require that a flip-flop be included for each shift register part and counter part for each bit, but only requires one flip-flop to perform both the count and shift function. The logical circuit is capable of performing an independent operation of a shift register, an independent operation of a counter and a compound operation of inputting data in a serial fashion for initialization and outputting counted data in a serial fashion.

Abstract: In utilizing frequency dividers at high frequencies the maximum operating frequency is determined by the delay time through the frequency divider. To minimize this delay time, a digital frequency divider is provided having a binary counter constructed of flip-flops and a shift register coupled to the output of said counter, wherein the output state of the shift register is forcibly reduced to a low level in response to a control signal for varying the number of frequency division of said counter. A circuit is also provided for feeding the input terminal of the flip-flop at the first stage of said counter with an OR output made up of the outputs of said shift register and said counter. Thus, the digital frequency divider can operate at a speed which is limited only by the toggle frequency of said flip-flop circuits.

Abstract: A general purpose retiming circuit comprising a timing signal source for generating timing signals, a plurality of N registers arranged in a row in a given order with each register having an input terminal, an output terminal, and clock input terminal and responsive to timing signals supplied thereto to transfer the signal supplied to said input terminal means to said output terminal. There is provided a serial input terminal for supplying a serial input signal thereto. Also provided are N switches arranged in the given order and each having first and second input terminals and an output terminal which is connected to the input terminal of a corresponding register of said row of N registers, and with the first input terminal of a first of the N switches being connected to the serial input terminal and the first input terminal of each of the remainder of the N switches being connected to the output terminal of the register preceding the corresponding register in the row of registers.

Abstract: A high speed shift register device includes first and second shift registers. Odd numbered bits of a word are stored in the first shift register and even numbered bits of the word are stored in the second shift register. The first shift register is clocked by a clock signal, and the second shift register is clocked by the complement of the clock signal. The outputs of the first and second shift registers are alternately shifted by means of a multiplexer to an output conductor. A control input of the multiplexer is connected to the clock input. Data is shifted out of the multiplexer at a rate which is twice the normal shifting rate of each of the first and second shift registers.