Abstract: A parallel-serial converter comprises a plurality of selection-delay unit circuits. The unit circuit selectively receives an output signal from the immediately preceding unit circuit and one of a plurality of input parallel signals and shifts the selectively received signal to the immediately succeeding unit circuit. The selection-delay unit circuit is only formed of three transfer gates and two inverters in order to reduce a chip size and save power consumption.

Abstract: A storage register which may be used to store several sets of data. The storage register may also be used as a demultiplexer to separate two or more sets of data that were received by the register over a single data line. The storage register includes a closed circuit loop of pairs of field effect devices and pairs of clocking devices wherein the clocking devices are coupled between the field effect devices. Input and output terminals are coupled to selected field effect devices. Embodiments of this storage register permit several bits of information to be stored simultaneously in the closed circuit loop and still remain accessible to input and output terminals at different times controlled by the clocking means. A further embodiment provides for several closed circuit loops to be arranged for the parallel storage of data bits.