Abstract: A clock control device and method are provided. The clock control device includes a stable time controller which receives an operational condition and generates an expiration counting value based on the operational condition; a stable time counter which receives the expiration counting value and activates a clock gating enable signal after a count value of the stable time counter is equal to the expiration counting value; a clock gating cell which transmits a clock signal after receiving the clock gating enable signal; and an oscillator which generates an oscillator clock signal and transmits the oscillator clock signal to the clock gating cell and the stable time counter.

Abstract: System, methods and apparatus are described that facilitate data communications using a single-ended communication link. A method for data communications includes decoupling a direct current component from an alternating current component of a single-ended input signal, biasing the alternating current component with a predetermined bias voltage to obtain a realigned signal, and providing a digital output representative of the input signal by comparing the realigned signal with the predetermined bias voltage. The realigned signal can be compared with the predetermined bias voltage using hysteresis comparison to provide an output signal that switches between logic states compatible with a logic circuit.

Abstract: A circuit may include a source of electrical energy and a plurality of current loads. Each load may be of a different amount. For each current load, a resistance may be in series between the source and the current load. The resistance may be weighted inversely proportional to the amount of the current load with respect to the other resistances. For each resistance, an integrator may generate an integrated output representative of an integration of the current traveling through the resistance. A summer may generate a summed output which is representative of the sum of each of the integrated outputs, weighted inversely proportional to the resistance that is associated with the integrated output.

Abstract: An electronic control circuit for a voltage variable capacitor, the electronic control circuit comprising a plurality of voltage variable capacitors, a plurality of resistors, and a plurality of variable electrical power sources wherein the plurality of voltage variable capacitors, the plurality of resistors, and the plurality of variable electrical power sources are electrically interconnected to form an electronic bias circuit for adjusting a capacitance of the plurality of voltage variable capacitors.

Abstract: A clock stability circuit (10, 20, 30, 40) assures stable clock generator operation after oscillator start-up, such as during re-entry after a low-power Halt mode in a microprocessor or microcomputer. The clock stability circuit detects stable clock cycles that transition between a selected high amplitude threshold (near VDD) and a selected low amplitude threshold (near VSS), and provides a clock stable signal after a selected number of stable clock cycles, indicating that the oscillator has stabilized. The clock stability circuit includes four modules: input sampler (10), pulse generator (20), pulse counter (30) and control logic (40). The input sampler module includes CMOS NAND gates (11, 14) respectively fabricated with p/n-channel ratios to provide a CLOCK A signal that transitions at the selected high amplitude threshold of an oscillator cycle, and a CLOCK B signal that transitions at the selected low amplitude threshold.

Abstract: The use of a comparator and counter associated, on-chip, with each photo-element of an array. Sensing each photo-element without discharging it and allowing each photo-element to accumulate a charge which is large relative to noise variations. These features result in a photo-detector with large signal-to-noise ratios.

Abstract: To permit address-free fault location on digital communication paths with several intermediate repeaters, one or more identification signals must be recognized in the intermediate repeaters with sufficient certainty. The identification signals are digital signals with periodically recurring sections which are marked with a string of successive like bits (e.g., 0 bits) and have different durations for a first identification signal and a second identification signal.The circuit contains a time discriminator (1) which responds when a string of successively received like bits is characteristic of a section of an identification signal. It then provides a pulse equal in length to this section to a frequency discriminator (2) which responds when such pulses recur at a frequency characteristic of an identification signal. The frequency discriminator thus delivers an output voltage whose amplitude is typical of one identification signal or the other because of the different pulse durations.