Abstract: A currency bill processing device for counting, denominating, discriminating, and/or sorting the currency bills and subsequently disinfecting the currency bills without any manual intervention. The currency bill processing device can process the currency bills at a speed of up to 1000 bills per minute. The currency bill processing device includes one or more elongated UV-C LED strips mounted on a rigid aluminum or copper base which can be mounted on an outer or exposed side of a support plate or reject receptacle plate or stacker guide bar plate located at the end of the currency bill conveying path. A disinfection unit of the currency bill processing device including the elongated UV-C LED strip that can activate and deactivate with turning-on and -off of the currency bill conveying mechanism respectively.

Abstract: A battery powered device is able to maintain a clock value when the battery is removed for a short period. During a first time period, while the battery is in the device, clock pulses derived from a first oscillator are counted at a first rate in a first counter that represents the clock value. During a second time period following the first time period, while the battery is removed, the value of the first counter is maintained independent of any clock pulses derived from the first oscillator, clock pulses derived from a second low power oscillator are counted in a second counter. During a recovery time period following the second time period, clock pulses derived from the second oscillator are again counted in the second counter, while clock pulses derived from the first oscillator are counted in the first counter at a second rate higher than the first rate, the duration of the recovery time period being determined based on the number of pulses counted in the second counter during the second time period.

Abstract: An analog counter includes, for at least one step, an input for receiving electric pulses and a means for modifying, by consecutive increments or decrements, a storage voltage for each received electrical pulse, a means for resetting the storage voltage, and a comparator for comparing the storage voltage with a threshold voltage and adapted to generate exceedance information. The counter further includes a control means adapted to control the resetting means in the event of the simultaneous detection of exceedance information from the comparator and of an input pulse.

Abstract: A counter circuit for an analog to digital converter includes: a plurality of counter stages configured to obtain an integer multiple of a digital gain for the analog to digital converter by bypassing at least one of the plurality of counter stages. An analog-to-digital converter includes at least one counter circuit, and an image sensor includes the analog-to-digital converter, which includes the counter circuit.

Abstract: Disclosed is a semiconductor integrated circuit for generating a frequency division clock signal that approximates a desired clock signal without increasing a size thereof. The semiconductor integrated circuit masks, for each programmable cycle, a clock signal to be supplied to a transmission clock generation unit 100, thereby delaying a counting operation of a clock counter 101, and setting a timing for extending a transmission clock signal so as to cause a transmission rate of an average frequency of the transmission clock signal to approximate a predetermined transmission rate, wherein the transmission clock generation unit 100 divides a frequency of a clock source signal S301 that is a high-speed clock signal.

Abstract: A high performance, low power up/down counter is set forth. The counter presented is controlled by two clock pulses, an up pulse and a down pulse, and updates all bits of the counter in parallel. These bits are then latched using a scannable pulsed limited output switching dynamic logic latch. By using a limited switch dynamic logic latch, the counter is able to utilize the speed of dynamic logic without requiring the traditional dynamic logic power. The area saved and speed gained by using a dynamic latch is significant compared to a typical edge-triggered flip-flop. Additionally, by computing all the next count state bits in parallel, the counter reduces an overall count computation delay by eliminating the counter ripple.

Abstract: The invention concerns counting circuitry for providing a corrected count value based on the number of rising and falling edges of an input signal occurring during a reference time period, the counting circuitry comprising a counter (22) arranged to provide a first count value based on one of the number of said rising edges of said input signal occurring during said reference time period, and the number of said falling edges of said input signal occurring during said reference time period; characterized in that said counting circuitry further comprises adjustment circuitry (24-26) arranged to generate a corrected count value by determining the state of said input signal at the start time (70) and end time (72) of said reference time period, and adjusting said first count value if the state of said input signal at the start of said reference time period is different from the state of said input signal at the end of said reference time period.

Abstract: A high performance, low power up/down counter is set forth. The counter presented is controlled by two clock pulses, an up pulse and a down pulse, and updates all bits of the counter in parallel. These bits are then latched using a scannable pulsed limited output switching dynamic logic latch. By using a limited switch dynamic logic latch, the counter is able to utilize the speed of dynamic logic without requiring the traditional dynamic logic power. The area saved and speed gained by using a dynamic latch is significant compared to a typical edge-triggered flip-flop. Additionally, by computing all the next count state bits in parallel, the counter reduces an overall count computation delay by eliminating the counter ripple.

Abstract: An LCD counter assembly including a housing that houses an LCD display at a first end and a printed circuit board (PCB) assembly at a second end opposite the first end. A diffuser is intermediate the PCB assembly and the LCD display, the LCD display and the PCB assembly in electrical contact with a connector that provides electrical signals from the PCB assembly to the LCD. The first end of the housing includes an aperture through which the LCD display is readily visible to an observer. The PCB assembly may include a backlight to improve the visibility of the LCD display. The PCB assembly further includes a PCB having a printed circuit and a plurality of pads, a single piece, double beam, activation and trigger switch combination assembled to the board, the board configured to receive the double beam activation and trigger switch combination and a removable tab to separate the activation switch in the double beam combination from one of the plurality of pads.

Abstract: A counter that outputs a counting signal having a random counting value. The counter includes a clock generator and a counting circuit. The clock generator generates first and second clock signals with different phases based on an input clock signal. The counting circuit executes a counting operation and outputs a counting signal having a random counting value, in response to the first and second clock signals. The counter can output a counting signal having a random counting value. Accordingly, semiconductor devices to which the counter is applied can execute a variety of operations.

Abstract: Provided is a counting circuit for controlling an off-chip driver and method of changing a DC output current value of the off-chip driver using the same in accordance with variations of processing characteristics with PMOS and NMOS in the state of wafer level. The counting circuit for controlling the off-chip driver includes: pluralities of latch circuits counting to generate pluralities of off-chip driving control signals; pluralities of fuse blocks generating set and reset input signals to vary initial values of the off-chip driving control signals; and pluralities of initial value modifying circuit varying the initial value of the off-chip driving control signals in response to the set and reset input signals.

Abstract: The present invention relates to an integrated circuit comprising a first clock circuit delivering a first clock signal, a second clock circuit delivering a second clock signal, a first counting circuit for delivering a time base signal using a clock signal and a counting value, and means for applying the first clock signal and a first counting value to the first counting circuit, so as to produce a first time base signal. According to the present invention, the integrated circuit comprises means for producing a second time base signal using the second clock signal and a second counting value, and means for calibrating the second counting value such that it is equal or proportional to the number of periods of the second clock signal occurring during a determined time interval equal to a period or to a whole number of periods of the first time base signal. Application particularly to the management of a timer in a microprocessor.

Abstract: An integrated circuit device having an output driver circuit and a control circuit. The output driver circuit outputs a first signal having a signal level according to a control value. The control circuit is coupled to receive the first signal from the output driver and adjusts the control value by a first increment until a transition event is detected. After the transition event is detected, the control circuit adjusts the control value by a second increment, the second increment being smaller than the first increment.

Abstract: A state machine, a counter, and related method for gating redundant triggering clocks according to the initial states is provided. The state machine includes a plurality of state units and a clock gating circuit. Each of the state unit is triggered by a clock to generate a corresponding varying state, and the clock gating circuit is capable of selectively withholding a triggering clock to at least one state unit according only to an initial state, such that the selected state unit(s) will not be triggered by the triggering clock while the rest of the state units are triggered by the triggering clock to update their corresponding states.

Abstract: When a PWM signal is generated by PWM generators which are provided for the number of channels, each PWM generator outputs the PWM start schedule data showing the timing of startup of the PWM signal to the CPU. When the number of PWM signals which start at substantially the same time exceeds a predetermined number on the basis of the PWM start schedule data, the CPU outputs delay setting data with respect to a channel corresponding to a portion exceeding the predetermined number to the PWM generator as the one showing that the generation of the PWM signal is to be delayed. The PWM generator delays the PWM signal, when the delay setting data shows a delay. As a result, a multi-channel pulse width modulation apparatus which can prevent a decrease in the operational reliability due to simultaneous start of the pulse width modulation signals can be provided.

Abstract: A multi-bit counter of the present invention is capable of high-speed operation because the time needed for increasing count values and combining count bits for a carry can be minimized by presetting all bit combinations for a unit having multiple bits and selecting the preset combinations by a clock signal, i.e., by presetting the state of each of the bit combinations and outputting a next required value.

Abstract: A synchronous counter, the inventive counter is synchronized to a clock, e.g., a master clock of an FPGA, and includes a first counter that increments in response to the master clock, a resynchronizer that receives counter bits from the first counter and, when appropriate, generates an increment signal, and a second counter, clocked by the master clock, that increments in response to the increment signal. In a preferred embodiment, the resynchronizer is an n bit AND gate (where the first counter is an n-bit counter) that ANDs at least selected ones of the counter bits and a latch, e.g., a flip-flop, that latches the output of the AND gate. Thus, small counter chains are linked together using flip-flops clocked at the master clock rate, i.e., the same rate as the counter chains, to form a counter chain of any length that will function at the master clock rate.

Abstract: A serial data receiving device comprises a first memory means for storing serial data while shifting the data bit by bit whenever receiving each one bit of the data and converting the serial data into parallel data when all the bits constituting the serial data are stored; a first detecting means for detecting the storage of all the bits constituting the serial data in the first memory means, a second memory means for storing a signal allowing the serial data to be received in accordance with the detection result by the first detecting means, and a first control means for controlling the reception of the serial data (outputting a hand-shake signal or transfer clock, for example) in accordance with the stored contents in the second memory means. A serial data transfer apparatus is equipped with the serial data receiving device, wherein the receiving device controls the transfer of the serial data.

Abstract: A counting circuit including destructive memory elements detection circuits for detecting whether the memory elements are broken, and control circuits for controlling the supply of a break current to the memory elements in a plurality of stages. A current feed circuit supplies the break current for breaking the memory elements in the counting circuit every time a to-be-counted write pulse is input. The control circuit in each stage of the counting circuit supplies the break current from the current feed circuit to the memory element of the stage based on a detection result of the detection circuit only when the memory element of the stage is unbroken while the memory element of a stage preceding the memory element is broken. The control circuit of the first stage supplies the break current to the memory element of the first stage when the memory element of the first stage is unbroken.

Abstract: A logic circuit provides increment functions +1 and +2 and decrement functions -1 and -2.

Abstract: A counter circuit converts a full count to a zero count and a zero count to a full count. An incrementing counter circuit according to the present invention has a plurality of threshold circuits with stepwise thresholds. An output of the highest threshold circuit is used as a cut off signal for other threshold circuits. A decrementing counter circuit according to the present invention has a plurality of threshold circuits from the lowest threshold to the highest thresholds. An output of the lowest threshold circuit is used as a closing signal for other threshold circuits.

Abstract: A clock stability circuit (10, 20, 30, 40) assures stable clock generator operation after oscillator start-up, such as during re-entry after a low-power Halt mode in a microprocessor or microcomputer. The clock stability circuit detects stable clock cycles that transition between a selected high amplitude threshold (near VDD) and a selected low amplitude threshold (near VSS), and provides a clock stable signal after a selected number of stable clock cycles, indicating that the oscillator has stabilized. The clock stability circuit includes four modules: input sampler (10), pulse generator (20), pulse counter (30) and control logic (40). The input sampler module includes CMOS NAND gates (11, 14) respectively fabricated with p/n-channel ratios to provide a CLOCK A signal that transitions at the selected high amplitude threshold of an oscillator cycle, and a CLOCK B signal that transitions at the selected low amplitude threshold.

Abstract: A signal generator which may be fabricated as monolithic integrated circuit is disclosed. The signal generator includes a counter having a plurality of stages and providing parallel outputs and a plurality of flip-flops. A programmable logic array capable of functioning as AND and OR logic and composed of a matrix arrangement of programmable elements receives as inputs the parallel outputs of the counter and provides inputs to the flip-flops to generate signals at the outputs of the flip-flops.

Abstract: Subharmonics of a data waveform are generated for the purpose of reducing ta bandwidth prior to transmission. Input data waveform is phase split and the antiphased output signals are fed to a rectifier. The rectification of antiphased signals creates two pulsating voltage with opposite polarity. The pulsating voltages are alternately switched by a chopper to provide a sinusoidal signal. The sinusoidal signal is filtered to average the energy of the pulsating voltage to provide a smooth waveform of one-half the frequency of the input data waveform.