Devices Having More Than Two Stable States Patents (Class 377/98)
  • Patent number: 7463547
    Abstract: A microcomputer includes a circuit block; a nonvolatile memory configured to store optimization data for optimization of an operation of the microcomputer; and an optimization circuit configured to read out memory optimization data as a part of the optimization data from the nonvolatile memory in synchronization with a first frequency clock signal as an first clock signal to optimize an operation of the nonvolatile memory, and then to read out circuit block optimization data as another part of the optimization data from the nonvolatile memory in synchronization with a second frequency clock signal as the first clock signal to optimize an operation of the circuit block. The frequency of the first frequency clock signal is lower than that of the second frequency clock signal.
    Type: Grant
    Filed: January 26, 2006
    Date of Patent: December 9, 2008
    Assignee: NEC Electronics Corporation
    Inventors: Shinichi Nakatsu, Hideo Isogai, Takehiro Masumoto, Kazuyuki Nishizawa, Toshihide Tsuboi, Kimiharu Etou
  • Patent number: 5237596
    Abstract: A stepping counter using resonant tunneling diodes (RTDs). The stepping counter utilizes the periodic hysteresis characteristic of a device with folding characteristics such as a RTD connected in series with a resistance. The series circuit is biased in the upper portion of the hysteresis loop through a current source in the case of a step-up counter. When a positive-going pulse is applied through a capacitor across the series RTD-resistor circuit, the operating point jumps to the next highest stable operating point in the hysteresis loop responsive to the leading edge of the pulse, but is prevented from returning to the original operating point at the trailing edge of the pulse because of the hysteresis.
    Type: Grant
    Filed: October 8, 1991
    Date of Patent: August 17, 1993
    Assignee: University of Maryland
    Inventor: Hung C. Lin
  • Patent number: 5033069
    Abstract: The disclosure is directed to an electronic circuit and method for counting input electrical signals. An embodiment of the method of the invention includes the following steps: providing a device having a current versus voltage characteristic with a plurality of peaks, and negative resistance regions between the peaks; generating a triggering pulse in response to each input signal to be counted, and applying said triggering pulse to the device to change the voltage across the device; and outputting the voltage across the device as an indication of the number of received input signals. The device may be a resonant tunneling diode with multiple peaks in its current versus voltage characteristic. The preferred embodiment of the method of the invention includes the step of providing a load resistance means across the device. In this embodiment, the triggering pulse is operative to change the voltage across the device to a stable operating point of the device in conjunction with the load resistance means.
    Type: Grant
    Filed: August 8, 1989
    Date of Patent: July 16, 1991
    Assignee: University of Maryland at College Park
    Inventors: Hung C. Lin, Tai-Haur Kuo
  • Patent number: 4990796
    Abstract: Disclosed is a circuit which provides the controlled generation of tri-level digital signals utilizing Field Effect Transistors (FETs), as active elements. The stability of all three states is due to a unique feed-back technique, and utilization of the gate threshold characteristics of FETs. This circuit is controllable with either bi-level or tri-level digital signals, and is externally configurable as: a ternary up counter, providing the count sequence of 0,1,2,0 . . . ; a ternary down counter, providing the count sequence of 2,1,0,2 . . . ; a ternary shift left/right register; or as a ternary memory.
    Type: Grant
    Filed: May 3, 1989
    Date of Patent: February 5, 1991
    Inventor: Edgar D. Olson