Abstract: A network control arrangement where two or more path hunt operations are performed in parallel using one or both of two techniques: (1) reading a memory for a second path hunt operation during the time that information read from the memory for a first path hunt operation is being processed to select a path, and (2) maintaining duplicate memories and reading from them both to perform two path hunt operations before either memory is updated. A disjoint path check unit rapidly determines whether all of the network paths from a first inlet to a first outlet are disjoint from all of the network paths from a second inlet to a second outlet. Plural path hunts are performed only when all network paths from the first inlet to the first outlet are determined to be disjoint from all network paths from the second inlet to the second outlet.

Abstract: The invention provides a crosspoint switching system (30) comprising a plurality of switching planes for transferring data therethrough. The switching planes are comprised of two types, data planes (32) used only for transferring data between processors and at least one control/data plane (34) capable of transferring data and controlling crosspoints in the other data planes. The switching system is operable with two protocols, a message-switched mode in which only the control/data plane is used for transfer of data and a circuit-switched mode in which the control/data plane and the other data planes are used for transfer of data.

Abstract: A switching network where a large class of combinatorial designs which are well known in the mathematical literature are for the first time applied to advantageously define the pattern of permanent connections effected between network input channels and initial network crosspoints, illustratively by a connection arrangement of a two-stage, rearrangeable network. The class of combinatorial designs comprises designs of three types: (1) block designs, (2) orthogonal arrays, and (3) difference sets. Each of these is used in a unique manner to derive an advantageous pattern of permanent connections.

Abstract: A switching component preferably in integrated circuit form is provided. The switching component has a plurality of inlet and outlet data ports with associated inlet and outlet clock ports, a clock regenerator and a flip-flop for each outlet data port, and a switch matrix for coupling each inlet data port and its associated inlet clock port to any outlet data port and its associated outlet clock port. The clock regeneration means obtains the clock signal exiting the switching core and regenerates the clock signal waveshape. The flip-flop causes data exiting the switching core to be clocked out of the switching component synchronously with its associated regenerated clock signal according to the regenerated clock signal. A plurality of identical switching components can be arranged in a folded Clos arrangement having a plurality of stages to provide a desired switch network of any size.

Abstract: The invention comprises an improved cross-connect switch constructed from a plurality of switch modules for connecting input lines to output lines. The improved switch includes a switch module replacement system that allows a craftsperson to replace a switch module without interrupting connections between cross-connect switch input and output lines that utilize switch points in the switch module in question.

Abstract: The invention comprises an improved cross-connect switch constructed from a plurality of switch modules for connecting input lines to output lines. The improved switch includes a test access system in which selected input or output lines of the cross-connect switch are utilized as test ports. The switch utilizes computer algorithms to make connections between a test port and one of the switch modules through which a path connecting specified input and output lines passes to make a bridging connection to the path.

Abstract: A cross-connect switch having different numbers of input and output lines is described. The switch is constructed from an odd number of stages. Each stage is constructed from a plurality of switch modules. Embodiments which require at most two different types of switch modules are described. Other embodiments which utilize at most two different types of switch modules are also described.

Abstract: The present invention concerns a process and a circuit enabling determination of the last intermediate node of a pathway comprising a minimum number of nodes from the m-th node to the n-th node in a network comprising p nodes interconnected by a number of links (p being a positive whole number). The process includes steps of iterative matrix calculation and comparison of elements of the same rank of certain matrices, and is especially suitable for communications networks constituted by a number of geographically separated nodes connected to one another by communications lines.

Abstract: A protocol for a switching system that establishes multiple parallel paths between users through multiple autonomous switching planes by having a user desiring connection to issue connection requests to each of the switching planes. According to the invention, the user monitors the number of connections that have been successfully completed and if only some of the connections have been completed, because of conflicting requests, it follows a conflict protocol to issue retry requests to the planes on which the connection request was unsuccessful. Each switching plane follows the conflict protocol to respond to the retry request by disconnecting existing connections and completing at most one retried connection request.

Abstract: An address (n) is associated with a sort element (30) so that input signals are compared with each other, or with the address (n) in the case of a null input (N). Several elements (30) are interconnected to provide unique signal routing from any input to a particular output, depending upon a characteristic of an input signal itself without reference to other input signals.

Abstract: An interface circuit includes programmable registers both for making provisioning signals available to a set of electric circuit devices, and for monitoring operation of at least a portion of those devices. Signals received from a control source are employed to program the registers and to provision device control memories enabled for that purpose by one or more of the registers.