Equipment Test Or Malfunction Indication Patents (Class 380/2)
  • Patent number: 10402248
    Abstract: A method and a program capable of controlling an error rate of device-specific information are provided.
    Type: Grant
    Filed: August 20, 2015
    Date of Patent: September 3, 2019
    Assignee: National Institute of Advanced Industrial Science and Technology
    Inventors: Yohei Hori, Kazukuni Kobara, Toshihiro Katashita, Toshihiro Matsui
  • Patent number: 10404977
    Abstract: Provided is a display device that has a usage validity period and confirms that the device is within the usage validity period when it is used, and can be improved in usefulness and can be used quickly, as well as a usage management method and program for the display device. The display device includes: a real-time clock; and, a control unit that, upon receiving a video display-ON signal for turning on video display under the condition that the status of the real-time clock is invalid, displays video corresponding to an input video signal.
    Type: Grant
    Filed: December 3, 2014
    Date of Patent: September 3, 2019
    Assignee: NEC DISPLAY SOLUTIONS, LTD.
    Inventors: Michio Yoshino, Masakazu Kobayashi
  • Patent number: 10291594
    Abstract: A computer-implemented method is provided for encrypting a message using a plurality of keys and a plurality of encryption algorithms. The method includes mapping, by the computing device, each of the plurality of keys to an encryption algorithm randomly selected from the plurality of encryption algorithms, and storing, by the computing device, in an index table the plurality of keys correlated to their respective encryption algorithms. The method also includes decomposing, by the computing device, the message into one or more message segments and encrypting, by the computing device, each of the one or more message segments using the index table. The method further includes transmitting, by the computing device, at least one of the index table or the one or more encrypted message segments to a receiving computing device over the electronic network.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: May 14, 2019
    Assignee: FMR LLC
    Inventor: Vishal Jindal
  • Patent number: 10275598
    Abstract: In one embodiment, the present invention includes a method to establish a secure pre-boot environment in a computer system and performs at least one secure operation in the secure environment. In one embodiment, the secure operation may be storage of a secret in the secure pre-boot environment.
    Type: Grant
    Filed: April 6, 2015
    Date of Patent: April 30, 2019
    Assignee: Intel Corporation
    Inventors: Vincent J. Zimmer, Bryant E. Bigbee, Andrew J. Fish, Mark S. Doran
  • Patent number: 10256980
    Abstract: A method and apparatus of a network element that authenticates a field replaceable unit of the network element is described. The network element authenticates a field replaceable unit of the network element by generating a nonce. In addition, the network element generates a signature using a nonce and a private encryption key that is securely stored in the field replaceable unit. The network element further verifies the signature using a public encryption key that is a pair to the private encryption key and is not securely stored in the field replaceable unit. If the field replaceable unit is verified, the network element uses the field replaceable unit to operate the network element. Otherwise, the network element disables the field replaceable unit.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: April 9, 2019
    Assignee: ARISTA NETWORKS, INC.
    Inventors: Alexander Channing Ho, Kenneth James Duda, Lorenz Wolfgang Redlefsen
  • Patent number: 10251060
    Abstract: In one example, a system for accessing services comprises a processor to detect a change in a topology of the system and request configuration data or a firmware image stored in secure storage of a wireless credential exchange or EEPROM, wherein the configuration data indicates an authorized stackable topology map for the system. The processor can also determine the change in the topology is allowed based on the authorized stackable topology map and execute an internet or local based service comprising a modification based on the change to the topology of the system, the service with the modification to be executed in response to a transmission of the change to the service.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: April 2, 2019
    Assignee: Intel Corporation
    Inventors: Kelly Steele, Rajesh Poornachandran, Vincent J. Zimmer
  • Patent number: 10210352
    Abstract: The present invention relates to a method to provide a dynamic change of security configurations in an integrated circuit product adapted to execute at least a given critical process and susceptible to be attacked. The method comprises the steps of tracking successive executions of the given critical process, and after a given number of such executions, triggering a change of the security configuration.
    Type: Grant
    Filed: April 13, 2015
    Date of Patent: February 19, 2019
    Assignee: GEMALTO SA
    Inventor: Philippe Loubet Moundi
  • Patent number: 10204134
    Abstract: A method, computer program product, and computer system for identifying, by a computing device, a change to at least one record of a plurality of records in a multi-record update. At least one problem condition associated with the change to the at least one record is determined, wherein the at least one problem condition is determined via at least one problem definition object before the change is saved. The at least one problem condition is organized on a display. An action is executed on the at least one problem condition displayed.
    Type: Grant
    Filed: August 14, 2014
    Date of Patent: February 12, 2019
    Assignee: International Business Machines Corporation
    Inventors: Filipe J. Barroso, Judith H. Cass, Marlin R. Deckert, Michael J. Saylor, Adam Skwersky
  • Patent number: 10200865
    Abstract: Methods and apparatus, including computer program products, are provided for adaptive security. In one aspect there is provided a method. The method may include receiving, at a user equipment, at least one policy update representative of a rule defining at least one of a security level and an operation allowed to be performed at the security level; monitoring a configuration of the user equipment to determine whether the configuration of the user equipment violates the at least one policy update; and adapting, based on the monitoring, at least one of a security indicator at the user equipment and the operation at the user equipment. Related apparatus, systems, methods, and articles are also described.
    Type: Grant
    Filed: August 29, 2013
    Date of Patent: February 5, 2019
    Assignee: Nokia Technologies Oy
    Inventors: Silke Holtmanns, Janne Uusilehto
  • Patent number: 10177915
    Abstract: The systems, methods and apparatuses described herein provide a computing device that is configured to attest itself to a communication partner. In one aspect, the computing device may comprise a communication port configured to receive an attestation request from the communication partner, and an application-specific integrated circuit (ASIC). The ASIC may be configured to receive the attestation request from the communication port. The attestation request may include a nonce generated at the communication partner. The ASIC may be further generate a verification value and send the verification value to the communication port to be transmitted back to the communication partner. The verification value may be a computation result of a predefined function taking the nonce as an initial value. In another aspect, the communication partner is configured to attest the computing device using speed of computation attestation.
    Type: Grant
    Filed: March 11, 2014
    Date of Patent: January 8, 2019
    Assignee: OLogN Technologies AG
    Inventor: Sergey Ignatchenko
  • Patent number: 10177916
    Abstract: The systems, methods and apparatuses described herein provide a computing device that is configured to attest itself to a communication partner. In one aspect, the computing device may comprise a communication port configured to receive an attestation request from the communication partner, and an application-specific integrated circuit (ASIC). The ASIC may be configured to receive the attestation request, which may include a nonce. The ASIC may be further configured to generate a verification value, capture data representing a state of computation of the ASIC when the verification value is being generated, and send the verification value and captured data to the communication port to be transmitted back to the communication partner. The verification value may be a computation result of a predefined function taking the nonce as an initial value. In another aspect, the communication partner may be configured to attest the computing device using speed of computation attestation.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: January 8, 2019
    Assignee: OLogN Technologies AG
    Inventor: Sergey Ignatchenko
  • Patent number: 10178638
    Abstract: A system, method and apparatus for configuring a node in a sensor network. A sensor service can enable sensor applications to customize the collection and processing of sensor data from a monitoring location. In one embodiment, sensor applications can customize the operation of nodes in the sensor network via a sensor data control system.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: January 8, 2019
    Assignee: Senseware, Inc.
    Inventors: Julien G. Stamatakis, Thomas Hoffmann, Nathan A. Sacks
  • Patent number: 10162777
    Abstract: A transmission unit for connection to a first bus system, the transmission unit receiving messages via the first bus system, the messages being constructed as a succession of a first bit sequence, of at least one control signal and of a second bit sequence, the first bit sequence of a received message being forwarded by the transmission unit to a processing station, at least one predefined control signal of the received message being checked by the transmission unit, the second bit sequence of the received message being forwarded by the transmission unit to the processing station if the predefined signal of the received message has a predefined value, instead of the second bit sequence, the transmission unit sending a predefined or predefinable terminating bit sequence to the processing station, if the predefined control signal of the received message has a value that deviates from the predefined value.
    Type: Grant
    Filed: May 26, 2015
    Date of Patent: December 25, 2018
    Assignee: ROBERT BOSCH GMBH
    Inventor: Stefan Thiele
  • Patent number: 10157282
    Abstract: In one embodiment, a system includes a processor and logic integrated with and/or executable by the processor, the logic being configured to cause the processor to receive a data stream including data for encryption, insert one or more test vectors between individual blocks of data of the data stream, encrypt the blocks of data including the one or more test vectors to produce an encrypted data stream including one or more encrypted test vectors, decrypt the encrypted data stream including the one or more encrypted test vectors, compare each decrypted test vector with a corresponding inserted test vector, and report results of the comparison. Other systems, methods, and computer program products for self testing an encryption/decryption cycle are described according to more embodiments.
    Type: Grant
    Filed: December 16, 2013
    Date of Patent: December 18, 2018
    Assignee: International Business Machines Corporation
    Inventors: Charles J. Camp, Bryan B. Grandy, Glen A. Jaquette
  • Patent number: 10102400
    Abstract: A system comprising a processor adapted to activate multiple security levels for the system and a monitoring device coupled to the processor and employing security rules pertaining to the multiple security levels. The monitoring device restricts usage of the system if the processor activates the security levels in a sequence contrary to the security rules.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: October 16, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Gregory R. Conti
  • Patent number: 10027640
    Abstract: A method includes: decrypting, in a device, a first subset of encrypted data using a cryptographic device key associated with the device to produce first plain text, where a set of encrypted data comprises the first subset of encrypted data and a second subset of encrypted data, and where the first subset of encrypted data and the second subset of encrypted data each contain less encrypted data than the set of encrypted data and are different from each other; decrypting, in the device, the second subset of encrypted data using the cryptographic device key to produce second plain text; encrypting, in the device, the first plain text using a first ephemeral key to produce first re-encrypted data; and encrypting, in the device, the second plain text using a second ephemeral key to produce second re-encrypted data, the second ephemeral key being different from the first ephemeral key.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: July 17, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Roberto Avanzi, Rosario Cammarota, Ron Keidar
  • Patent number: 9990797
    Abstract: A user terminal comprises an encryption apparatus, a tamper detection system associated with the encryption apparatus and means for triggering the tamper detection system in response to tampering with the encryption apparatus, at least one further component, and further means for triggering the tamper detection system, wherein the further means for triggering the tamper detection system is configured to trigger the tamper detection system in response to tampering with the at least one further component.
    Type: Grant
    Filed: October 11, 2013
    Date of Patent: June 5, 2018
    Assignee: KORALA ASSOCIATES LIMITED
    Inventor: Aravinda Korala
  • Patent number: 9984238
    Abstract: A storage device can include processing and cryptographic capability enabling the device to function as a hardware security module (HSM). This includes the ability to encrypt and decrypt data using a cryptographic key, as well as to perform processing using such a key, independent of whether that processing involves data stored on the device. An internal key can be provided to the drive, whether provided before customer software access or received wrapped in another key, etc. That key enables the device to perform secure processing on behalf of a user or entity, where that key is not exposed to other components in the network or environment. A key may have specified tasks that can be performed using that key, and can be discarded after use. In some embodiments, firmware is provided that can cause a storage device to function as an HSM and/or processing device with cryptographic capability.
    Type: Grant
    Filed: March 30, 2015
    Date of Patent: May 29, 2018
    Assignee: AMAZON TECHNOLOGIES, INC.
    Inventors: Gregory Branchek Roth, Eric Jason Brandwine
  • Patent number: 9887947
    Abstract: A circuit transmits a beneficiary to a benefits server when a message recipient has disposed of an incentivized message by opening and attending to the message. A navigation and viewport control circuit presents a précis of an incentivized message with a proposed time to disposition (TTD), a proposed disposition, and a proffered benefit for at least minimally engaging with the message; records the time the message is opened; and whether the required minimum has been attained. A message transformation and disposition apparatus retrieves, from a benefit server, a decay or expiration time, a required quantum of engagement, and a proffered benefit. Stored disposition history of recipient and peers is read to determine a proposed disposition and TTD according to user's preferences for benefits and their expiration dates. A timer causes performance of the proposed disposition depending on user's activity or inactivity. Engagement can require passive viewing or non-random interacting.
    Type: Grant
    Filed: February 19, 2015
    Date of Patent: February 6, 2018
    Assignee: Notion AI, Inc.
    Inventors: Lindsay Snider, Ian Berry, Guy Suter
  • Patent number: 9881147
    Abstract: A method includes receiving, from a user via an electronic device, input representing a password to be utilized for an account; automatically determining, utilizing a processor, a complexity value for the input password; automatically determining, based on the determined complexity value, security settings for the account; receiving, from a user via an electronic device, input representing an attempt to login to the account, the input representing an attempt to login to the account including an attempted password; automatically determining that the attempted password does not match the password to be utilized for the account; and determining a course of action to take in response to the determination that the attempted password does not match the password to be utilized for the account, the course of action being determined based at least in part on the automatically determined security settings for the account.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: January 30, 2018
    Assignee: ALLSCRIPTS SOFTWARE, LLC
    Inventors: David Thomas Windell, Todd Michael Eischeid, Scott David Bower
  • Patent number: 9881300
    Abstract: Technologies for split key security include a payment device to generate a key encryption key and a first key encryption key part. The payment device generates a second key encryption key part based on the key encryption key and the first key encryption key part and deletes the key encryption key in response to generating the second key encryption key part. Further, the payment device stores the first key encryption key part to a secure memory of a security co-processor of the payment device and the second key encryption key part to a secure memory of a secondary processor of the payment device. The secondary processor is electrically coupled to a backup energy source.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: January 30, 2018
    Assignee: Intel Corporation
    Inventors: Kenneth W. Reese, Raviprakash Nagaraj, Leonard Goodell, James L. Fafrak
  • Patent number: 9832420
    Abstract: A source device that provides contents to a sink device and a communication method thereof are provided. The communication method of the source device includes: transmitting a communication signal including a High-bandwidth Digital Content Protection (HDCP) signal to the sink device; determining a communication status with the sink device using an HDCP communication result received from the sink device; and adjusting the communication signal according to the determined communication status. Therefore, the communication method can provide a user with optimized contents.
    Type: Grant
    Filed: May 24, 2012
    Date of Patent: November 28, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Sung-bo Oh
  • Patent number: 9824240
    Abstract: A method and an apparatus for using a memory device are provided. A host device includes a transmitter that transmits data; a receiver that receives data; and a controller configured to receive configuration information of the memory device including the information related to the data stored in the one or more slots determined according to each vendor of the memory device, identify information related to predetermined data in the configuration data of the memory device, and receive the predetermined data from the memory device.
    Type: Grant
    Filed: November 13, 2013
    Date of Patent: November 21, 2017
    Assignee: Samsung Electronics Co., Ltd
    Inventors: In-Kyo Kim, Jae-Bum Lee, Hyoung-Suk Jang, Do-Young Kim, Yong Chang
  • Patent number: 9774451
    Abstract: Methods, devices, systems, and non-transitory process-readable storage media for using secure elements to authenticate a data source device for providing reporting data to a recipient device via local point-to-point communications. An embodiment method includes operations performed by a secure processor of a recipient device that include generating a random token, a data encryption key, and a control register, encrypting the generated data using a shared encryption algorithm and a secret key associated with a unique identifier of the data source device, decrypting data re-encrypted by the data source device and sent within a response message using the shared encryption algorithm and the secret key, determining whether decrypted data matches the random token, and identifying the data source device is authenticated in response to determining that decrypted data matches the random token. The unique identifier and secret key may be pre-loaded on the recipient device.
    Type: Grant
    Filed: February 10, 2015
    Date of Patent: September 26, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Goutam Motika, Samatha Sudabattula
  • Patent number: 9766963
    Abstract: Systems, apparatuses and methods may provide for receiving one or more debug communications and programming, via a bus, a set of debug registers with debug information corresponding to the one or more debug communications. Additionally, tunnel logic hardware may be instructed to transfer the debug information from the set of debug registers to one or more test access ports of an intelligent device such as a non-volatile memory storage unit having a microcontroller. In one example, if it is detected that debug permission has been granted during a boot process, a control status register may be unlocked. If, on the other hand, the debug permission is not detected during the boot process, the control status register may be locked. Accordingly, an enable bit of the control status register may be used to activate the tunnel logic hardware only if the control status register is unlocked.
    Type: Grant
    Filed: September 23, 2015
    Date of Patent: September 19, 2017
    Assignee: Intel Corporation
    Inventors: Shamanna M. Datta, Murugasamy K. Nachimuthu, Mahesh S. Natu
  • Patent number: 9742565
    Abstract: Provided are a method and system for backing up a private key in an electronic signature token, the method comprising: a first electronic signature token and a second electronic signature token negotiate an encryption strategy and a corresponding decryption strategy to use for communication therebetween; the first electronic signature token utilizes the encryption strategy to encrypt a request data packet and transmits the encrypted request data packet; the second electronic signature token decrypts the encrypted request data packet; the second electronic signature token utilizes the encryption strategy to encrypt a response data packet and transmits the encrypted responses data packet; and the first electronic signature token utilizes the decryption strategy to decrypt the response data packet, and acquires a private key from the response data packet.
    Type: Grant
    Filed: April 18, 2014
    Date of Patent: August 22, 2017
    Assignee: Tendyron Corporation
    Inventor: Dongsheng Li
  • Patent number: 9729322
    Abstract: Method and system for personalizing a chip, intended to be integrated into a smart card, comprising a tester associated to an FPGA device connected to the chip, the chip being part of a wafer comprising a plurality of chips and a disposable hardware module for verifying presence of the chip on the wafer. The tester sends a first secret code to the FPGA device, which commands the chip to initiate a test mode activation. The FPGA device encrypts a second secret code by using a secret encryption algorithm parameterized with a random number received from the chip and the first secret code to obtain a first cryptogram which is sent to the chip. The chip determines a second cryptogram by carrying out a Boolean function over a result obtained by decryption of the first cryptogram using the inverse algorithm parameterized with the random number and the first secret code.
    Type: Grant
    Filed: April 7, 2016
    Date of Patent: August 8, 2017
    Assignee: NAGRAVISION S.A.
    Inventors: Roan Hautier, Marco Macchetti, Jerome Perrine
  • Patent number: 9712515
    Abstract: A system includes a gateway and a verification server. The gateway is configured to receive a first message from a client over a network; send a request to a verification server to generate a first credential based on the first message; and route the first message toward a remote device. The verification server is configured to receive the request from the gateway; generate the first credential in response to the request; store the first credential; receive a second message from the remote device, the message requesting the verification server to validate a second credential; determine whether the second credential is valid based on the first credential; and send a notification to the remote device indicating whether the second credential is valid.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: July 18, 2017
    Assignee: Cellco Partnership
    Inventors: Kumar Sanjeev, Amir Mayblum, Eliezer K. Pasetes, Sethumadhav Bendi, Jerry M. Kupsh, Alice Yuan Bain
  • Patent number: 9698991
    Abstract: The systems, methods and apparatuses described herein provide a computing device that is configured to attest itself to a communication partner. In one aspect, the computing device may comprise a communication port configured to receive an attestation request from the communication partner, and an application-specific integrated circuit (ASIC). The ASIC may be configured to receive the attestation request, which may include a nonce. The ASIC may be further configured to generate a verification value, capture data representing a state of computation of the ASIC when the verification value is being generated, and send the verification value and captured data to the communication port to be transmitted back to the communication partner. The verification value may be a computation result of a predefined function taking the nonce as an initial value. In another aspect, the communication partner may be configured to attest the computing device using speed of computation attestation.
    Type: Grant
    Filed: March 11, 2014
    Date of Patent: July 4, 2017
    Assignee: OLogN Technologies AG
    Inventor: Sergey Ignatchenko
  • Patent number: 9680637
    Abstract: A monolithic integrated circuit (IC) secure hashing device may include a memory, and a processor integrated with the memory. The processor may be configured to receive a message, and to process the message using a given secure hash algorithm (SHA) variant from among different SHA variants. The different SHA variants may be based upon corresponding different block sizes of bits.
    Type: Grant
    Filed: May 1, 2009
    Date of Patent: June 13, 2017
    Assignee: HARRIS CORPORATION
    Inventors: Douglas Wayne Walker, Christopher David Mackey
  • Patent number: 9641339
    Abstract: A method and apparatus of a network element that authenticates a field replaceable unit of the network element is described. The network element authenticates a field replaceable unit of the network element by generating a nonce. In addition, the network element generates a signature using a nonce and a private encryption key that is securely stored in the field replaceable unit. The network element further verifies the signature using a public encryption key that is a pair to the private encryption key and is not securely stored in the field replaceable unit. If the field replaceable unit is verified, the network element uses the field replaceable unit to operate the network element. Otherwise, the network element disables the field replaceable unit.
    Type: Grant
    Filed: July 31, 2014
    Date of Patent: May 2, 2017
    Assignee: Arista Networks, Inc.
    Inventors: Alexander Channing Ho, Kenneth James Duda, Lorenz Wolfgang Redlefsen
  • Patent number: 9628338
    Abstract: In embodiments of mesh network commissioning, a node device in a mesh network receives a commissioning dataset, and compares a timestamp in the received commissioning dataset with a stored timestamp in a commissioning dataset that is stored in the node. The node device can determine from the comparison that the stored timestamp is more recent than the received timestamp, and in response, transmit a message to a leader device of the mesh network, where the message includes the stored commissioning dataset. The leader device accepts the stored commissioning dataset as the most recent commissioning dataset for the mesh network, and propagates the stored commissioning dataset to the mesh network. Alternatively, the node device can determine that the received timestamp is more recent than the stored timestamp, and in response to the determination, update the stored commissioning dataset to match the received commissioning dataset.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: April 18, 2017
    Assignee: Google Inc.
    Inventors: Martin A. Turon, Grant M. Erickson, Christopher A. Boross, Jay D. Logue
  • Patent number: 9571273
    Abstract: A method and system for accelerated decryption of a cryptographically protected user data unit, wherein a transmitter initially generates a cryptographic key that is provided with a related key identification. The transmitter then performs asymmetrical encryption of the generated cryptographic key using a public cryptographic key and encryption of at least one user data unit using the generated cryptographic key. The encrypted user data unit, the asymmetrically encrypted cryptographic key and the related key identification of the cryptographic key are transported to a receiver that decrypts the received asymmetrically encrypted key using a private key, if verification of the received related key identification of the cryptographic key indicates the cryptographic key is not present in a decrypted state in the receiver. The receiver then decrypts the received cryptographically encrypted user data unit using the cryptographic key in the receiver or with the cryptographic key decrypted using the private key.
    Type: Grant
    Filed: October 12, 2010
    Date of Patent: February 14, 2017
    Assignee: Siemens Aktiengesellschaft
    Inventors: Michael Braun, Markus Dichtl, Bernd Meyer
  • Patent number: 9544668
    Abstract: A method of operation of an optical network communication system including: providing a planar lightwave circuit including: connecting 2×2 single-mode optical couplers in an array for forming a 1×N single-mode optical splitter/combiner, and routing harvesting ports to an optical line terminal receiver for collecting harvested-light, from two or more of the harvesting ports, in the optical line terminal receiver wherein one of more of the harvesting ports is from the 2×2 single-mode optical couplers; transmitting to an optical network unit through the planar lightwave circuit at a first wavelength; and interpreting a response from the optical network unit at a second wavelength through the harvested-light.
    Type: Grant
    Filed: December 13, 2010
    Date of Patent: January 10, 2017
    Assignee: NeoPhotonics Corporation
    Inventors: David Piehler, Anthony J. Ticknor
  • Patent number: 9537790
    Abstract: A computing environment adapted with a resource allocation policy, the resource allocation policy being configured to evenly distribute application instances to as many servers as possible.
    Type: Grant
    Filed: June 16, 2015
    Date of Patent: January 3, 2017
    Assignee: JPMorgan Chase Bank, N.A.
    Inventors: Minlin Gao, Alexey V. Syomichev, Aaron Bell, Libin Yang, Jason K. S. Choy
  • Patent number: 9503443
    Abstract: A network element, configured to operate in a network to provide various network functions therein, includes a main processor communicatively coupled to a main memory, wherein the main processor is configured to perform Operations, Administration, Maintenance, and Provisioning (OAM&P) associated with the network element, wherein the main processor is accessible through one or more access techniques; and a supervisory plane comprising a secure processor and a secure memory communicatively coupled thereto, wherein the supervisory plane is separate from and communicatively coupled to the main processor and the main memory, the supervisory plane is configured to allow secure, direct access to the main processor and the main memory.
    Type: Grant
    Filed: September 15, 2014
    Date of Patent: November 22, 2016
    Assignee: Ciena Corporation
    Inventors: David Jordan Krauss, Stephen B. Alexander, Loudon Thomas Blair
  • Patent number: 9437129
    Abstract: Provided are display driving integrated circuits, display devices, and/or methods of operating the display driving integrated circuit. The display driving integrated circuit including a timing controller processing input data and outputting output data; and a source driving unit including at least one source driver and converting into analog data the output data received through a transmission channel connected to the timing controller and outputting the analog data as display data may be provided. The timing controller may include a data selecting unit comparing a transition count of the input data with a transition count of encoded data obtained by encoding the input data, and outputting one of the input data and the encoded data as selection data according to the comparison, a data randomizing unit randomizing the selection data and generating random data, and a data transmitting unit converting the random data into the output data may be provided.
    Type: Grant
    Filed: January 21, 2015
    Date of Patent: September 6, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young-hun Lee, Sun-ik Lee, Young-min Choi
  • Patent number: 9384352
    Abstract: An embodiment includes an apparatus comprising: an out-of-band cryptoprocessor including secure non-volatile storage that couples to a root index, having a fixed address, and comprises first and second variables referenced by the root index; and semiconductor integrated code (SIC) including embedded processor logic to initialize a processor and embedded memory logic to initialize a memory coupled to the processor; wherein (a) the SIC is to be executed responsive to resetting the processor and prior to providing control to boot code, and (b) the SIC is to perform pre-boot operations in response to accessing at least one of the first and second variables. Other embodiments are described herein.
    Type: Grant
    Filed: October 2, 2013
    Date of Patent: July 5, 2016
    Assignee: Intel Corporation
    Inventors: Jiewen Yao, Vincent J. Zimmer, Nicholas J. Adams, Willard M. Wiseman, Qin Long, Shihui Li
  • Patent number: 9378379
    Abstract: Systems, methods and consumer-readable media for providing an system implementing an information lock box. Sensitive files may be identified by the system prior to engagement of the protection system. One method according to the invention may preferably include hiding and/or encrypting sensitive files upon detecting changes of the network status. The information lock box may utilize a file-system driver to control access to files. The system may communicate with administrative serve and communicating messages to a user.
    Type: Grant
    Filed: June 16, 2011
    Date of Patent: June 28, 2016
    Assignee: Bank of America Corporation
    Inventor: William S. Treadwell
  • Patent number: 9361170
    Abstract: The invention aims to provide a method and a system on chip able to detect at once hardware and software errors to prevent manipulations for retrieving cryptographic keys, inserting or suppressing instructions to bypass security processes, modifying programs or memory content etc. The system on chip comprises a core including at least two processors, registers, and a data consistency check module. The core is connected to at least one set of memories containing zones for instructions of a first program and of a second program, said instructions being to be executed respectively by the first and second processor, which respectively produce and store result data into the registers and the memories.
    Type: Grant
    Filed: June 17, 2015
    Date of Patent: June 7, 2016
    Assignee: NAGRAVISION S.A.
    Inventors: Marc Bellocchio, Christophe Gogniat
  • Patent number: 9338004
    Abstract: Method and system for personalizing a chip, intended to be integrated into a smart card, comprising a tester associated to an FPGA device connected to the chip, the chip being part of a wafer comprising a plurality of chips and a disposable hardware module for verifying presence of the chip on the wafer. The tester sends a first secret code to the FPGA device, which commands the chip to initiate a test mode activation. The FPGA device encrypts a second secret code by using a secret encryption algorithm parameterized with a random number received from the chip and the first secret code to obtain a first cryptogram which is sent to the chip. The chip determines a second cryptogram by carrying out a Boolean function over a result obtained by decryption of the first cryptogram using the inverse algorithm parameterized with the random number and the first secret code.
    Type: Grant
    Filed: October 8, 2013
    Date of Patent: May 10, 2016
    Assignee: NAGRAVISION S.A.
    Inventors: Roan Hautier, Marco Macchetti, Jerome Perrine
  • Patent number: 9253161
    Abstract: A method of communicating in a secure communication system, comprises the steps of assembling as message at a sender, then determining a security level, and including an indication of the security level in a header of the message. The message is then sent to a recipient.
    Type: Grant
    Filed: January 10, 2014
    Date of Patent: February 2, 2016
    Assignee: Certicom Corp.
    Inventor: Marinus Struik
  • Patent number: 9225521
    Abstract: Described herein are an apparatus and method for Skein hashing. The apparatus comprises a block cipher operable to receive an input data and to generate a hashed output data by applying Unique Block Iteration (UBI) modes, the block cipher comprising at least two mix and permute logic units which are pipelined by registers; and a counter, coupled to the block cipher, to determine a sequence of the UBI modes and to cause the block cipher to process at least two input data simultaneously for generating the hashed output data.
    Type: Grant
    Filed: October 6, 2014
    Date of Patent: December 29, 2015
    Assignee: Intel Corporation
    Inventors: Farhana Sheikh, Jesse Walker, Sanu K. Mathew, Ram K. Krishnamurthy
  • Patent number: 9094189
    Abstract: A cryptographic method for communicating confidential information m between a first electronic entity (A) and a second electronic entity (B), includes a distribution step and a reconciliation step, the distribution step including a plurality of steps, one of which consists of the first entity (A) and the second entity (B) calculating a first intermediate value PA and a second intermediate value PB, respectively, such that: PA=YA·SB=YA·XB+YA·f(YB), and PB=YB·SA=YB·XA+YB f(YA), such that, during the reconciliation step, the first entity (A) can retrieve the confidential information by a process of decrypting a noisy message composed by the second entity (B) in particular from the second intermediate value PB.
    Type: Grant
    Filed: February 17, 2011
    Date of Patent: July 28, 2015
    Assignee: CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE-CNRS
    Inventors: Philippe Gaborit, Carlos Aguilar Melchor
  • Patent number: 9066117
    Abstract: A video processing device for encrypting a compressed video signal that includes a key storage device for storing at least one encryption key. An encryption processing device retrieves the at least one encryption key from the key storage device, and directly encrypts an elementary bit stream into at least one encrypted elementary bit stream.
    Type: Grant
    Filed: March 19, 2012
    Date of Patent: June 23, 2015
    Assignee: VIXS Systems, INC
    Inventor: Paul D. Ducharme
  • Publication number: 20150092939
    Abstract: Embodiments of an invention for using dark bits to reduce physically unclonable function (PUF) error rates are disclosed. In one embodiment, an integrated circuit includes a PUF cell array and dark bit logic. The PUF cell array is to provide a raw PUF value. The dark bit logic is to select PUF cells to mark as dark bits and to generate a dark bit mask based on repeated testing of the PUF cell array.
    Type: Application
    Filed: September 27, 2013
    Publication date: April 2, 2015
    Inventors: Kevin Gotze, Gregory Iovino, David Johnston, Patrick Koeberl, Jiangtao Li, Wei Wu
  • Patent number: 8959327
    Abstract: A security processor may be embedded within a digital cable ready (DCR) digital TV (DTV) system-on-chip to performing content protection operations during digital TV signal processing. The embedded security processor may be used to perform operations that are currently performed by an external entity, such as, for an example, a CableCard. The embedded security processor maybe configured to use a conditional access function including, but not limited to, CableLabs® Downloadable Conditional Access System (DCAS) based function. The security processor may be reprogrammable to enable the system-on-chip to be reconfigured with a different function and/or to allow operation with a new cable service provider. The security processor may enable secure reprogrammability of the system-on-chip utilizing security algorithms and/or other mechanisms including use of chip-specific identification information. The SoC may be enabled to operate with a CableCard whenever the security processor may be disabled.
    Type: Grant
    Filed: April 27, 2007
    Date of Patent: February 17, 2015
    Inventor: Xuemin Chen
  • Patent number: 8948375
    Abstract: A data processing system is provided that includes applications, databases, encryption engines, and decryption engines. Encryption and decryption engines may be used to perform format-preserving encryption on data strings stored in a database. Applications may be used to embed information in data strings. Information may be embedded by using a character set that is larger than a character set being used by a data string. A data string may be converted into a larger character set, analogous to converting a number from a lower base to higher base. Such a conversion may shorten a data string, allowing information to be embedded as appended characters.
    Type: Grant
    Filed: May 5, 2009
    Date of Patent: February 3, 2015
    Assignee: Voltage Security, Inc.
    Inventors: Steven D. Burnett, Terence Spies, Luther W. Martin, Robert K. Vaterlaus, Matthew J. Pauker
  • Patent number: 8925074
    Abstract: Incoming files are examined to detect abnormal files. The incoming files may be examined for a weak file structure, such as a weak file format structure or a weak file data structure, to detect abnormal files. A weak file structure includes file structures that do not conform to the file format of the file yet still loadable by a file loader of the file format. The incoming files may also be examined for suspicious loading in memory to detect abnormal files.
    Type: Grant
    Filed: July 17, 2012
    Date of Patent: December 30, 2014
    Assignee: Trend Micro Incorporated
    Inventor: Chik-Kun Ho
  • Patent number: 8918452
    Abstract: Embodiments allow developers to use HTTP message abstractions inline within their Web API methods to directly access and manipulate HTTP request and response messages. A hosting layer is provided for in-process, in-memory and network-based services. Message handlers and operational handlers may be combined to create a message channel for asynchronous manipulations of the HTTP requests and response. A formatter may be used on the server or client for consuming HTTP and providing desired media types.
    Type: Grant
    Filed: September 28, 2011
    Date of Patent: December 23, 2014
    Assignee: Microsoft Corporation
    Inventors: Henrik Frystyk Nielsen, Glenn Block, Randall Tombaugh, Ronald A. Cain, HongMei Ge, Alexander Corradini