Abstract: A data processing method includes the following steps. An input image is received, the input image has a plurality of pixels, and each of the pixels has a pixel position. An valid region is defined in the input image, a plurality of valid pixels among the pixels are located in the valid region, and each valid pixel has a valid data. The valid data is written to the target address of the memory correspondingly according to a starting write address of the memory and a valid width of the input image, or according to the starting write address, the starting offset of the input image and the accumulation address of the memory.

Abstract: In a low power hardware architecture for handling accumulation overflows in a convolver unit, an accumulator of the convolver unit computes a running total by successively summing dot products from a dot product computation module during an accumulation cycle. In response to the running total overflowing the maximum or minimum value of a data storage element, the accumulator transmits an overflow indicator to a controller and sets its output equal to a positive or negative overflow value. In turn, the controller disables the dot product computation module by clock gating, clamping one of its inputs to zero and/or holding its inputs to constant values. At the end of the accumulation cycle, the output of the accumulator is sampled. In response to a clear signal being asserted, the dot product computation module is enabled, and the running total is set to zero for the start of the next accumulation cycle.

Abstract: An image processing device includes a plurality of processing units which are connected to a common data bus and performing predetermined processing on data read from a data storage unit connected to the data bus via the data bus. At least one of the processing units includes: a plurality of processing modules that are configured to perform predetermined processing on input data; an input/output module that is configured to operate as the processing module that directly inputs and outputs data from/to outside without passing through the data bus; and a connection switching unit that is configured to change a configuration of a pipeline by switching a connection between the processing modules according to input settings, and is an image processing unit that are configured to perform a pipeline processing by each of the processing modules constituting the pipeline.

Abstract: A non-transitory computer-readable recording medium stores computer-readable instructions, when executed by a processor of an information processing apparatus, causing the information processing apparatus to perform: receiving a parameter from a first other program different from the program; in response to receiving the parameter from the first other program, transmitting a scan execution command including the received parameter to a scanner through a communication interface of the information processing apparatus, the parameter being indicative of a setting value that is set for executing scan processing on the scanner; receiving mode selection information from a second other program different from the program and from the first other program; and in response to receiving the mode selection information from the second other program, converting the received mode selection information into a parameter, and transmitting a scan execution command including the converted parameter to the scanner through the commu

Abstract: In one embodiment, a method includes accessing foreground visual data that comprises a set of coordinate points that correspond to a plurality of surface points of a person in an environment; generating a bounding box for the set of coordinate points, wherein the bounding box comprises every coordinate point in the set of coordinate points; providing instructions to collect background visual data for an area in the environment that is outside of the bounding box; and providing the foreground visual data and the background visual data to an intelligent director associated with the computing device.

Abstract: Systems and methods for producing blot images. A blot, for example a western blot, is imaged using an imaging system having a field of view and a magnification. Features of interest in the blot correspond to features in the digital image, and the sizes of the features in the digital image depend on the magnification of the imaging system. A structuring element is selected based on the sizes and shapes of the features in the digital image, and the image is morphologically eroded and dilated varying numbers of times. The eroded and dilated image is subtracted from the original blot image to remove background signal from the blot image, producing an output image. The number of erosions needed to completely erode the features of interest is determined automatically, for example by investigating the behavior of the kurtosis of the output image as a function of the number of erosions performed.

Abstract: One embodiment provides a unified multifunction circuitry. The unified multifunction circuitry includes a logarithm circuitry and an antilogarithm circuitry. The logarithm circuitry is to determine a log output operand. The log output operand includes a piecewise linear approximation of a base 2 logarithm of a significand of a log input operand. The antilogarithm circuitry is to determine an antilog output operand. The antilog output operand includes a piecewise linear approximation of a base 2 antilogarithm of a fraction of a selected input operand.

Abstract: Techniques and mechanisms described herein include a signal processor implemented as an overlay on a field-programmable gate array (FPGA) device that utilizes special purpose, hardened intellectual property (IP) modules such as memory blocks and digital signal processing (DSP) cores. A Processing Element (PE) is built from one or more DSP cores connected to additional logic. Interconnected as an array, the PEs may operate in a computational model such as Single Instruction-Multiple Thread (SIMT). A software hierarchy is described that transforms the SIMT array into an effective signal processor.

Abstract: There are provided methods and apparatus for video usability information (VUI) for scalable video coding (SVC). An apparatus includes an encoder for encoding video signal data into a bitstream. The encoder specifies video user information, excluding hypothetical reference decoder parameters, in the bitstream using a high level syntax element. The video user information corresponds to a set of interoperability points in the bitstream relating to scalable video coding.

Abstract: Embodiments of the present inventions are related to systems and methods for data processing, and more particularly to systems and methods for recovering data where synchronization information is not detected.

Abstract: An analytical instrument includes a data acquisition system that produces data. The analytical instrument includes a data compression system/process that utilizes a lossless data compression technique that can be implemented using minimal hardware and software resources. The process may be implemented in such a way that it can be split into many parallel operations. The process can be implemented utilizing software and/or processing devices such as Field-Programmable Gate Arrays (FPGAs) or Graphics Processing Units (GPUs).

Abstract: Methods and systems of recognizing images may include an apparatus having a hardware module with logic to, for a plurality of vectors in an image, determine a first intermediate computation based on even pixels of an image vector, and determine a second intermediate computation based on odd pixels of an image vector. The logic can also combine the first and second intermediate computations into a Hessian matrix computation.

Abstract: Techniques are provided to implement line based processing of thermal images and a flexible memory system. In one example, individual lines of a thermal image frame may be provided to an image processing pipeline. Image processing operations may be performed on the individual lines in stages of the image processing pipeline. A memory system may be used to buffer the individual lines in the pipeline stages. In another example, a memory system may be used to send and receive data between various components without relying on a single shared bus. Data transfers may be performed between different components and different memories of the memory system using a switch fabric to route data over different buses. In another example, a memory system may support data transfers using different clocks of various components, without requiring the components and the memory system to all be synchronized to the same clock source.

Abstract: Techniques are provided to implement line based processing of thermal images and a flexible memory system. In one example, individual lines of a thermal image frame may be provided to an image processing pipeline. Image processing operations may be performed on the individual lines in stages of the image processing pipeline. A memory system may be used to buffer the individual lines in the pipeline stages. In another example, a memory system may be used to send and receive data between various components without relying on a single shared bus. Data transfers may be performed between different components and different memories of the memory system using a switch fabric to route data over different buses. In another example, a memory system may support data transfers using different clocks of various components, without requiring the components and the memory system to all be synchronized to the same clock source.

Abstract: A system on chip (SoC) including a configurable image processing pipeline is provided. The SoC includes a bus; a first image processing module configured to be connected to the bus and to process image data; a first image processing stage configured to transmit either first image data or second image data received from the bus to at least one of the bus and the first image processing module through a first bypass path in response to first control signals; and a second image processing stage configured to transmit either third image data received from the first image processing module or fourth image data received from the bus to the bus through one of a second bypass path and a second scaler path in response to second control signals.

Abstract: A method for printing with a printhead, comprising: generating a first imaging matrix comprising cells each containing information related to the ink to be deposited on a corresponding area of the print medium; on the basis of said first matrix, generating a second imaging matrix, comprising cells each containing information related to the ink drops to be deposited on a corresponding area of the print medium; wherein some cells of the second matrix are prioritized and for some of them the information related to the ink drops depends on a cell of the first matrix that corresponds to a different area of the print medium than the area of said prioritized cell of the second matrix; such that upon printing, nozzles of the printhead associated with some prioritized cells fire ink that in the first matrix is associated with areas of the print medium corresponding to non-prioritized cells.

Abstract: A display controller system with a memory controller and buffers is described. The system enables transferring data from the main memory of the CPU to the image memory without interfering the image updating. As a result, the present invention may allow continuously updating the display image and continuously writing new image data from CPU to the image memory which improves overall system performance.

Abstract: A method of processing digital video signals, comprising: receiving input pixels to be processed; performing multiple processing operations on the input pixels, where the multiple processing operations are performed during a time interval determined in part by a desired video output rate; and performing a classification analysis at an intermediate time during the time interval, the classification analysis yielding tag data that is used to dynamically vary one or more of the multiple processing operations, and where the tag data is generated on a per-pixel basis to enable pixel by pixel variation of the multiple processing operations.

Abstract: The disclosed embodiments include an apparatus implemented in a semiconductor integrated chip. The apparatus is configured to operate a composite function, comprising a first function and a second function, on a first patch of an image. The apparatus includes a first function operator configured to operate the first function on the group of pixel values to provide a first processed group of pixel values. The apparatus also includes a delay system configured to maintain the first processed group of pixel values for a predetermined period of time to provide a delayed processed group of pixel values. The apparatus further includes a second function operator configured to operate a second function on at least a second processed group of pixels and the delayed processed group to determine an output of the composite function.

Abstract: An image processing apparatus for processing image data by a plurality of pipeline-connected processing modules is provided. The apparatus includes a first pipeline processing unit configured to include a plurality of processing modules including a processing module which processes image data for every first size; and a second pipeline processing unit configured to be branched from the first pipeline processing unit and include a plurality of processing modules including a processing module which processes image data for every second size different from the first size. The second pipeline processing unit includes, at a start, a change unit configured to acquire partial image data of the first size from the first pipeline processing unit and change the partial image data of the first size into partial image data of the second size.

Abstract: A hardware architecture is applied to the calculation of a Difference-of-Gaussian filter, which is typically employed in image processing algorithms. The architecture has a modular structure to easily allow the matching of the desired delay/area ratio as well as a high computational accuracy. A new solution is provided for the implementation of multiply-accumulators which allows a significant reduction of area with respect to the conventional architectures.

Abstract: Techniques and systems for media data customization system are provided. In one embodiment, a media data customization system includes a resource allocator that receives media data and a media data customization request and that allocates customization resources for a service of the media data customization request, a pipe repository that stores pipe filter modules, and a pipe manager that retrieves pipe filter modules stored in the pipe repository based on the media data customization request, that integrates the retrieved pipe filter modules to form a pipe group, and that applies the pipe group to the media data using the customization resources to generate customized media data.

Abstract: An image processor comprises a plurality of processing modules coupled together in series. Each of at least two of the processing modules includes an image data input to receive at least one of i) an original image or ii) image data output by a previous processing module in the series. Each of the at least two of the processing modules also includes a processing unit configured to i) detect that image data is to be generated and ii) process image data received via the at least one image data input to generate image data. Each of the at least two of the processing modules also includes a memory to store image data generated by the processing unit.

Abstract: An image processing apparatus for processing image data by a plurality of pipeline-connected processing modules is provided. The apparatus includes a first pipeline processing unit configured to include a plurality of processing modules including a processing module which processes image data for every first size; and a second pipeline processing unit configured to be branched from the first pipeline processing unit and include a plurality of processing modules including a processing module which processes image data for every second size different from the first size. The second pipeline processing unit includes, at a start, a change unit configured to acquire partial image data of the first size from the first pipeline processing unit and change the partial image data of the first size into partial image data of the second size.

Abstract: According to one embodiment, an image processing apparatus connectable to a main memory in which a plurality of pixel values of unconverted image is stored and a cache memory including a plurality of cache blocks. The apparatus includes a counter, a coordinate determination module, a memory controller, a cache access module, a pixel value calculator, and an output module. The counter determines a coordinate within converted image according to a predetermined execution sequence. The coordinate determination module determines a plurality of coordinates within unconverted image of the pixel values of unconverted image necessary to calculate a pixel value of converted image corresponding to the coordinate within converted image. The memory controller transfers the pixel values of unconverted image stored in the main memory to the cache blocks corresponding to each of the coordinates within unconverted image.

Abstract: Provided herein is a method for implementing antialiasing including independently operating different portions of a graphics pipeline at different sampling rates in accordance with pixel color details.

Abstract: Cell phones and other portable devices are equipped with a variety of technologies by which existing functionality is improved, and new functionality is provided. Some aspects relate to imaging architectures, in which a cell phone's image sensor is one in a chain of stages that successively act on instructions/data, to capture and later process imagery. Other aspects relate to distribution of processing tasks between the device and remote resources (“the cloud”). Elemental image processing, such as filtering and edge detection—and even some simpler template matching operations—may be performed on the cell phone. Other operations are referred out to remote service providers. The remote service providers can be identified using techniques such as a reverse auction, through which they compete for processing tasks. Other aspects of the disclosed technologies relate to visual search capabilities, and determining appropriate actions responsive to different image inputs.

Abstract: To realize effective load distribution and improve the performance in image formation processing, an image processing apparatus includes a first image processing unit configured to perform image processing on a drawing area, a second image processing unit configured to be differentiated from the first image processing unit, a load analysis unit configured to analyze a composition processing load of an object in the drawing area, a rotational angle analysis unit configured to analyze a rotational angle of the object in the drawing area, and a load distribution determination unit configured to determine whether to distribute a part of image formation processing to be applied on the drawing area from the first image processing unit to the second image processing unit based on the analyzed composition processing load of the object and the analyzed rotational angle of the object.

Abstract: In one respect, provided are systems, methods and techniques in which local regions within an image are processed to provide fuzzy classification scores, which are calculated by determining changes in pixel values along a number of different directions. The resulting fuzzy classification scores are then used to detect or identify edge-containing or texture-containing regions, or to otherwise process the image regions differentially according to their fuzzy classification score. In another respect, provided are systems, methods and techniques for differential processing of different areas in an image. The differential processing in this case is based on calculated measures of local activity, which indicate features in corresponding local regions, and also based on calculated measures of local pixel-value variations, which indicate an amount of variation in pixel values across the corresponding local regions.

Abstract: Methods and systems for processing image data on a per tile basis in an image sensor pipeline (ISP) are disclosed and may include communicating, to one or more processing modules via control logic circuits integrated in the ISP, corresponding configuration parameters that are associated with each of a plurality of data tiles comprising an image. The ISP may be integrated in a video processing core. The plurality of data tiles may vary in size. A processing complete signal may be communicated to the control logic circuits when the processing of each of the data tiles is complete prior to configuring a subsequent processing module. The processing may comprise one or more of: lens shading correction, statistics, distortion correction, demosaicing, denoising, defective pixel correction, color correction, and resizing. Each of the data tiles may overlap with adjacent data tiles, and at least a portion of them may be processed concurrently.

Abstract: An image forming apparatus includes a renderer configured to render a one page amount of image data based on intermediate data generated by either a first execution unit or a second execution unit, a printer engine configured to form image data of a page rendered by the renderer on a recording medium, and after forming the image data, stop each unit in the engine when there is no image data formation instruction corresponding to a next page of the page even after a cycle down time limit has elapsed, and a request unit configured to, during generation of intermediate data of a predetermined page by the first execution unit, request an extension of the cycle down time limit set in the printer engine based on a number of pages of rendered image data corresponding to intermediate data of pages following the predetermined page.

Abstract: Systems and methods are disclosed for video processing modules. More specifically a network is disclosed for processing data. The network comprises a register DMA controller adapted to support register access and at least one node adapted to the data. At least one link communicates with the node, and is adapted to transmit data and at least one network module communicates with at least the link, and is adapted to route data to at least the link.

Abstract: A reception processing unit provided in a document processing system receives a document data processing request from a user device. A division processing unit divides document data corresponding to the processing request and generates divided document data. A document processing unit performs document processing for the divided document data, and a coupling processing unit combines the document-processed divided document data. A resource management unit increases or decreases the number of the division processing units, the document processing units, and the coupling processing units in response to the processing status of each thereof.

Abstract: An image processor comprises a plurality of processing modules coupled together in series. Each of at least two of the processing modules includes an image data input to receive at least one of i) an original image or ii) image data output by a previous processing module in the series. Each of the at least two of the processing modules also includes a processing unit configured to i) detect that image data is to be generated and ii) process image data received via the at least one image data input to generate image data. Each of the at least two of the processing modules also includes a memory to store image data generated by the processing unit.

Abstract: Image descriptor quantization technique embodiments are presented which quantize an image descriptor defined by a vector of number elements. This is generally accomplished by lowering the number of bits per number element to a prescribed degree. The resulting quantized image descriptor exhibits minimal loss of matching reliability while at the same time reducing the amount of storage space needed to store the descriptor in a database. Lowering the number of bits per number element also allows for increased matching speed.

Abstract: A media processing system and device with improved power usage characteristics, improved audio functionality and improved media security is provided. Embodiments of the media processing system include an audio processing subsystem that operates independently of the host processor for long periods of time, allowing the host processor to enter a low power state while the audio data is being processed. Other aspects of the media processing system provide for enhanced audio effects such as mixing stored audio samples into real-time telephone audio. Still other aspects of the media processing system provide for improved media security due to the isolation of decrypted audio data from the host processor.

Abstract: Techniques are provided to implement line based processing of thermal images and a flexible memory system. In one example, individual lines of a thermal image frame may be provided to an image processing pipeline. Image processing operations may be performed on the individual lines in stages of the image processing pipeline. A memory system may be used to buffer the individual lines in the pipeline stages. In another example, a memory system may be used to send and receive data between various components without relying on a single shared bus. Data transfers may be performed between different components and different memories of the memory system using a switch fabric to route data over different buses. In another example, a memory system may support data transfers using different clocks of various components, without requiring the components and the memory system to all be synchronized to the same clock source.

Abstract: Embodiments of the present invention provide a system for performing image conversion operations. The system starts by receiving a request from a client for one or more pixel buffers containing a pixel-formatted, cropped, geometrically transformed, and/or color matched version of an image representation. The system then determines if a provider can provide the one or more pixel buffers. If so, the system calls the provider to generate the one or more pixel buffers containing the pixel-formatted, cropped, geometrically transformed, and/or color matched version of the image representation. Otherwise, the system calls the provider to generate one or more intermediate pixel buffers, generates a sequence of converters for converting the one or more intermediate pixel buffers, and calls the sequence of converters to generate the one or more pixel buffers containing the pixel-formatted, cropped, geometrically transformed, and/or color matched version of the image representation.

Abstract: Assets of raw geo-located imagery can be divided into tiles and coverage masks can be generated for each tile. For each tile, fragments of pixels from coverage masks of neighboring tiles can be extracted and tagged. The fragments can be sorted and stored in a data structure so that fragments having the same tag can be grouped together in the data structure. The fragments can be used to feather the coverage mask of the tile to produce a blend mask. Multi-resolution imagery and mask pyramids can be generated by extracting fragments from tiles and minified (e.g., down-sampled). The minified fragments can be tagged (e.g., by ancestor tile name), sorted and stored in a data structure, so that fragments having like tags can be stored together in the data structure. The fragments can be assembled into fully minified tiles for each level in the pyramid.

Abstract: One embodiment of the present invention sets forth a technique for dynamically specifying a texture header and texture sampler using an index. The index corresponds to a particular register value that may be static or computed during execution of a shader program. Any texture operation instruction may specify an index value for each of the texture header and the texture sampler.

Abstract: Techniques are disclosed relating to generating generic labels, translating generic labels to image pipeline-specific labels, and automatically adjusting images. In one embodiment, generic labels may be generated. Generic algorithm parameters may be generated based on training a regression algorithm with the generic labels. The generic labels may be translated to pipeline-specific labels, which may be usable to automatically adjust an image.

Abstract: Methods and apparatuses for scheduling and storing media creation are described. Methods and apparatuses for rendering a plurality of vector graphic objects on a display are also described.

Abstract: Systems and methods are disclosed for video processing modules. More specifically a network is disclosed for processing data. The network comprises a register DMA controller adapted to support register access and at least one node adapted to the data. At least one link communicates with the node, and is adapted to transmit data and at least one network module communicates with at least the link, and is adapted to route data to at least the link.

Abstract: A print-document conversion apparatus includes a conversion-module activation section that activates, as a process, a conversion module for performing conversion processing for converting print-document data which is described in a page description language and which includes units of processing into print-image data. The conversion module includes a thread activation part, an assigning part, and a shared cache. The thread activation part activates conversion processing threads. The assigning part assigns the units of processing to the conversion processing threads, and causes the conversion processing threads to perform processing on the units of processing. The shared cache is shared by the conversion processing threads. When a conversion result obtained by converting an object included in the units of processing is stored in the shared cache, each of the conversion processing threads obtains the stored conversion result instead of obtaining the conversion result by converting the object.

Abstract: In general, the present disclosure describes various techniques for programmable, pattern-based unpacking and packing of data channel information, including still image, video, and audio component data. One example device comprises a programmable processor having a plurality of processing pipelines. The processor is configured to receive pattern information that specifies a pattern for a plurality of input data components, the pattern information comprising a plurality of pattern elements that are each associated with one or more of the input data components, and each input data component being selected from a component group consisting of a still image data component, an audio data component, and a video data component. For example, the input data components may comprise pixel data components, such as color channels. The processor is further configured to provide each input data component to a selected processing pipeline of the processor in accordance with the pattern information.

Abstract: A circuit arrangement, program product and method stream level of detail components between hardware threads in a multithreaded circuit arrangement to perform physics collision detection. Typically, a master hardware thread, e.g., a component loader hardware thread, is used to retrieve level of detail data for an object from a memory and stream the data to one or more slave hardware threads, e.g., collision detection hardware threads, to perform the actual collision detection. Because the slave hardware threads receive the level of detail data from the master thread, typically the slave hardware threads are not required to load the data from the memory, thereby reducing memory bandwidth requirements and accelerating performance.

Abstract: Embodiments of the present application automatically utilize parallel image captures in an image processing pipeline. In one embodiment, image processing circuitry concurrently receives first image data to be processed and second image data to be processed, wherein the second image data is processed to aid in enhancement of the first image data.

Abstract: What is disclosed is a novel fault tolerant page parallel RIP system having a plurality of distributed RIP nodes and a method for robust recovery in the event of a fault having occurred on the system. In one embodiment, the present fault tolerant page parallel RIP system comprises at least a plurality of RIP nodes, a supervisor node, and a splitter node. The splitter receives a location of the job file and splits the job file into at least one original chunk. In formation sufficient to regenerate the original chunk in the event of a fault condition having occurred on the page parallel RIP system is stored. The splitter then sends the original chunk to a destination RIP node wherein the original chunk is RIP'ed into at least one page in print-ready form. The one page is the provided in print-ready form to an output subsystem. Various embodiments are disclosed.

Abstract: A method and an apparatus are provided for combining multiple independent tile-based graphic cores. An incoming geometry stream is split into a plurality of streams and sent to respective tile based graphics processing cores. Each one generates a separate tiled geometry list as described. These may be combined into a master tiling unit or, alternatively, markers may be inserted into the tiled geometry lists which are used in the rasterization phase to switch between tiling lists from different geometry processing cores.

Abstract: In this invention, scan conversion processing of changing the scan order for each block is used. Parallel scan conversion processing is executed if possible, thereby making the number of scan conversion target blocks per unit time larger than before. To do this, a scan status holding unit holds statistical information based on the appearance frequency values of coefficients in a block. A scan order holding unit holds coefficient position information in which the coefficient positions in a block are arranged based on the scan order. A parallel number determination unit determines the number of blocks processable in parallel based on the statistical information held in the scan status holding unit and supplies the result to a scan conversion unit as a control signal. If the control signal from the parallel number determination unit indicates parallel processing, the scan conversion unit executes scan conversion of two input blocks in parallel.