Abstract: In this invention, scan conversion processing of changing the scan order for each block is used. Parallel scan conversion processing is executed if possible, thereby making the number of scan conversion target blocks per unit time larger than before. To do this, a scan status holding unit holds statistical information based on the appearance frequency values of coefficients in a block. A scan order holding unit holds coefficient position information in which the coefficient positions in a block are arranged based on the scan order. A parallel number determination unit determines the number of blocks processable in parallel based on the statistical information held in the scan status holding unit and supplies the result to a scan conversion unit as a control signal. If the control signal from the parallel number determination unit indicates parallel processing, the scan conversion unit executes scan conversion of two input blocks in parallel.

Abstract: A device and method for converting one stereoscopic format into another. A software-enabled matrix is used to set forth predefined relationships between one type of format as an input image and another type of format as an output image. The matrix can then be used as a look-up table that defines a correspondence between input pixels and output pixels for the desired format conversion.

Abstract: According to one embodiment, a parallax image generating apparatus includes a deriving unit, a generating unit, a first calculating unit, a setting unit, a searching unit, and an interpolating unit. The deriving unit derives a parallax vector corresponding to a first pixel from the input image and depth information associated with the first pixel. The generating unit generates an intermediate image. The first calculating unit calculates first weights for respective pixels of a parallax image. The setting unit sets one or more candidate blocks near a shade-forming-area pixel of the intermediate image, and sets a reference block among one or more candidate blocks. The searching unit searches a target block similar to the reference block in the input image and/or the intermediate image. The interpolating unit interpolates a pixel value of the shade-forming-area pixel.

Abstract: An image processing system includes a first image processor that reads out a first image written in a main memory to apply a first process to the first image and write in the main memory as a second image, a second image processor that reads out a second image written in the main memory to apply a second process to the second image and write in the main memory as a second image, and an address snooping apparatus that snoops an address of the image written in the main memory to start the first process when the address is indicated to a previously set first value and start the second process when the address is indicated to a previously set second value, effectively enabling synchronization between a process by a CPU or a special purpose processor and a data delivery/receipt process between pipeline stages.

Abstract: According to an embodiment, a compiling device compiling a source program written so as to use a frame memory includes a processing delay amount calculator configured to calculate respective processing delay amounts between a plurality of process tasks in the source program on the basis of processing states of pieces of data processed by the process tasks. The compiling device also includes a line memory amount calculator configured to calculate respective line memory sizes required for each of the process tasks on the basis of an access range of a frame memory from which the process task reads data and an instruction code converter configured to convert the plurality of process tasks to instruction codes executable in a pipeline on the basis of the processing delay amounts and the line memory sizes.

Abstract: A multithreaded rendering software pipeline architecture utilizes a rolling texture context data structure to store multiple texture contexts that are associated with different textures that are being processed in the software pipeline. Each texture context stores state data for a particular texture, and facilitates the access to texture data by multiple, parallel stages in a software pipeline. In addition, texture contexts are capable of being “rolled”, or copied to enable different stages of a rendering pipeline that require different state data for a particular texture to separately access the texture data independently from one another, and without the necessity for stalling the pipeline to ensure synchronization of shared texture data among the stages of the pipeline.

Abstract: An edge detection filter comprising an array of filter coefficients having an odd number of rows and columns, a first set of zero coefficients extending along a direction traversing the array through a center position to form a first and second side, a second set of positive coefficients extending away from the direction on the first side, and a third set of negative coefficients extending away from the direction on the second side.

Abstract: Methods and apparatus provide for an output manager that receives an identification of content. The output manager receives an identification of a set of filters to be applied to the content where each filter in the set of filters defines a sequence of steps to be applied to the content. The output manager identifies shared steps that are common to the sequence of steps of at least two filters in the set of filters. Thus, upon a first execution of a shared step in a sequence of steps by a filter, the output manager caches output of the first execution to be used in place of execution of that shared step in a sequence of steps of another filter in the set of filters.

Abstract: An image forming apparatus including: a video memory; a load management unit that loads page data on a print image into the video memory page by page; a print engine that performs printing using the page data stored in the video memory; and a main management unit that, when printing of a page is completed as part of an electronic sort process, causes the video memory to retain the page data if there is a subsequent page to be printed using the same page data as that on the page, and deletes the page data from the video memory if there is no subsequent page to be printed using the same page data as that on the page.

Abstract: A method and an apparatus are provided for combining multiple independent tile based graphic cores. An incoming geometry stream is split into a plurality of streams and sent to respective tile based graphics processing cores. Each one generates a separate tiled geometry lists. These may be combined into a master tiling unit or, alternatively, markers may be inserted into the tiled geometry lists which are used in the rasterization phase to switch between tiling lists from different geometry processing cores.

Abstract: An example embodiment includes a processor module, a pipe analyzer and a central processing unit. The processor module extracts a plurality of components from an input bit stream by extracting predetermined n-bits at a time from the input bit stream and analyzing the n-bits for components. The central processing unit has at least two pipelines for receiving the components derived from the input bit stream. The pipe analyzer is coupled between the processor module and the central processing unit for analyzing the components of the input bit stream and directing each of the components into a suitable pipeline of the central processing unit based on the analysis the pipe analyzer.

Abstract: Systems and methods are disclosed for video processing modules. More specifically a network is disclosed for processing data. The network comprises a register DMA controller adapted to support register access and at least one node adapted to the data. At least one link communicates with the node, and is adapted to transmit data and at least one network module communicates with at least the link, and is adapted to route data to at least the link.

Abstract: A system and method for reducing the data-rate when processing video, particularly wide-angle video.

Abstract: The present approach increases bandwidth by performing at least two functions at the pre-processing level. Specifically, under the present approach, program code is structured so that the segmentation and binarization functions/modules (and optionally a blob analysis function/module) are merged into a single module to reduce memory bandwidth. In addition, each image frame is segmented into a plurality of partitions (e.g., vertical strips) to enhance the reusability of the image data in LS already fetched from main memory. Each partition is then processed by a separate one of a plurality of processing engines, thereby increasing the utilization of all processing engines and allowing the processing engines to maintain good bandwidth.

Abstract: An image processing apparatus which applies processes to input image data is disclosed. The image processing apparatus includes a first processing section which applies processes to the image data by a specific calculating device, and a second processing section which applies processes to the image data by a general-purpose calculating program. The input image data are multilevel image data. The first processing section includes an image data binarizing unit for forming binary image data from the multilevel image data, and a multilevel image data processing section for applying a calculation process to the multilevel image data. The second processing section includes a binary image data processing section for applying a calculation process to the binary image data formed by the image data binarizing unit.

Abstract: Image descriptor quantization technique embodiments are presented which quantize an image descriptor defined by a vector of number elements. This is generally accomplished by lowering the number of bits per number element to a prescribed degree. The resulting quantized image descriptor exhibits minimal loss of matching reliability while at the same time reducing the amount of storage space needed to store the descriptor in a database. Lowering the number of bits per number element also allows for increased matching speed.

Abstract: An image processing apparatus has a plurality of serially connected image processing blocks for sequentially processing image data input thereto. After a first command for controlling the plurality of image processing blocks and image data to be processed by the plurality of image processing blocks are output to the leading image processing block, a second command indicating end of this output is output to the leading image processing block. When the second command is output from a final image processing block, the next first command and image data are output to the leading image processing block.

Abstract: An image processor includes a frequency transform unit performing frequency transform on a first pixel block as a target block, and a pre-filter performing prefiltering with a region which overlaps with plural unit regions for processing by the frequency transform unit as a unit region for processing, before frequency transform is performed. The pre-filter performs prefiltering on a second pixel block being a predetermined number of pixels each larger horizontally and vertically than the first pixel block as a target block. The pre-filter performs prefiltering sequentially on a plurality of second pixel blocks aligned horizontally. The number of pixel signals in a vertical direction within a group of pixel signals continuously inputted to the pre-filter for prefiltering is equal to the number of rows in the second pixel block.

Abstract: An overall processing time to rasterize, at the first device, the electronic document to be rendered is computed. Also, a rendering time to render, at the first device, the electronic document to be rendered is computed. When the overall processing time to rasterize at the first device is greater than the rendering time to render at the first device, the electronic document to be rendered is parsed into a first document and sub-documents. A productivity capacity of each node is determined, the productivity capacity being a measured of the processing power of the node and the communication cost of exchanging information between the first device and the node. A sub-document is rasterized at a node when a productivity capacity of the node reduces the processing time to rasterize the electronic document to be rendered to be less than the computed overall processing time.

Abstract: A software architecture based on a concept called “pipes and filters” is applied to an image processing apparatus, thereby simplifying the customization, expansion, etc., of functions. In addition, filters are combined together using a description table in which the combination of the filters is described so as to construct a job, thereby further simplifying the customization, expansion, etc., of functions.

Abstract: A user specifies a group by a user-defined query. An input order is assured among data of a same group. By outputting data belonging to a same group from the same node, an order inputted for a necessary portion is assured. By outputting data belonging to different groups from another node, processing in plural nodes is achieved to avoid reduction in performance.

Abstract: An image processing apparatus has a plurality of serially connected image processing blocks for sequentially processing image data input thereto. After a first command for controlling the plurality of image processing blocks and image data to be processed by the plurality of image processing blocks are output to the leading image processing block, a second command indicating end of this output is output to the leading image processing block. When the second command is output from a final image processing block, the next first command and image data are output to the leading image processing block.

Abstract: A system and method for pipeline image processing is disclosed. In one example embodiment the one or more swaths of the image may be received on the server from a client device connected to the server via a network. The received one or more swaths are processed on a swath by swath basis to obtain one or more image quality parameters. The obtained one or more image quality parameters are compared with a predetermined threshold level. The obtained one or more image quality parameters may be sent to the client device for further processing of the image based on the obtained one or more image quality parameters.

Abstract: An image pipeline device is used for processing an image. The device comprises an external memory, a direct memory access (DMA), an image pipeline controller, and a filter layer. The image pipeline controller comprises a physical memory allocation (PMA) having a physical buffer unit, and a first array controller for configuring the physical buffer unit as a corresponding first logic buffer unit. The filter layer comprises a first filter set electrically connected to the first array controller correspondingly and having a plurality of filters. The first filter set receives the image through the first array controller, processes the image selectively according to the first logic buffer unit and the filters, and stores the processed image back to the external memory through the DMA.

Abstract: An efficient method and system to enhance digital acquisition devices for analog data is presented. The enhancements offered by the method and system are available to the user in local as well as in remote deployments yielding efficiency gains for a large variety of business processes. The quality enhancements of the acquired digital data are achieved efficiently by employing virtual reacquisition. The method of virtual reacquisition renders unnecessary the physical reacquisition of the analog data in case the digital data obtained by the acquisition device are of insufficient quality. The method and system allows multiple users to access the same acquisition device for analog data. In some embodiments, one or more users can virtually reacquire data provided by multiple analog or digital sources. The acquired raw data can be processed by each user according to his personal preferences and/or requirements.

Abstract: A technique is provided for displaying pixels of an image at arbitrary subpixel positions. In accordance with aspects of this technique, interpolated intensity values for the pixels of the image are derived based on the arbitrary subpixel location and an intensity distribution or profile. Reference to the intensity distribution provides appropriate multipliers for the source image. Based on these multipliers, the image may be rendered at respective physical pixel locations such that the pixel intensities are summed with each rendering, resulting in a destination image having suitable interpolated pixel intensities for the arbitrary subpixel position.

Abstract: An image processing apparatus for processing image data by a plurality of pipeline-connected processing modules is provided. The apparatus includes a first pipeline processing unit configured to include a plurality of processing modules including a processing module which processes image data for every first size; and a second pipeline processing unit configured to be branched from the first pipeline processing unit and include a plurality of processing modules including a processing module which processes image data for every second size different from the first size. The second pipeline processing unit includes, at a start, a change unit configured to acquire partial image data of the first size from the first pipeline processing unit and change the partial image data of the first size into partial image data of the second size.

Abstract: A processing device has plural processing modules executing a processing; and plural connectors each having a linking section, an associating section, and a controller. The linking section is able to link with at least one other connector at an input side or an output side. The associating section associates the connector with one of the processing modules. In accordance with a linked state, the controller controls the processing module associated by the associating section.

Abstract: An edge detection filter comprising an array of filter coefficients having an odd number of rows and columns, a first set of zero coefficients extending along a direction traversing the array through a center position to form a first and second side, a second set of positive coefficients extending away from the direction on the first side, and a third set of negative coefficients extending away from the direction on the second side.

Abstract: A circuit arrangement and method support a multithreaded rendering architecture capable of dynamically routing pixel fragments from a pixel fragment generator to any pixel shader from among a pool of pixel shaders. The pixel fragment generator is therefore not tied to a specific pixel shader, but is instead able to utilize multiple pixel shaders in a pool of pixel shaders to minimize bottlenecks and improve overall hardware utilization and performance during image processing.

Abstract: An image processing device for curbing memory expansion and reducing costs while securing programming freedom by a small programmable data processing unit. A plurality of process programs and process parameters thereof, to be sequentially executed in a data processing unit, are stored beforehand in a data memory. In the data processing unit is repeated, as many times as there are process programs in the data memory, an operation in which image data to be processed are divided into plural respective divided image data as process units, and a process program, process parameters thereof and divided image data are read from the data memory, the process program is executed on the divided image data referring to the process parameters thereof, and then the divided image data after processing, the executed process program and the process parameters thereof are written back to the data memory.

Abstract: A processing device has plural processing modules executing a processing; and plural connectors each having a linking section, an associating section, and a controller. The linking section is able to link with at least one other connector at an input side or an output side. The associating section associates the connector with one of the processing modules. In accordance with a linked state, the controller controls the processing module associated by the associating section.

Abstract: In a first image processing apparatus, a first image processing unit 104 applies image processing to video content stored in a first storage unit. At this time, the first image processing unit stores information relating to detail and progress of the applied image processing in an image processing information storage unit as image processing information. In a case in which the first image processing unit interrupts the image processing being applied and the interrupted image processing is taken over and executed by a second image processing apparatus, the partially processed video content and the corresponding image processing information are transferred to the second image processing apparatus.

Abstract: In an embodiment, an apparatus includes a first processor that includes a first processor element. The apparatus also includes a second processor that includes a second processor element. The first processor is configured to transmit data to the second processor through a third processor, wherein no processor element within the third processor is configured to perform a process operation on the data as part of the transmission of the data from the first processor to the second processor.

Abstract: Circuits, methods, and apparatus that provide texture caches and related circuits that store and retrieve texels in a fast and efficient manner. One such texture circuit provides an increased number of bilerps for each pixel in a group of pixels, particularly when trilinear or aniso filtering is needed. For trilinear filtering, texels in a first and second level of detail are retrieved for a number of pixels during a clock cycle. When aniso filtering is performed, multiple bilerps can be retrieved for each of a number of pixels during one clock cycle.

Abstract: Systems and methods of encoding a video signal that includes a succession of images are disclosed. A system may include a plurality of independently programmable processing elements (PEs), an input interface device adapted to receive, buffer, and divide the input video signal in a manner appropriate to the plurality of PEs, and an output interface device adapted to receive encoded bitstreams generated by the plurality of PEs and provide an encoded video signal. Each PE is configurable to carry out the steps of a selected encoding algorithm and includes a digital processor and a memory in communication with the digital processor. The memories are independently accessible, and PEs communicate with each another during the encoding.

Abstract: An image processing system and method, in which a plurality of image processing operations are dynamically controlled based on dynamically changing tag data associated with pixels being processed.

Abstract: One embodiment of the present invention sets forth a technique to setup efficient bump mapping using a geometry shader. This approach uses a vertex shader, a primitive assembly unit, and a geometry shader. The vertex shader performs vertex operations, such as calculating a per-vertex normal vector, and emits vertex data. The primitive assembly unit processes the vertex data and constructs primitives. Each primitive includes a series of one or more vertices, each of which may be shared amongst multiple primitives, and state information defining the primitive. The geometry shader processes each primitive, calculating an object-space to texture-space mapping for each vertex of the primitive and, subsequently, using this mapping to transform the object-space view vector and the object-space light vectors associated with each vertex of the primitive to texture-space equivalents.

Abstract: Disclosed is a stereo image matching method for re-creating 3-dimensional spatial information from a pair of 2-dimensional images. The conventional stereo image matching method generates much noise from a disparity value in the vertical direction, but the present invention uses disparity information of adjacent image lines as a constraint condition to eliminate the noise in the vertical direction, and compress the disparity by using a differential coding method to thereby increase a compression rate.

Abstract: The present invention is a method, system and apparatus for componentized application sharing. The system can include a multiplicity of different pluggable image processing modules. Each of the different pluggable image processing modules can conform to a single interface expected by the application sharing module. Additionally, a communicative coupling can be provided between the application sharing module and a selected one of the different image compression modules.

Abstract: Systems and/or methods are described that enable multi-threaded multimedia processing. These systems and/or methods may, in some embodiments, allocate threads for components of a multimedia pipeline based on input/output characteristics of the components. These systems and/or methods may also allocate threads and priorities for those threads based on a relative importance given components of two or more multimedia pipelines.

Abstract: This document discusses, among other things, systems and methods that track overall time for processing operations such that the processing time can be shared among the resources in an efficient manner. Processing time can be shifted to image processing where the time will provide the most benefit to image quality. Moreover, access time from one process is banked to be used by a subsequent process or on a subsequent group of pixels. This document also discusses, among other things, systems and methods that provide additional processing power on an as needed basis. In an example, a processing stage and its controller are outside the normal pixel processing flow path. When it is determined that additional processing is required, the processing stage and its controller are activated to perform the additional processing.

Abstract: Performing a hash algorithm in a processor architecture to alleviate performance bottlenecks and improve overall algorithm performance. In one embodiment of the invention, the hash algorithm is pipelined within the processor architecture.

Abstract: An image processing system and method, in which an image processing operation is performed on a pixel or pixels by selecting and applying one of a plurality of implementations of the image processing operation. The plurality of implementations is varied from time to time, such that one or more of the implementations is replaced with a different implementation or implementations.

Abstract: A pipeline video decoder and decompression system handles a plurality of separately encoded bit streams arranged as a single serial bit stream of digital bits and having separately encoded pairs of control codes and corresponding data carried in the serial bit stream. The pipeline system employs a plurality of interconnected stages to decode and decompress the single bit stream, including a start code detector. When in a search mode, the start code detector searches for a specific start code corresponding to one of multiple compression standards. The start code detector responding to the single serial bit stream generates control tokens and data tokens. A respective one of the tokens includes a plurality of data words. Each data word has an extension bit which indicates a presence of additional words therein. The data words are thereby unlimited in number.

Abstract: An image processing apparatus includes an information processor that is controlled by a general-purpose operating system, and an image processor. The information processor performs a function in a category different from an image processing function performed in the image processor. As a result, a general purpose application program can be used as software for making effective use of the image processing function. Therefore, it is possible to facilitate development of the software to allow the image processing apparatus to perform the function in a category different from the image processing function performed in the image processor, in addition to the image processing function as a basic function.

Abstract: An integrated image processor implemented on a substrate is disclosed. An input interface is configured to receive pixel data from two or more images. A pixel handling processor disposed on the substrate is configured to convert the pixel data into depth and intensity pixel data. In some embodiments, a foreground detector processor disposed on the substrate is configured to classify pixels as background or not background. In some embodiments, a projection generator disposed on the substrate is configured to generate a projection in space of the depth and intensity pixel data.

Abstract: Disclosed is a stereo image matching method for re-creating 3-dimensional spatial information from a pair of 2-dimensional images. The conventional stereo image matching method generates much noise from a disparity value in the vertical direction, but the present invention uses disparity information of adjacent image lines as a constraint condition to eliminate the noise in the vertical direction, and compress the disparity by using a differential coding method to thereby increase a compression rate.

Abstract: This document discusses, among other things, systems and methods that track overall time for processing operations such that the processing time can be shared among the resources in an efficient manner. Processing time can be shifted to image processing where the time will provide the most benefit to image quality. Moreover, access time from one process is banked to be used by a subsequent process or on a subsequent group of pixels. This document also discusses, among other things, systems and methods that provide additional processing power on an as needed basis. In an example, a processing stage and its controller are outside the normal pixel processing flow path. When it is determined that additional processing is required, the processing stage and its controller are activated to perform the additional processing.

Abstract: A digital watermark detector comprises a memory buffer for receiving an incoming stream of data. The detector includes a registration module for determining registration of embedded data in blocks of the incoming stream of data, and logic for re-using the registration for subsequent blocks of the incoming stream of data to detect machine readable signals. Another digital watermark detector comprises a message reader for extracting message estimates from blocks of media signal data and a decoder for combining the extracted message estimates and decoding a message from the combined message elements. Another digital watermark detector comprises a memory buffer and pipelined watermark processor segments. The segments each perform a different watermark detector operation. These segments concurrently operate on different data segments of the block of data in a processing pipeline.