Abstract: Filing the documents prepared by a computer (HOST) without a detour via a computer printout, by virtue of the fact that, as in the case of driving a printer, the printing data (SPDS) which can be retrieved via a printer connection interface (CH) of the computer (HOST) is converted into a pixel data stream (PIX-DAT). In parallel therewith text information and bar codes are filtered out of the printing data stream and neutralized and converted into an index data stream (IND-DAT). The two data streams are then logically synchronized and fed to the filing data carrier (ARCHIV). Designing the apparatus as a self-contained apparatus (APALINK) or as a combined apparatus having a printer (PRINTER) and an ancillary device (PC), it also is possible for the ancillary device to be an integral component of the printer. Furthermore, it is possible for the filing to be performed in parallel with printing out or without simultaneous printing out.

Abstract: A method and apparatus for reading data collection symbols initially samples and preferably stores an image of light reflected from the symbol. An initial portion of the symbol in the stored image is located and multiple reading techniques are performed based on the stored symbol image and the located portion. Several output signals are produced from the multiple reading techniques, and one of the output signals is selected as a decoded signal that represents the data encoded in the symbol. The multiple reading techniques can be multiple reading methods performed substantially simultaneously with each other (on one or more processors), a single method performed multiple times and at multiple locations within the stored symbol image, or each reading method can be broken down into constituent modules, and like modules grouped into sets.

Abstract: A multiple parallel digital signal processor having a large number of bit processing processor elements arranged in one-dimensional array is treated as a processor block, and a plurality of the processor blocks are connected in sequence, while removing redundancy, to form a processor block column. A plurality of processor blocks are connected in sequence such that a processor block at a subsequent stage is supplied either with output of a processor block at a previous stage or with input data, and an output of any of the processor blocks is delivered as a final output, thereby making it possible to realize a signal processing apparatus which has high performance, versatility, and simple configuration.

Abstract: The present invention provides an image forming apparatus including a scanner for reading image data from an original sheet, a first filter for filtering the image data, a second filter provided in parallel with the first filter, and different from the first filter, adding circuit means for adding up the outputs from these filters, and a function for forming an image on the basis of the result of addition

Abstract: In an image clustering apparatus for classifying an image into plural clusters, modification of cluster parameter is executed by parallel processing as well as parallel processing of comparison of likelihood.

Abstract: A system and method is disclosed that compresses and decompresses images. The compression system and method includes an encoder which compresses images and stores such compressed images in a unique file format, and a decoder which decompresses images. The encoder optimizes the encoding process to accommodate different image types with fuzzy logic methods that automatically analyze and decompose a source image, classify its components, select the optimal compression method for each component, and determine the optimal parameters of the selected compression methods. The encoding methods include: a Reed Spline Filter, a discrete cosine transform, a differential pulse code modulator, an enhancement analyzer, an adaptive vector quantizer and a channel encoder to generate a plurality of data segments that contain the compressed image. The plurality of data segments are layered in the compressed file to optimize the decoding process.

Abstract: A process and apparatus is described to improve error diffusion halftone imaging by reducing the amount of time necessary to perform the halftoning process. This processing time reduction is produced without sacrificing the quality of the output binary images by achieving parallelism of error diffusion within an image row. The method works by cutting each image row into a number of segments and error diffusing these segments in parallel. It utilizes two different error diffusion filters: the cut filter for the pixel just before the cuts and the normal filter for the rest of the pixels. Dependencies among the segments is eliminated by ensuring that the cut filter has zero weight for the right neighboring pixel. The normal filter can be any filters that can show excellent quality of the output binary images. Banding artifacts along the cuts are minimized through careful design of the cut filter.

Abstract: A multi-modal method for locating objects in images wherein a tracking analysis is first performed using a plurality of channels which may comprise a shape channel, a color channel, and a motion channel. After a predetermined number of frames, intermediate feature representations are obtained from each channel and evaluated for reliability. Based on the evaluation of each channel, one or more channels are selected for additional tracking. The results of all representations are ultimately integrated into a final tracked output. Additionally, any of the channels may be calibrated using initial results obtained from one or more channels.

Abstract: An image processing system and method which may be used for standalone deconvolution or, alternatively, may be employed as a staring point for very rapid convergence with subsequent use of prior art deconvolution methods. Processing speed is improved because the sequential requirement of the CLEAN method is relaxed. Fractional removal of noise is accomplished for multiple features within the image during the processing of a single subtractive iteration. Thus the number of iterations can be significantly reduced allowing dramatic reduction of the subtractive stage and a resulting increase in overall processing speed.

Abstract: A data coding device codes input object color pixel data into coded data. The data coding device includes a parallel/serial converter that converts the object color pixel data composed of parallel data of multiple bits into serial data, a state signal generator that generates a states signal for each bit of the serial data and a prediction device which groups each bit of the serial data based on the state signal, and an arithmetic calculator that converts the color pixel data into coded data based on the data received from the prediction device. A corresponding data decoding device is also disclosed.

Abstract: Methods, apparatus and computer program products for utilizing a plurality of processing elements to evaluate a linear expression of the form Ax+By+C wherein x and y are coordinates of pixels in a screen. X and y values are assigned to each of the plurality of processing elements and the plurality of processing elements are provided a plurality of multiples of at least one coefficients of the linear expression. The processing elements select from the plurality of multiples of at least one of the coefficients provided at least one multiple of a coefficient associated with the x and y values assigned to the processing element. The processing elements then evaluate the expression Ax+By+C based on the assigned x and y values and the selected multiple.

Abstract: This invention relates to a data conversion system utilizing a cell comprising: a shift register supplied with a plurality of data for sequentially shifting the data; a memory, supplied with data in a certain area of the shift register as addresses, storing data for outputting a predetermined value when data in the certain area are in a pattern to determine the value of the center dot of the area, or for outputting an instruction signal for determining the value of the center dot according to dot data outside of the certain area when data in the certain area are not in a pattern to determine the value of the center dot of the area; and an operation unit for selecting and outputting said predetermined value from said memory when no instruction signal is supplied from the memory and for outputting the value of the center dot by determining it from data outside the certain area per the instruction signal.

Abstract: In a system for processing and imaging documents to develop a stream of digital, video bit sets, each related to a different document is a passing array, this system including an arrangement for simultaneously compressing a number of said bit-sets for different document images and sending the results to output, this arrangement as comprising:a preprocessing stage for distributing each said bit set in a pair, of like parallel bit-compression paths, one, a Master path for half the bits in a set, the other a Slave path for the other half as controlled by The Master, with both input to a common buffer, each compression path being adapted to execute a first compression and then a conditional second compression when certain initial factors are indicated and to provide a real-time-compressed output to this buffer; andboth said compressions being performed on a single, two pass stage of a Histogram/Compressor printed circuit board.

Abstract: A method for decoding coded data is executed to use a decoder composed of plural decoding units, those units being parallel processors. The coded data is divided into a first and a second coded areas. A first decoding unit starts to decode the coded data from the head of the first coded area, that is, from the head of the overall coded data. A second processor starts the decoding process from the head of the second coded area, that is, from any location of code sequence from the head. If conflict takes place in the decoded data, the decoding device operates to repeat a trial-and-error operation for re-starting the decoding process from a new location close to the head of the second coded area. When the decoding process of the first decoding unit reaches the second coded area, if a right answer is found in the decoded result given by the second decoding process, it is picked up as the proper result.

Abstract: Consecutive pixel values are loaded into the fields of a register. The data stored in the register is then transformed by operating on the register with one or more instructions that treat multiple pixel values as if they were single values. In a preferred embodiment, subsampled motion estimation processing is implemented on SIMD architecture. Values for consecutive pixels are loaded into the 8-bit fields of a SIMD register with a single byte-based SIMD load instruction. The contents of the register are then processed by applying one or more word-based SIMD instructions to the register which treat the data in the registers as 16-bit values. This word-based processing preferably results in sums of squares of differences between reference and target pixels used in motion estimation processing. Although the byte-based SIMD load instruction loads unwanted pixels (i.e.

Abstract: In a printer driver 11, a source code for an image processing procedure called out by an application program 12 is generated. A grain size detection process 48 counts the number of procedures which have been called out and a parallelization position detection process 49 checks whether each procedure called out is attended with pixel generation or not and whether the procedure depends on the preceding procedure or not. While calling-out of procedures not dependent on the preceding procedure is continued, source codes for those procedures are accumulated in a buffer 60. Whenever a procedure attended with pixel generation is called out, the printer driver 11 outputs a set of source codes accumulated in the buffer 60 in a description of a complex sentence indicating a parallel processing unit in accordance with the grammar of a parallel sentence structure as long as the aforementioned count value reaches the grain size of a preliminarily set unit of parallel processing.

Abstract: The present invention is a super-scalar method and apparatus for the generation of halftone dot patterns in an image processing system. The super-scalar design employs at least one block of memory for the storage of at least one predetermined halftone dot pattern across a plurality of unique locations therein, and a sequencer for producing an index into said memory as a function of the position of the pixel along a scan line and the halftone dot characteristics. Also included is addressing circuitry for memory access control, to combine the index produced by said sequencer and a pixel value for the pixel to produce a memory address, the memory address being thereby employed to access one of said locations in memory and to cause said memory to output a signal representative of a portion of the halftone dot pattern stored at the unique addressed location.

Abstract: Processing a moving image such that, after an input video signal is supplied to an image inputter, the image inputter time-divisionally converts the input video signal to a digital signal and outputs a control signal such as a vertical synchronous signal. A multiplexer reads image data converted by the image inputter into the digital signal and stores them into a plurality of temporary storers unique for frames according to the control signal from the image inputter. The plurality of temporary storers are respectively connected with a plurality of processor elements which process the memory contents of the plurality of temporary storers and re-store the processing results back in the plurality of temporary storers. A multiplexer sequentially retrieves the memory contents from the plurality of temporary storers, and has an image outputter for converting a digital signal to a video signal output them.

Abstract: One page of image data is divided into six data streams of blocks data. First to sixth FIFO memories of a speed difference absorbing circuit absorb a difference between a transfer rate of the block data and a processing speed of the subsequent circuits. FIFO memories of a line delay circuit delay the respective block data such that delay times for the respective block data change step by step by a predetermined time. An order conversion circuit produces 4-line parallel image data by sequentially selecting the block data sent from the line delay circuit. Sync signals for the four respective lines are delayed step by step by a predetermined time.

Abstract: A method of processing a digital signal wherein multiple signal values are simultaneously operated upon in a single register. The register is not segmented in hardware, but is segmented by operation of a controlling computer software program. The controlling computer software arranges the digital signal in a computer memory in such a manner as to permit the register to be loaded with a plurality of digital samples, each having a precision less than the total precision available in the register. The method may include steps to partially compensate for errors introduced by carries from one segment of the register to another segment of the register, when necessary.

Abstract: Image data, read by an image reading device and binarized, is stored in a buffer memory by one scanning line. Then a compressive coding on the stored image data by one scanning line and a compressive coding on image data developed form codes, such as codes written in a page description language (PDL), or image data read from a predetermined memory are performed by a single encoder.

Abstract: An advanced manufacturing inspection system includes a database containing a rasterized reference image of the product inspected at the inspection resolution, allowing for accurate representation of shaped features. The full image is stored in the system database and is accessed and fed in a raster manner to an electronic registration subsystem which aligns the reference data to the incoming thresholded product inspection data. The aligned reference and inspection data are driven to all parallel defect detection channels. A classifier block selects the output of the desired channels for recording into a defect memory. Alternatively, the thresholding of the inspection gray scale signal is done after registration such that thresholding can be controlled by the reference data. The system is flexible in rendering abnormalities between reference and gray scale inspection images and functions independently of image resolution because the reference and inspection images are of the same resolution.

Abstract: A coprocessor in an image processing system is coupled to the bus to which a CPU and RAM holding image data are also coupled. The coprocessor extracts an input pixel stream corresponding to input images from selected bus transactions, performs computations on the input stream to produce output pixel streams corresponding to output images, and inserts the output pixel streams into selected CPU-to-memory bus transactions so that the memory stores the data. The CPU generates the selected bus transactions with specially marked address and/or control signals. The coprocessor includes a lookup table, and a first row delay. The row delay accumulates the three most recent rows of input pixels, which are sent to Sobel and rank processing sections for neighborhood processing. The results are thresholded and formatted, and are either output directly or passed through an additional pair of row delays to accumulate three rows of result data for neighborhood peak detection.

Abstract: A character recognition apparatus for recognizing characters in a document by sequentially detecting one-character portions of images in a document image and by recognizing the character images of the one-character portions detected. The character recognition apparatus includes a character detecting section for detecting an image of one character from the document image; a character recognizing section for recognizing the detected image of one character and outputting a character code; and a control section for effecting control such that the character image of one character recognized by the character recognizing means is stored in correspondence with the character code obtained as a result of recognition, a comparison is made between the stored character image and the image of a newly detected character, and the character-code stored in correspondence with the relevant character image is read as a result of recognition in a case where the similarity of the images is sufficiently large.

Abstract: An image processor comprising a plurality of processor elements each having a product sum calculating function. Input switching means are incorporated for selection of image data so that the desired data in an arbitrary processing step of any one processor element can be transferred to an arbitrary processing step of the other processor element. Each processor element includes a data writing line memory, a multiplier for multiplying the output data of the line memory, a register file for storing the multiplied output therein, and an accumulator for calculating the output of the register file. Pipeline processing of the data can be executed in such constitution, and due to the provision of the input switching means in the preceding stage of each processing circuit, the image data can be transferred between the processor elements to consequently realize enhanced general ability for the image processing.

Abstract: A motion detecting apparatus in which when pixels within a search range formed of a predetermined number of pixels and pixels within a reference data block the number of which is smaller than the predetermined number of pixels in the search range, are compared on the basis of the arrangement state thereof, a processing circuit processes sums of difference absolute values of respective pixels within the reference data block and corresponding pixels within the search range formed at every search range, to thereby detect a motion state on the basis of the sums. Respective pixels within the search range are input to the processing circuit at a set time and pixels within the search range are input to the processing circuit at the set time, thereby being sequentially processed with corresponding pixels within the data block.

Abstract: To make the architecture of an image processing module of a monochrome printing machine convertible to a full color printing machine, bypass circuits are included in the luminance processing circuit of the monochrome printing system. These bypass circuits are inserted between a conventional shading circuit and conventional two-dimensional filter and auto-segmentation circuit of the luminance image processing system and between a conventional brightness adjustment circuit and a conventional one-dimensional image processor/screening circuit of the luminance image processing system. This inclusion of bypass circuits enables a chroma processing circuit to be installed in parallel with the luminance processing to make the monochrome system convertible to a full color system. The converted full color system utilizes the luminance processing system of the monochrome system to realize fully color processed signals ready for transmission to a printing subsystem.

Abstract: A decoding processing is executed in a multiple processing at high speed with a simple construction or control in a manner such that the image memory 11 stores an input compressed code, the multiplexer 14 selects the compressed code shift circuit 12 or 13 where the compressed code is shifted, and the decoder 15 decodes the shifted compressed-code.

Abstract: In order to display continuous tone colour image on a discrete colour level display, methods of halftoning must be used. The high display rate of colour output devices means that serial methods of real time halftoning are difficult to use. A method and apparatus are disclosed for reducing the speed with which a halftoning method must be performed by performing the halftoning of an output image in parallel by simultaneously error diffusing more than one line of input at a time.

Abstract: An image processing system wherein for an inputted composite image composed of a line image and a dither image, both a line image processing and a dither image processing are carried out in parallel, and one of the processed results as selected in accordance with the image region discrimination result. The dither image processing is carried out through data conversion for calculating multivalued gray scale image from the inputted image data, gray scale data conversion for adjusting the gray scale image data so as to match an output device and obtaining such adjusted gray scale image data, and re-binarization for re-binarizing the gray scale image data after subjected to the gray scale conversion. The image region discrimination for discriminating if an image region is of a line image of a dither image is carried out based on a ratio of the number of black or white pixels within the region to the contour line length within the range.

Abstract: A VLSI structure and method for polygon recognition that identifies an unknown two dimensional contour as corresponding to one or more of a plurality of known two dimensional contours. The VLSI architecture comprises a systolic processing system comprising a plurality of matrix element processing elements (MEPEs), and an array of feasible match processing elements (FMPEs) interconnected with selected MEPEs and with each other in a predetermined configuration. The plurality of MEPEs receive inputs comprising pairs of edge length ratios and corresponding threshold values for consecutive edges of the unknown contour and for each of the known polygon contours. Each MEPE (i) receives edge length ratios and threshold values for a pair of edges of the unknown contour and a known polygon contour, (ii) determines a dissimilarity value for the pair of edges, and (iii) directs this value to a selected FMPE of the array.

Abstract: When determining areas, a data for determining area Ds, including bit data D.sub.0 which shows whether the area to be processed or not, is stored in a frame memory for determining area 5. When carrying out image processing, the frame memory 5 outputs the data Ds in synchronization with the output of image data D form a A/D converter 3. A gate 4 outputs the image data D only when the bit data D.sub.0 is a value [1] representing the area to be processed. In Synchronization with the output of the data D, bit sequence D.sub.1 .about.D.sub.n is output as the additional data regarding to the area. In an image processing system(not shown), although the image processing is carried out for the whole of a frame memory, the image data D is not supplied except for the area shown by the bit data D.sub.0 so as not to be carried out the image processing. Therefore, only for the area shown by the bit data D.sub.0, the image processing is carried out in accordance with the bit sequence D.sub.1 .about.D.sub.n.

Abstract: An image processing device including a blocking section for dividing an input image into a plurality of blocks each consisting of N1.times.N2 (N1, N2: positive integers) picture elements; a block attribute determining section for determining an attribute of each block, the attribute being defined as one of a flat portion having substantially no density variation in each block, a semi-flat portion having a binary density distribution in each block, and an edge portion having a steep density variation in each block; a first coding section for coding each block of the flat portion; a second coding section for coding each block of the semi-flat portion; a third coding section for predictively coding the picture elements in each block of the edge portion; a fourth coding section for coding the attribute determined by the block attribute determining section; and a code assembling section for assembling codes obtained by the first to fourth coding sections.

Abstract: A method and apparatus for implementing a weighted voting scheme for reading and accurately recognizing characters in a scanned image. A plurality of optical character recognition processors scan the image and read the same image characters. Each OCR processor outputs a reported character corresponding to each character read. For a particular character read, the characters reported by each OCR processor are grouped into a set of character candidates. For each character candidate, a weight is generated in accordance with a confusion matrix which stores probabilities of a particular OCR to identify characters accurately. The weights are then compared to determine which character candidate to output.

Abstract: In order to display a continuous tone colour image on a discrete colour level display, methods of halftoning must be used. The high display rate of colour output devices means that serial methods of real time halftoning are difficult to use. A method and apparatus is disclosed for reducing the speed with which a halftoning method must be performed by performing the halftoning of an output image by simultaneously dividing the input image into a number of areas and simultaneously halftoning the areas individually making special provisions for pixels located in the boarder regions of a given area.

Abstract: A light modulation device comprising a first transparent electrode layer, a photoconductive layer, a conductive electrode, a light modulation layer, and a second transparent electrode layer formed together in the preceding order, and characterized by the light modulation characteristic of the light modulation layer being a non-linear saturation function of an applied electrical field, and the conductive electrode comprising plural electrode patterns. The light modulation layer modulates the read light when the input light exceeds a specific threshold value wherein by forming the electrode pattern of the conductive electrode in the shape of the pattern to be extracted, the features of the input image corresponding to that shape can be quickly extracted.

Abstract: There is provided an image data partitioning circuit for use in a parallel image decoding system which is capable of a effective partitioning operation for a variable length coded image, thereby advantageously achieving a high speed decoding operation. The image data partitioning circuit comprises: N buffer, each coupled to the respective decoding module for storing a partitioned variable length coded image to be processes thereby, respectively; first detector for detecting a starting position of the horizontally sliced data and generating a starting position detection signal; second detector for detecting a vertical position of the horizontally sliced data and for generating a vertical position detection signal; and partitioning device responsive to the starting position detection signal and the vertical position signal for partitioning the variable length coded image and for sequentially coupled the partitioned data of the variable length coded image to the N buffers.

Abstract: The image data (BDAT) associated with a respective document are transmitted to one of a plurality of recognition units for processing in a recognition process comprising a plurality of partial processes. The allocation of the processing jobs and the monitoring of the time cycles of the recognition processes is performed by a control unit (AU), by mean of which a timer is triggered to set the processing time of the recognition process in a recognition unit (e.g. RUn), the value of which is compared with an expected value for the processing time of the currently running partial process. The partial process results from the processing status of the recognition unit which is determined by status information and can be called at any time.

Abstract: A character recognition method and apparatus realizes high-speed character recognition by using small capacity memories. A character in an original image is read as an input character pattern in an image input process. An n-th calculator 109 in a similarity calculation unit 6 inputs the input character pattern into an input pattern memory 110 and compares the input character pattern with a standard character pattern (.phi..sub.m : m=0,M) stored in a dictionary memory 101 sequentially, thus calculating similarities between the input character pattern and the respective standard character patterns. If a CPU 1 issues a similarity calculation request instruction while an n-th calculator 109 is operating, another one of the calculators in a standby status is used so that another similarity calculation can be performed while simultaneously avoiding access conflict in the memory 101.

Abstract: An area recognition apparatus is provided with a mark detecting device for detecting a mark portion drawn on an original document to designate a specific area, on the basis of image data read from an original document, crossing portion detecting device for detecting the portion where the mark portion crosses an image portion on the original document, on the basis of the image data, and a closed loop recognizing device for recognizing a closed loop formed by the mark portion and the crossing portion, on the basis of the results of detection by the mark portion detecting device and the crossing portion detecting device.

Abstract: An apparatus and method for processing video data for compression/decompression in real-time. The apparatus comprises a plurality of compute modules, in a preferred embodiment, for a total of four compute modules coupled in parallel. Each of the compute modules has a processor, dual port memory, scratch-pad memory, and an arbitration mechanism. A first bus couples the compute modules and a host processor. Lastly, the device comprises a shared memory which is coupled to the host processor and to the compute modules with a second bus. The method handles assigning portions of the image for each of the processors to operate upon.

Abstract: An image data processor including a plurality of unit processors and processes a block of image data using the unit processors in parallel. Allotment ratios corresponding to the unit processors are stored in an allotment memory, and each of the unit processors processes its allotment of the block of image data according to its allotment ratio, whereby the lengths of time needed to process the allotments are equalized. The allotment ratios can be updated from time to time regarding the actual results of the processing time of the unit processors, or regarding the content of the image (which can be detected by sampling a part of the image data) and the type of data processing.

Abstract: A system for performing parallel processing of digital data in order to compute numerical functions and extract characteristic information based on the digital data. After the digital data is processed by the parallel processing portion, a sequential processing portion rewrites the processing data according to a sequential processing operation so that operations such as thinning and labelling may be performed.