Abstract: An image processing system and method, in which a plurality of image processing operations are dynamically controlled based on dynamically changing tag data associated with pixels being processed.

Abstract: Disclosed is a stereo image matching method for re-creating 3-dimensional spatial information from a pair of 2-dimensional images. The conventional stereo image matching method generates much noise from a disparity value in the vertical direction, but the present invention uses disparity information of adjacent image lines as a constraint condition to eliminate the noise in the vertical direction, and compress the disparity by using a differential coding method to thereby increase a compression rate.

Abstract: Systems and/or methods are described that enable multi-threaded multimedia processing. These systems and/or methods may, in some embodiments, allocate threads for components of a multimedia pipeline based on input/output characteristics of the components. These systems and/or methods may also allocate threads and priorities for those threads based on a relative importance given components of two or more multimedia pipelines.

Abstract: To provide an image processing technique compatible with both a CCD and a CIS, which controls storage of image data read by each device in a memory and the read of the stored data for each rectangular area to obtain a high memory efficiency, an image processing apparatus includes an input section which executes input processing of image data read by an image reading device in accordance with the data output format of the device, an output data control section which distributes the image data that has undergone the input processing by the input section in accordance with the output format of the image reading device, an address generation section which generates address information corresponding to the output format to store the distributed image data in a memory, and a memory control section which DMA-transfers the distributed image data to the memory and stores the image data on the basis of the generated address information.

Abstract: A multi-mode parallel graphics rendering and display system supporting real-time graphics rendering and display operations using a graphics hub device. The system includes a CPU memory space, one or more CPUs for executing graphics-based applications, and a multi-mode parallel graphics rendering system (MPGRS) supporting multiple modes of parallel operation including object division, image division, and time division. The MMPGRS includes a plurality of graphic processing pipelines (GPPLs) that support a parallel graphics rendering process employing one or more modes of parallel operation.

Abstract: A JPEG image processing circuit, capable of performing a JPEG process at high speed, and with low power consumption, and of automatically recovering from a slight trouble, has been disclosed. In the JPEG processing circuit, a JPEG processing section is configured so as to comprise a plurality of JPEG processing cores and a plurality of data storage regions provided in correspondence with the plurality of JPEG processing cores, and when each of the JPEG processing cores performs the process in parallel, the unprocessed data required for the process of each of the JPEG processing cores is stored in each of the data storage regions, corresponding to each of the JPEG processing cores, via a common bus connected to an image memory.

Abstract: This document discusses, among other things, systems and methods that track overall time for processing operations such that the processing time can be shared among the resources in an efficient manner. Processing time can be shifted to image processing where the time will provide the most benefit to image quality. Moreover, access time from one process is banked to be used by a subsequent process or on a subsequent group of pixels. This document also discusses, among other things, systems and methods that provide additional processing power on an as needed basis. In an example, a processing stage and its controller are outside the normal pixel processing flow path. When it is determined that additional processing is required, the processing stage and its controller are activated to perform the additional processing.

Abstract: In image processing, parallel and synchronous pixel processing elements have a pixel value register, a neighbor value register, and a processor receiving adjacent pixel and neighbor values for four adjacent pixels. In a series of iterations, the neighbor value register is updated with—in one mode—the maximum and—in another mode—the minimum of: the current value; the pixel value from any adjacent pixel whose pixel value is different from the current pixel value and the neighbor value from an adjacent pixel whose pixel value is the same as the current pixel value. The pixel value is then replaced by the minimum or maximum (depending on the mode) of the current pixel and neighbor values. The modes may alternate with the number of iterations in each series remaining constant or growing.

Abstract: Performing a hash algorithm in a processor architecture to alleviate performance bottlenecks and improve overall algorithm performance. In one embodiment of the invention, the hash algorithm is pipelined within the processor architecture.

Abstract: The disclosed systems and methods pertain to the processing of large format images in a manner to avoid introducing imaging defects, and more particularly to dividing the large image into bands, processing these bands in parallel and then putting them back together in to create the final processed image. The methods include the use of overlapping the image bands, padding of the bands prior to processing and the redefinition of image values at common boundaries of the bands to minimize or eliminate visible defects.

Abstract: Plate-image-inspection RIP data CD2, CD3 are prepared using the same RIP processing conditions from two print image data prepared in different steps of the prepress process, and inspection results are obtained by comparing these data CD2, CD3. Plate-image-inspection RIP data CD2, CD3 can be prepared in several methods: (1) a method for RIP processing respective non-RIP data using standard RIP processing conditions; (2) a method for respectively converting two RIP data to standard RIP processing conditions; and (3) a method for converting one of two RIP data such that it conforms to the RIP processing conditions of the other.

Abstract: A method and apparatus for determining a closest match of N input patterns relative to R reference patterns using K processing units. Each of a set of input patterns are loaded into the K processing units. One of the Reference patterns is sequentially loaded into each of the processing units and a distance defining the similarity between the reference pattern and each of the input patterns is calculated. A present calculated distance replaces its corresponding stored present minimum distance if it is has a smaller value. After the R reference patterns have been processed the minimum distance and its corresponding identification for all N input patterns is determined without merging outputs. The minimum distances and the identifications may be read either in parallel or serially. The apparatus is easily scalable by adding processors. The number of reference patterns may be easily increased without altering system configuration.

Abstract: An image processing apparatus of the invention includes: a plurality of processing units which share image processing; a parameter memory unit which holds a parameter specifying an operation of each of the processing units; and a control unit which controls the plurality of processing units, and the control unit includes: a sequence management unit which activates each of the processing units according to a sequence indicating a sequence of activation of and completion of processing by each of the processing units, and confirms completion of the processing; and a parameter setting unit which, in advance of activation of each of the processing units by the sequence management unit, reads a parameter for each processing unit to be activated, from the parameter memory unit according to a memory map indicating an address of the parameter for the processing unit, and sets the parameter to the processing unit according to the read result.

Abstract: Image processing in mobile devices is optimized by combining at least two of the color conversion, rotation, and scaling operations. Received images, such as still images or frames of video stream, are subjected to a combined transformation after decoding, where each pixel is color converted (e.g. from YUV to RGB), rotated, and scaled as needed. By combining two or three of the processes into one, read/write operations consuming significant processing and memory resources are reduced enabling processing of higher resolution images and/or power and processing resource savings.

Abstract: An image processing apparatus includes an information processor that is controlled by a general-purpose operating system, and an image processor. The information processor performs a function in a category different from an image processing function performed in the image processor. As a result, a general purpose application program can be used as software for making effective use of the image processing function. Therefore, it is possible to facilitate development of the software to allow the image processing apparatus to perform the function in a category different from the image processing function performed in the image processor, in addition to the image processing function as a basic function.

Abstract: An image reading apparatus includes: an image signal generating part reading a plurality of color components of image data from an original, and generating corresponding image signals for the respective color components; an image processing part carrying out predetermined image processing on the image signal for each of the plurality of color components; and a signal processing part outputting in sequence for each color component the respective color components of the image signals thus generated by the image signal generating part to the image processing part.

Abstract: One embodiment of a method of tracking a plurality of targets can be broadly summarized by the following steps: capturing a plurality of images of a plurality of targets with a plurality of image capture devices; generating a target observation for each target, said target observation including at least a visual signature of the target and a time value; partitioning target observations according to similarities in their visual signatures; and producing primary tracks from the partitioned target observations, wherein each primary track includes ordered sequences of observation events having similarities in their visual signatures. Other methods and systems are also provided.

Abstract: An RF unit receives radio-frequency signals where a plurality of channels are frequency-multiplexed. An A-D unit converts the radio-frequency signals to digital signals. A processing unit processes the plurality of channels contained in the digital signals which have been converted by the A-D unit. The processing unit includes: a band-pass filter, having bands corresponding respectively to the plurality of frequency-multiplexed channels, which separates the digital signals into the plurality of channels; and a demodulation unit which demodulates the plurality of channels separated by the band-pass filter.

Abstract: An information processing apparatus comprises: a division unit dividing input data; a processing unit performing predetermined processing for the divided data; a generation unit generating intermediate data by referencing the processed divided data, and combining the intermediate data; a temporary storage unit storing the processed divided data; and a detection unit selecting a group of divided data that includes the processed divided data, and determining whether or not all processed divided data in the selected group is stored, is provided. As a result of the determination, if it is determined that all the processed divided data is stored, the generation unit generates intermediate data and then deletes all the processed divided data in the selected group, and if it is determined that a part of the processed divided data is not stored, the processing unit preferentially generates the part of the processed divided data.

Abstract: Disclosed is a stereo image matching method for re-creating 3-dimensional spatial information from a pair of 2-dimensional images. The conventional stereo image matching method generates much noise from a disparity value in the vertical direction, but the present invention uses disparity information of adjacent image lines as a constraint condition to eliminate the noise in the vertical direction, and compress the disparity by using a differential coding method to thereby increase a compression rate.

Abstract: Disclosed is a stereo image matching method for re-creating 3-dimensional spatial information from a pair of 2-dimensional images. The conventional stereo image matching method generates much noise from a disparity value in the vertical direction, but the present invention uses disparity information of adjacent image lines as a constraint condition to eliminate the noise in the vertical direction, and compress the disparity by using a differential coding method to thereby increase a compression rate.

Abstract: An image processing apparatus is provided for enhancing the image processing function without having to increase the circuit scale. The image processing apparatus includes an image divider, a pixel processor, and an image coupler. If the number of horizontal pixels on the width of an input image is larger than a size of a line buffer, the image divider equally divides the input image in the vertical direction so that the resulting divided area is smaller than the number of horizontal pixels on the width of the line buffer. Then, the image divider controls an input data transfer circuit so that the pixel data of the input image may be sequentially transferred to the line buffer for each of the equally divided areas. The image processor sequentially processes the pixel data of the input image temporarily stored in the line buffer and then sends out the output pixel data.

Abstract: A check processing method involves capturing at a first compression rate certain portions of a received check, and evaluating, based on that captured image data, whether certain information of the check can be reproduced by image data at a second compression rate that is greater than the first compression rate. If so, then image data representing the subject portions of the check is captured at the second compression rate image data, stored, and used to electronically process a corresponding check payment transaction. If not, then a specific process is executed without using image data at the second compression rate. This processing step outputs a specific signal or stores image data containing representing the subject portions of the received check at the first compression rate. Such process may be embodied in a check processing apparatus and may be carried out in response to a program of instructions.

Abstract: When image processing is performed, the present invention increases the speed of processing for an individual scanning line constituting an image, and improves the throughput while suppressing the required memory area. The present invention is an image processor for performing image processing in parallel using a plurality of processors, wherein when an individual scanning line is divided into a plurality of partial areas, at least one of the plurality of processors is allocated to each of the partial areas for at lest one scanning line constituting an image, and image processing is performed in parallel. As a memory area for storing the image processing result, the image processor comprises memory areas for the number of scanning lines, which is less than the number of the plurality of processors.

Abstract: An image data processing circuit including: an input section for inputting image data; a plurality of compressing sections which are capable of compressing the input image data solely or in parallel; a plurality of decompressing sections which are capable of decompressing the compressed image data solely or in parallel; an output section for outputting the decompressed image data; a transferring section for transferring image data between a memory and of the input section, the compressing sections, the decompressing sections and the output section individually; and a transfer controlling section for selecting a mode from a parallel input/output mode, a parallel input mode and a parallel output mode.

Abstract: An imaging system features high speed digitization of pixel signals by utilizing top and bottom digitization circuits which pipeline sample-and-hold operations with analog-to-digital conversion. In operation, while one digitization circuit is performing a sample-and-hold operation, the other digitization circuit is performing analog-to-digital conversion. The speed of the imaging system may be further increased by pipelining and interleaving operations within the top and bottom digitization circuits by using additional sets of sample-and-hold circuits and analog-to-digital converters.

Abstract: Systems and method for providing shared attribute evaluation circuits in a graphics processing unit are provided. One embodiment can be described as a system for evaluating attributes in a graphics processing unit having a plurality of processing stages. The system can include an evaluation block, configured to process a plurality of attributes corresponding to a plurality of pixels and a plurality of FIFO buffers, each configured between one of the plurality of processing stages and the evaluation block. An embodiment can further include a shared buffer, configured to store the plurality of attributes or pointers during the attribute processing and processing priority logic, configured to determine a plurality of priorities corresponding to the plurality of attributes.

Abstract: An image processing apparatus and method produce sectional image data of a specimen in an arbitrary direction without deterioration of picture quality. A re-construction process produces volume data such that one of coordinate axes of a volume coordinate system such as the z axis is aligned with the principal axis of inertia of a specimen. When sectional image data of the specimen on a certain section are to be produced, from among all voxels which compose the volume data, those voxels whose z coordinates have predetermined values are read out, and the read out voxels are regarded as pixels. As a result, it is not necessary to interpolate pixels, and the deterioration of picture quality arising from interpolation of pixels is prevented.

Abstract: An image processing system processes images via a first processing layer adapted to perform object-independent processing, a second processing layer adapted to perform object-dependent processing, and a third processing layer adapted to perform object composition, recognition and association. The image processing system performs object-independent processing using a plurality of processors each of which is associated with a different one of the pixels of the image. The image processing system performs object-independent processing using a symmetric multi-processor. The plurality of processors may form a massively parallel processor of a systolic array type and configured as a single-instruction multiple-data system. Each of the plurality of the processors is further configured to perform object-independent processing using a unified and symmetric processing of N dimensions in space and one dimension in time.

Abstract: For image processing for repeatedly executing process segment sets including N (N is an integer of 3 or greater) unit process segments Lc, Lm, Ly, Lk, Llc, Llm and Ldy, unit process segments are executed by M (M is an integer of 2 or greater but less than N) processing units. The unit process segments include a first-type unit process segments Lc, Llc, Llm, and Lk for performing processing using a first processing method and a second-type unit process segment Lm, Ly and Ldy for performing processing using a second processing method that is different from the first processing method. Then, when executing process segment sets, the M unit process segments including at least one each of the first-type and the second-type unit process segments Lc, Lm are first executed on the M processing units.

Abstract: For image processes performed repeatedly using a plurality of processing units on a plurality of partial images aligned mutually adjacent to each other, specified processing is performed. This image process includes (i) a first-type process segment on first partial image data representing a partial image to generate M types (M is an integer of 2 or greater) of second partial image data; and (ii) the respectively corresponding M types of second-type process segments on the M types of second partial image data. When executing image processing, parallel processing is performed for the second-type process segment relating to the i-th (i is a positive integer) partial image and the first-type process segment relating to any of the (i+1)-th to the (i+p)-th (p is a positive integer) partial images.

Abstract: A technique is provided for generating quantitative projection images from projection images. The pixels of the quantitative projection images correspond to quantitative composition estimates of two or more materials. The quantitative projection images are reconstructed to generate a quantitative volume in which each voxel value corresponds quantitatively to the two or more materials or a mixture of the two or more materials.

Abstract: In image processing carried out by means of repeated execution of process set which includes N unit processes (where N is an integer equal to 3 or greater), prior to execution of the process groups, the N unit processes are assigned to a number M (where M is an integer equal to 2 or greater, but less than N) of processing modules for executing the unit processes. First, on the basis of execution results of unit processes included in the process group executed immediately prior, there is estimated an estimated load of unit processes of each class in the next process group. Then, on the basis of the estimated load, the N unit processes are assigned to the processing modules. During this process, a selected unit process which is one of the unit processes not yet assigned to a processing module, is assigned to one of the processing modules.

Abstract: An image processing apparatus and method which can achieve a reduction in size of the crossbar circuit and achieve a higher speed of processing, which perform DDA processing (ST11), then read out texture data from a memory (ST12), perform sub-word reallocation processing (ST13), then perform texture-filtering (ST14), then globally distribute data by the crossbar circuit 13 to a first operation processing element of each processing module (ST15), then perform processing at the pixel level, specifically use the texture data after filtering and the various types of data after rasterization to perform operations by pixel units and draw the pixel data passing the various types of tests in the processing at the pixel level to a frame buffer on a memory module (ST16).

Abstract: In a first image processing apparatus, a first image processing unit 104 applies image processing to video content stored in a first storage unit. At this time, the first image processing unit stores information relating to detail and progress of the applied image processing in an image processing information storage unit as image processing information. In a case in which the first image processing unit interrupts the image processing being applied and the interrupted image processing is taken over and executed by a second image processing apparatus, the partially processed video content and the corresponding image processing information are transferred to the second image processing apparatus.

Abstract: A symmetric type image filter processing apparatus having a symmetric type image filter composed of symmetric kernel coefficients, in which SIMD commands are utilized efficiently for making the filtering processes high speed, is provided. The symmetric type image filter processing apparatus provides a row-wise intermediate data generating section, a row-wise intermediate data utilizing section, and a memory. The row-wise intermediate data generating section multiplies each kernel coefficient of M pieces in each column of {(N+1)/2} columns at the right or left column by each pixel of M pieces in the column direction of image data having P pixels in one row, and cumulatively adds the multiplied results, by using SIMD commands that can process sequential data of Q pieces. This multiplication and addition operation is executed P/Q times, and intermediate data in one row of the image data are generated and stored in an intermediate data storing region in the memory.

Abstract: An image processor is disclosed. The image processor includes: N execution means (where N is 2 or greater) for executing given image processing; and a control means for dividing an input image into N parts from a boundary portion between given processing unit blocks to be processed by the N execution means and controlling the execution of the image processing on the resulting N parts of the image performed by the N execution means. The control means extracts an assigned image from the input image for each one of the N parts of the image and assigns the N extracted assigned images to the N execution means, respectively. The N execution means execute the image processing on the images assigned by the control means in a parallel manner.

Abstract: A method and apparatus for determining a closest match of N input patterns relative to R reference patterns using K processing units. Each of a set of input patterns are loaded into the K processing units. One of the Reference patterns is sequentially loaded into each of the processing units and a distance defining the similarity between the reference pattern and each of the input patterns is calculated. A present calculated distance replaces its corresponding stored present minimum distance if it is has a smaller value. After the R reference patterns have been processed the minimum distance and its corresponding identification for all N input patterns is determined without merging outputs. The minimum distances and the identifications may be read either in parallel or serially. The apparatus is easily scalable by adding processors. The number of reference patterns may be easily increased without altering system configuration.

Abstract: The camera includes a sensor for sensing the photographer's iris image and registering the image in advance. The iris image is recorded in the image of a subject by a digital MCU at a timing different from that at which the image of the subject is captured. The recording timing is that at which the camera power supply is turned off, that at which a recording medium is ejected from the camera or that at which the iris image to be recorded is changed to the registered iris image of another photographer. The recording of the iris image is achieved by embedding it as a watermark or by appending it to metadata.

Abstract: An image processing apparatus includes at least two signal processor modules interconnected each other in series. Each of the signal processor modules has an input port through which data is input, a memory which stores data, a signal processor portion which carries out processing on input data according to program and an output port through which data is output. At least one of the signal processor modules outputs, through its output port, input data unprocessed and processed data obtained by carrying out processing on the input data according to the program.

Abstract: In a data conversion device, a plurality of series of data to be converted is input from a buffer memory device to a data processor. The data processor processes a plurality of the series of the data to be converted, simultaneously in parallel, and outputs a plurality of the series of the data to be converted, simultaneously in parallel. A memory controller of the buffer memory device relates a plurality of the series of the data to be converted to respective conversion tables formed therein by the data processor so as to read converted data corresponding to the series of the data to be converted from the respective conversion tables simultaneously in parallel.

Abstract: A system architecture is disclosed that facilitates rapid execution of 3D registration or alignment algorithms. A first image module (e.g., RAM) is included to store data corresponding to images to be registered. A processor coupled to the first storage module accesses the data and determined mutual histogram (MH) values which are then used to compute mutual information (MI) between the images. The processor accumulates the MH values in a second image module. The second storage module is accessible so that registered images can be displayed. The architecture is scalable facilitating distributed calculations to speed-up the registration process.

Abstract: There are provided a data processing apparatus which makes an I/F for data processing modules (processors) versatile to facilitate addition/modification on a data processing module basis in accordance with processing contents, an image processing apparatus, and a method for the apparatuses. A data processing module (3) includes a read address generator (11), read FIFO (7), write address generator (13), write FIFO (9), and arbiter (10) and is connected to a host arbiter (4) through a 1-channel port. The read address generator (11) and write address generator (13) generate interrupts upon acceptance of final access requests so as to control activation of each data processing module (8-1-8-m) in accordance with the state of each data processing module in interrupt processing. Note that data transfer among the respective data processing modules is performed on a RAM (6).

Abstract: In a pipeline process operation including a branching process unit 25 as one of process modules, this branching process unit 25 is provided with an input management unit 251 for managing an input condition, a branching information management unit 252 for managing information as to branching destinations, a buffer unit 253 whose upper storage limit can be designated, and a branching control unit 254 for controlling an entire branching process unit. The branching process unit 25 may execute an arbitrary number of branching process operations without having such a buffer for an entire image.

Abstract: In order to efficiently process image data in a circuit dividing single image data into a plurality of data and processing the data with a plurality of MPUs in parallel with each other, the MPUs process image data input through an input image data in parallel with each other. An address bus inputs addresses of the image data, and address memories provided on the MPUs store the addresses of the image data processed by the MPUs respectively. When the image data are completely processed, the image data are output through an output image bus while the addresses of the image data are output through the address bus.

Abstract: The present invention relates to a method and system for distributed computing an S transform dataset of multidimensional image data of an object. The multidimensional image data are fast Fourier transformed into Fourier domain producing a Fourier spectrum. The respective Fourier frequencies are then partitioned into a plurality of portions of frequencies for simultaneously processing. Processing of each of the plurality of portions of the Fourier frequencies is assigned to a respective processor of a plurality of processors. The Fourier spectrum of multidimensional image data and each of the plurality of portions of the Fourier frequencies is transmitted to the respective processor. The portions of the Fourier frequencies are then simultaneously processed in order to produce the S transform dataset. The S transform data are then collected and stored.

Abstract: A manner of specifying a document to be printed to multiple output mechanisms, including multiple printers and multiple output bins of each printer. Print specification data is received for an electronic document that is desired to be printed. The print specification data specifies two or more output mechanisms. An output mechanism is any potential entity that may be identified to receive one or more printed copies of electronic documents. Non-limiting, illustrative examples of output mechanisms includes the output bin of a single bin printer, a particular output bin of a multiple bin printer, or the output bin of a fax machine. Each of the two or more output mechanisms receives at least one printed copy of the electronic document. Thereafter, the print specification data is processed to initiate printing of the electronic document to the two or more output mechanisms.

Abstract: An image selecting apparatus includes a designation receiving portion which receives designation of a desired specific scene, an input receiving portion which receives input of image data representing an object image, a characteristic value deriving portion which derives from the image data input into the input receiving portion a characteristic value for use in distinguishment of the specific scene referring to reference data in which the kind of a characteristic value and distinguishing condition corresponding to the characteristic value are defined in advance by the scenes which can be designated as the specific scene, and a distinguishing portion which determines whether the image data represents an image which is of the specific scene input into the designation receiving portion on the basis of the characteristic value derived by the characteristic value deriving portion referring to the corresponding distinguishing condition defined in the reference data.

Abstract: The image processing apparatus is provided with a plural memory controllers, each of which controls a RAM. The memory controllers are connected to an SIMD type arithmetic processing section. A control register is connected to the memory controllers. The control register controls transfer of image data between the RAMs and the SIMD type arithmetic processing section.

Abstract: A signal router routes N inputs to M outputs. All inputs signals are ultimately applied to a data buss by spreading across multiple buss lines and time multiplexing. The data are read from the buss and written in identical images to K random access memories. The memories are addressed and read according to a different schedule for each of K output signals that are ultimately demultiplexed to M outputs. As each RAM image is read, another RAM image is written and vice versa. Since each RAM image contains the same data, the generation of signals from each RAM to supply each of the respective K output signals can be done at a rate that is substantially more independent of the input, buss, or RAM write operations than prior art techniques permit.