Abstract: A technique of extending a correction limit defined by an ECC is described. According to one aspect of the present invention, remaining errors that cannot be corrected by the ECCs in a data array is first identified and then formed in form of matrix with defined size. These remaining errors are flipped in value, namely from “1” to “0” or “0’ to “1” if the number of the errors are within a range or additional ECCs are applied to correct the errors in flipped data bits.
Abstract: In general, techniques are described for adapting audio streams for rendering. A device comprising a memory and one or more processors may be configured to perform the techniques. The memory may store a plurality of audio streams that include one or more sub-streams. The one or more processors may determine, based on the plurality of audio streams, a total number of the one or more sub-streams for all of the plurality of audio streams, and adapt, when the total number of the sub-streams is greater than a render threshold, the plurality of audio streams to decrease the number of the one or more sub-streams and obtain an adapted plurality of audio streams. The one or more processors may also apply the renderer to the adapted plurality of audio streams to obtain the one or more speaker feeds, and output the one or more speaker feeds to one or more speakers.
Type:
Grant
Filed:
July 1, 2020
Date of Patent:
April 6, 2021
Assignee:
Qualcomm Incorporated
Inventors:
Isaac Garcia Munoz, Siddhartha Goutham Swaminathan, Nils Günther Peters
Abstract: The invention relates to a digital low frequency correction circuit and a corresponding method for correction of low frequency disturbances within a digital signal, in particular to a reduction of distortions caused by analog circuitry, such as analog signal amplifiers. The low frequency correction circuit comprises a main signal path adapted to delay a digital input signal received by a signal input terminal and at least one correction signal path including a digital correction filter adapted to filter the received digital input signal. Furthermore, an adder of the circuit is adapted to add the digital signal delayed by the main signal path and the digital signal corrected by said correction signal path to generate a digital output signal output by a signal output terminal of the circuit.
Type:
Grant
Filed:
March 13, 2019
Date of Patent:
September 1, 2020
Assignee:
ROHDE & SCHWARZ GMBH & CO. KG
Inventors:
Andrew Schaefer, Andreas Maier, Detlef Schlager
Abstract: A method of managing power consumption in a video device capable of displaying encoded multi-stream video is disclosed. Power reduction is achieved by limiting the amount of video and audio decoding and processing performed on at least some of the encoded streams, by taking particular application contexts into account. In a normal power consumption mode, audio/video data from all streams are decoded and digitally processed for output. In response to detecting a reduced power consumption mode, audio/video from at least some of the streams are processed in a modified manner to reduce power consumption.