Clock Recovery Patents (Class 398/155)
  • Patent number: 11005571
    Abstract: A method and structure for compensation techniques in coherent optical receivers. The present invention provides a coherent optical receiver with an improved 8×8 adaptive MIMO (Multiple Input, Multiple Output) equalizer configured within a digital signal processor (DSP) to compensate the effects of transmitter I/Q skew in subcarrier multiplexing (SCM) schemes. The 8×8 MIMO equalizer can be configured such that each of the 8 outputs is electrically coupled to 3 of 8 inputs, wherein each of the input-output couplings is configured as a filter. The method includes compensating for impairments to the digital conversion of an optical input signal via the 8×8 MIMO equalizer following other signal processing steps, such as chromatic dispersion (CD)/polarization-mode dispersion (PMD) compensation, carrier recovery, timing synchronization, and cycle slip correction.
    Type: Grant
    Filed: June 3, 2020
    Date of Patent: May 11, 2021
    Assignee: INPHI CORPORATION
    Inventors: Mario Rafael Hueda, José L. Correa Lust, Damian Alfonso Morero
  • Patent number: 10925058
    Abstract: An optical transmission device includes a bandwidth allocator that periodically reads bandwidth request information indicating a bandwidth required for a termination device to transmit an uplink signal from a storage and allocates a bandwidth to the termination device on the basis of the read bandwidth request information, and a timing adjuster that adjusts a period at intervals of which the bandwidth allocator reads the bandwidth request information from the storage on the basis of the timing at which resource information used to generate the bandwidth request information is received from an upper device.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: February 16, 2021
    Assignee: NIPPON TELEGRAPH AND TELEPHONE CORPORATION
    Inventors: Tatsuya Shimada, Takayuki Kobayashi, Hiroshi Ou, Daisuke Hisano
  • Patent number: 10880011
    Abstract: Apparatus and method for digital signal constellation transformation are provided herein. In certain configurations, an integrated circuit includes an analog front-end that converts an analog signal vector representing an optical signal into a digital signal vector, and a digital signal processing circuit that processes the digital signal vector to recover data from the optical signal. The digital signal processing circuit generates signal data representing a signal constellation of the digital signal vector. The digital signal processing circuit includes an adaptive gain equalizer that compensates the signal data for distortion of the signal constellation arising from biasing errors of optical modulators used to transmit the optical signal.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: December 29, 2020
    Assignee: INPHI CORPORATION
    Inventor: Shu Hao Fan
  • Patent number: 10879912
    Abstract: A method includes receiving data for a desired output frequency of an output clock of a phase locked loop (PLL) circuit. The method includes determining a preset value for a digitally controlled oscillator (DCO) of the PLL circuit, determining first gain coefficients and second gain coefficients for a filter of the PLL circuit, and determining ratio values for a divider circuit of the PLL circuit based on the data. The method includes providing the preset value to the DCO, the first gain coefficients to the filter, and the ratio values to the divider circuit while the PLL circuit operates in an open-loop configuration. The method includes subsequently operating the PLL circuit in a closed-loop configuration by connecting the filter to the DCO, and providing the second gain coefficients to the filter in response to detecting a phase lock of the PLL circuit operating in the closed-loop configuration.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: December 29, 2020
    Assignee: MARVELL ASIA PTE, LTD.
    Inventors: Manisha Gambhir, Ahmed Hesham Mostafa, Myung Jae Yoo, Zubir Adal
  • Patent number: 10868663
    Abstract: Apparatus and associated methods relate to implementing an analog auxiliary clock and data recovery (CDR) path to provide a high bandwidth CDR in a transceiver that supports both PAM4 and NRZ signaling. In an illustrative example, the auxiliary CDR path may include a phase-frequency detector (PFD)-based phase-locked loop (PLL) and a phase detector (PD)-based PLL. When the PFD-based PLL is locked to a reference clock signal of the transceiver, the PFD-based PLL may be then disabled and the PD-based PLL may be then enabled. Implementing the auxiliary CDR path may advantageously enable the transceiver to implement much larger parts per million (ppm) acquisition and tracking, and thus enable the transceiver to advantageously support new standards such as Peripheral Component Interconnect Express (PCIe) 5.0 and PCIe 6.0, for example.
    Type: Grant
    Filed: May 8, 2020
    Date of Patent: December 15, 2020
    Assignee: XILINX, INC.
    Inventors: Didem Z. Turker Melek, Mayank Raj, Adebabay M. Bekele, Parag Upadhyaya, Yohan Frans
  • Patent number: 10805126
    Abstract: According to one embodiment, a data generation circuit includes a storing circuit, and first and second selection circuits. The storing circuit is configured to store different data items and output the data items in different phases in response to clock signals. The first selection circuit is configured to select first data items one by one from the data items output from the storing circuit and output a first series of selected data items. The second selection circuit is configured to select second data items one by one, whose phase are different from the selected first data items, from the data items output from the storing circuit and output a second series of selected data items.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: October 13, 2020
    Assignee: Toshiba Memory Corporation
    Inventor: Hiroyuki Kobayashi
  • Patent number: 10785827
    Abstract: A master unit and a remote unit is provided for a multiband transmission system for distributing and combining signals of at least one wireless communication network and at least one digital network. A reference frequency generator is arranged in the master unit, the reference frequency generator being designed to clock a master modem for converting the signals of the at least one digital network. The reference frequency signal emitted by the reference frequency signal is restored via a reference frequency receiver and is used for closing a remote modem that is located there for demodulation.
    Type: Grant
    Filed: October 26, 2018
    Date of Patent: September 22, 2020
    Assignee: Andrew Wireless Systems GmbH
    Inventors: Oliver Braz, Stefan Eisenwinter, Mathias A. Schmalisch, Joerg Stefanik, Peter Schmid
  • Patent number: 10749602
    Abstract: Systems and methods include a transmitter configured to communicate over an optical link to a receiver; and a controller configured to, with the transmitter and the receiver operating in a first operating mode, obtain measurements related to operation over the optical link, determine statistical properties of the optical link based on the measurements, wherein the statistical properties relate to conditions on the optical link, and set a second operating mode of one or more of the transmitter and the receiver based on the determined statistical properties. Each of the first operating mode and the second operating mode refer to associated settings in one or more of the transmitter and the receiver, and there is a trade-off between the first operating mode and the second operating mode and associated margin on the optical link.
    Type: Grant
    Filed: June 4, 2019
    Date of Patent: August 18, 2020
    Assignee: Ciena Corporation
    Inventors: Douglas W. Charlton, Andrew D. Shiner, Eric Maniloff, Michael Y. Frankel
  • Patent number: 10715259
    Abstract: A method and structure for compensation techniques in coherent optical receivers. The present invention provides a coherent optical receiver with an improved 8×8 adaptive MIMO (Multiple Input, Multiple Output) equalizer configured within a digital signal processor (DSP) to compensate the effects of transmitter I/Q skew in subcarrier multiplexing (SCM) schemes. The 8×8 MIMO equalizer can be configured such that each of the 8 outputs is electrically coupled to 3 of 8 inputs, wherein each of the input-output couplings is configured as a filter. The method includes compensating for impairments to the digital conversion of an optical input signal via the 8×8 MIMO equalizer following other signal processing steps, such as chromatic dispersion (CD)/polarization-mode dispersion (PMD) compensation, carrier recovery, timing synchronization, and cycle slip correction.
    Type: Grant
    Filed: January 24, 2019
    Date of Patent: July 14, 2020
    Assignee: INPHI CORPORATION
    Inventors: Mario Rafael Hueda, José L. Correa Lust, Damian Alfonso Morero
  • Patent number: 10651937
    Abstract: A method and system for high-precision long-distance distributed fiber-optic time transfer. The system comprises a first clock source, a first fiber-optic time transfer unit, N relay and user units, M bidirectional optical amplifying units, a second fiber-optic time transfer unit, and a second clock source. Each relay and user unit obtains timing signals synchronized with the first clock source according to time interval between received forward and backward timing signals and realize distributed fiber-optic time transfer while realizing optical-electric-optical relay of forward and backward transmitted optical signals.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: May 12, 2020
    Assignee: Shanghai Jiao Tong University
    Inventor: Guiling Wu
  • Patent number: 10559937
    Abstract: A pulsed light generation device, includes: a first optical fiber through which first pulsed light and second pulsed light, having an intensity that decreases while an intensity of the first pulsed light increases, and increases while the intensity of the first pulsed light decreases, having been multiplexed and entered therein, are propagated; and a second optical fiber at which the first pulsed light, having exited the first optical fiber and entered therein, is amplified while being propagated therein, wherein: at the first optical fiber, phase modulation occurs in the first pulsed light due to cross phase modulation caused by the second pulsed light; and self-phase modulation occurring in the first pulsed light at the second optical fiber is diminished by the phase modulation having occurred at the first optical fiber.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: February 11, 2020
    Assignee: NIKON CORPORATION
    Inventor: Akira Tokuhisa
  • Patent number: 10461867
    Abstract: This invention relates to a optical receiver circuit (200) comprising: at least one photo detector (207) configured to convert a received light signal to an input current signal, a transimpedance amplifier circuit (201) with an input to receive the input current signal from the at least one photo detector (207) and being configured to convert the received input current signal to an output voltage signal to generate an output signal of the transimpedance amplifier circuit (201), wherein the transimpedance amplifier circuit comprises a plurality of gain amplifier stages (209, 210, 211), a DC restoration component (205), wherein the DC restoration component (205) is configured to receive the output voltage signal of the transimpedance amplifier circuit (201) for restoring the DC component of the received current signal and configured for outputting a corresponding current signal, and an automatic gain control component (204) configured for controlling via at least one programmable feedback resistor (226, 227) th
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: October 29, 2019
    Assignee: KNOWLEDGE DEVELOPMENT FOR POF SL
    Inventors: Alberto Rodriguez-Perez, Luis Rolindez Alberich, Ruben Perez de Aranda Alonso
  • Patent number: 10340927
    Abstract: In some implementations, a system includes a phase locked loop (PLL) circuit and a digital control unit. The PLL circuit includes a digital loop filter, a digitally controlled oscillator (DCO), and a divider circuit. The digital control unit is configured determine a preset value for the DCO; determine initial gain coefficients and final gain coefficients for the digital loop filter; determine N/R values for the divider circuit; while the PLL circuit is operating in an open-loop configuration, provide the preset value to the DCO, the initial gain coefficients to the digital loop filter, and the N/R values to the divider circuit; after providing the preset value, initial gain coefficients, and N/R values, initiate operation of the PLL circuit in the closed-loop configuration; and in response to detection of a phase lock of the PLL circuit operating in the closed-loop configuration, provide the final gain coefficients to the digital loop filter.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: July 2, 2019
    Assignee: MARVELL INTERNATIONAL LTD.
    Inventors: Manisha Gambhir, Ahmed Hesham Mostafa, Myung Jae Yoo, Zubir Adal
  • Patent number: 10326533
    Abstract: A method and structure for equalization in coherent optical receivers. Block-based LMS (BLMS) algorithm is one of the many efficient adaptive equalization algorithms used to (i) increase convergence speed and (ii) reduce implementation complexity. Since the computation of the equalizer output and the gradient of the error are obtained using a linear convolution, BLMS can be efficiently implemented in the frequency domain with the constrained frequency-domain BLMS (FBLMS) adaptive algorithm. The present invention introduces a novel reduced complexity constrained FBLMS algorithm. This new approach replaces the two discrete Fourier transform (DFT) stages required to evaluate the DFT of the gradient error, by a simple frequency domain filtering. Implementation complexity can be drastically reduced in comparison to the standard constrained FBLMS. Furthermore, the new approach achieves better performance than that obtained with the unconstrained FBLMS in ultra-high speed coherent optical receivers.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: June 18, 2019
    Assignee: INPHI CORPORATION
    Inventors: Mario R. Hueda, Néstor D. Campos
  • Patent number: 10205524
    Abstract: A method and an apparatus for setting a quiet window in a passive optical network system are provided. A first response time from a time after an optical line terminal (OLT) transmits a serial number request up to a time in which the OLT receives a first response signal to the serial number request is measured, and a second response time up to a time in which the OLT receives a final response signal to the serial number request is measured. In addition, distance information of an optical network unit (ONU) including the first response time and the second response time is acquired.
    Type: Grant
    Filed: March 16, 2017
    Date of Patent: February 12, 2019
    Assignee: ELECTRONICS & TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Geun Yong Kim, Hark Yoo, Sung Chang Kim, Dongsoo Lee
  • Patent number: 10177871
    Abstract: A method of fragmented packet transmission in a multiple-channel passive optical network (PON), comprising fragmenting, by a Gigabit-PON encapsulation method (GEM)/next generation-PON encapsulation method (XGEM) engine of a network element, data into a plurality of packet fragments; encapsulating, by the GEM/XGEM engine, the plurality of packet fragments into frames; scheduling, by a bonding block of the network element, transmission of the frames on a plurality of channels, wherein an order for transmitting the frames is based in part on channel availability; and transmitting, by a transmitter of the network element, the frames to a receiver on the plurality of channels according to the scheduling.
    Type: Grant
    Filed: July 8, 2016
    Date of Patent: January 8, 2019
    Assignee: Futurewei Technologies, Inc.
    Inventors: Yuanqiu Luo, Frank Effenberger, Duane Remein
  • Patent number: 10110304
    Abstract: A communication device includes: an optical-communication circuit that is capable of performing optical communication with a different communication device and transmits a first electric signal to the different communication device at a startup time of the communication device; an electro-communication circuit that is capable of performing electro communication with the different communication device and receives a second electric signal transmitted from the different communication device in response to the first electric signal; and a control circuit that transmits error information indicating an error in the optical communication to a device after the second electric signal is received by the electro-communication circuit.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: October 23, 2018
    Assignee: FUJITSU LIMITED
    Inventor: Atsushi Miki
  • Patent number: 10097279
    Abstract: An heterodyne apparatus and method for measuring performance parameters of a coherent optical receiver at RF frequencies is disclosed. Two coherent lights are launched into signal and LO ports of the receiver with an optical frequency offset f. One of the lights is modulated in amplitude at two phase-locked modulation frequencies F1 and F2. COR performance parameters are determined by comparing two frequency components of the COR output. The group delay variation (GDV) information is obtained by comparing phases of two time-domain traces corresponding to frequency components of the COR output signal at the two modulation frequencies shifted by the optical frequency offset f.
    Type: Grant
    Filed: October 4, 2017
    Date of Patent: October 9, 2018
    Assignee: Elenion Technologies, LLC
    Inventors: Bernd-Harald Horst Jurgen Rohde, Erich Gottwald
  • Patent number: 9871583
    Abstract: A receiver applies a calibration method to compensate for skew between input channels. The receiver skew is estimated by observing the coefficients of an adaptive equalizer which adjusts the coefficients based on time-varying properties of the multi-channel input signal. The receiver skew is compensated by programming the phase of the sampling clocks for the different channels. Furthermore, during real-time operation of the receiver, channel diagnostics is performed to automatically estimate differential group delay and/or other channel characteristics based on the equalizer coefficients using a frequency averaging or polarization averaging approach. Framer information can furthermore be utilized to estimate differential group delay that is an integer multiple of the symbol rate. Additionally, a DSP reset may be performed when substantial signal degradation is detected based on the channel diagnostics information.
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: January 16, 2018
    Assignee: INPHI CORPORATION
    Inventors: Shih Cheng Wang, Seyedmohammadreza Motaghiannezam, Matthew C. Bashaw
  • Patent number: 9696412
    Abstract: A system and method for measuring the temporal delay an optical signal experiences along a path is provided it uses single photon sensitive detectors and multiple optical pulse rates. The multiple optical pulse rates are chosen to allow each to be isolated in post-processing even if only a single detector is employed. The detectors can be time-gated at a repetition rate synchronized but different from the optical pulse rates, including the use of a pulsed-pump up-conversion detector. The pulse rate choice allows improved performance, including an extension of the unambiguous temporal delay range. The ability to isolate the pulse rates can also be used for measuring multiple path delays simultaneously or for spectrally resolving path characteristics without requiring the use of spectral filtering. The post-processing function can be segmented to include an initial signal quality estimation step so further processing can be aborted if it is unlikely to succeed.
    Type: Grant
    Filed: January 20, 2015
    Date of Patent: July 4, 2017
    Assignee: Nucript LLC
    Inventors: Gregory S. Kanter, Daniel R. Reilly
  • Patent number: 9686019
    Abstract: The disclosed coherent optical receiver includes a local light source; a 90-degree hybrid circuit; an optoelectronic converter; an analog-to-digital converter; a skew addition unit; and a FFT operation unit. The 90-degree hybrid circuit makes multiplexed signal light interfere with local light from the local light source, and outputs multiple optical signals separated into a plurality of signal components. The optoelectronic converter detects the optical signal and outputs a detected electrical signal. The analog-to-digital converter digitizes the detected electrical signal and outputs a detected digital signal. The skew addition unit adds to the detected digital signal an additional skew amount whose absolute value is equal to, whose sign is opposite to a skew amount of a difference in propagation delay in each lane connected to each output channel of the 90-degree hybrid circuit. The FFT operation unit performs a fast Fourier transform on the output from the skew addition unit.
    Type: Grant
    Filed: December 16, 2011
    Date of Patent: June 20, 2017
    Assignee: NEC CORPORATION
    Inventors: Kiyoshi Fukuchi, Junichi Abe, Wakako Yasuda
  • Patent number: 9625505
    Abstract: A line frequency detector receives an input signal representing a power source and detects a line frequency of the power source based on the input signal. The line frequency detector includes a first band pass filter having a pass band centered at an upper end of an expected frequency range of the power source and a second band pass filter having a pass band centered at a lower end of the expected frequency range. The input signal is filtered by the first and second band pass filters, generating a first characteristic signal and a second characteristic signal. The line frequency detector determines a characteristic ratio between the first characteristic signal and the second characteristic signal, and maps the characteristic ratio to the line frequency of the power source.
    Type: Grant
    Filed: February 24, 2014
    Date of Patent: April 18, 2017
    Assignee: Dialog Semiconductor Inc.
    Inventor: John W. Kesterson
  • Patent number: 9602116
    Abstract: In an example, the present invention provides an analog to digital converter device for a high speed data transmission from 1 GS-s to 100 GS-s, although there can be other variations. In an example, the device has an input receiver device coupled to a transimpedance amplifier. In an example, the transimpedance amplifier is coupled to an input stream of data at 10 GHz to 100 GHz, or other variations.
    Type: Grant
    Filed: January 7, 2016
    Date of Patent: March 21, 2017
    Assignee: INPHI CORPORATION
    Inventors: Michael Le, James Gorecki, Jamal Riani, Jorge Pernillo, Amber Tan, Karthik Gopalakrishnan, Belal Helal, Chang-Feng Loi, Irene Quek, Guojun Ren
  • Patent number: 9578074
    Abstract: Techniques for adaptive content transmission are described herein. During transmission of a content item, a network connection may be monitored to collect data corresponding to one or more network conditions associated with the transmission of the content item. Such network conditions may include, for example, network throughput, available network bandwidth, network latency and others. The collected data may be used to dynamically adjust one or more transmission attributes in connection with the transmitted content item. The one or more transmission attributes may be determined for adjustment at any desired transmission interval.
    Type: Grant
    Filed: November 11, 2013
    Date of Patent: February 21, 2017
    Assignee: Amazon Technologies, Inc.
    Inventors: Mark Kalman, Scott Wright Heath, Gerard Joseph Heinz, II, Keith Emery Belovay, Vinod Murli Mamtani, Bin Wang
  • Patent number: 9549008
    Abstract: Techniques for adaptive content transmission are described herein. During transmission of a content item, a network connection may be monitored to collect data corresponding to one or more network conditions associated with the transmission of the content item. Such network conditions may include, for example, network throughput, available network bandwidth, network latency and others. The collected data may be used to dynamically adjust one or more transmission attributes in connection with the transmitted content item. The one or more transmission attributes may be determined for adjustment at any desired transmission interval.
    Type: Grant
    Filed: November 11, 2013
    Date of Patent: January 17, 2017
    Assignee: Amazon Technologies, Inc.
    Inventors: Mark Kalman, Scott Wright Heath, Gerard Joseph Heinz, II, Keith Emery Belovay, Vinod Murli Mamtani, Bin Wang
  • Patent number: 9252559
    Abstract: An optical-fiber filter system to narrow a linewidth and to reduce noise fluctuations of an optical beam is provided. The optical-fiber filter system includes an optical fiber having a first end-face and an opposing second end-face, the first end-face and the second end-face setting a fiber length; a fiber Bragg grating having a first reflectivity positioned at the first end-face; and a reflector having a second reflectivity positioned at the second end-face. When the optical beam at a first frequency is coupled from a laser into one of the first end-face or the second end-face, a resonant cavity is established at the first frequency between the fiber Bragg grating and the reflector while Brillouin scattered light shifted from the first frequency within the optical fiber is transmitted through the fiber Bragg grating.
    Type: Grant
    Filed: July 10, 2012
    Date of Patent: February 2, 2016
    Assignee: Honeywell International Inc.
    Inventors: Chellappan Narayanan, Glen A. Sanders, Lee K. Strandjord, Jianfeng Wu
  • Patent number: 9094122
    Abstract: A signal equalizer for compensating impairments of an optical signal received through a link of a high speed optical communications network. At least one set of compensation vectors are computed for compensating at least two distinct types of impairments. A frequency domain processor is coupled to receive respective raw multi-bit in-phase (I) and quadrature (Q) sample streams of each received polarization of the optical signal. The frequency domain processor operates to digitally process the multi-bit sample streams, using the compensation vectors, to generate multi-bit estimates of symbols modulated onto each transmitted polarization of the optical signal. The frequency domain processor exhibits respective different responses to each one of the at least two distinct types of impairments.
    Type: Grant
    Filed: January 23, 2013
    Date of Patent: July 28, 2015
    Assignee: CIENA CORPORATION
    Inventors: Kim B. Roberts, Han Sun
  • Patent number: 9042737
    Abstract: In the present invention, wasted power consumption caused when a clock and data recovery unit in an optical network unit in a PON system is activated from a power-saving state is reduced and rapid, secure communication is performed. A clock and data recovery unit includes a phase-locked loop that can be set to normal mode or power-saving mode and that includes a voltage-controlled oscillator and recovers a clock signal and a data signal from input signals. The clock and data recovery unit includes a reference clock multiplier circuit that multiplies a reference clock signal and outputs the multiplied reference clock signal; and a frequency training loop that includes the same voltage-controlled oscillator and performs synchronous oscillation training by the voltage-controlled oscillator using the reference clock multiplier circuit before the phase-locked loop transitions from power-saving mode to normal mode.
    Type: Grant
    Filed: February 21, 2012
    Date of Patent: May 26, 2015
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: Naruto Tanaka
  • Patent number: 9025965
    Abstract: Disclosed are a phase locked loop (PLL) of a digital scheme and a method thereof. More specifically, disclosed are a digital phase locked loop having a time-to-digital converter (TDC), a digital loop filter (DLF), and a digitally controlled oscillator (DCO), and that is designed to have a constant jitter characteristic at all times even though an operating condition of a circuit varies according to a process, voltage, temperature (PVT) change, and a method thereof.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: May 5, 2015
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Seung Woo Lee, Kwang Chun Choi, Woo Young Choi, Bhum Cheol Lee
  • Patent number: 9020086
    Abstract: A clock data recovery circuit module including a clock recovery circuit, a frequency comparison circuit and a signal detecting circuit is provided. The clock recovery circuit is configured to output a data recovery stream and a data recovery clock based on an input signal and a clock signal. The frequency comparison circuit is coupled to the clock recovery circuit. The frequency comparison circuit is configured to compare a frequency difference between the data recovery clock and the clock signal to adjust the frequency of the clock signal based on a comparison result. The signal detecting circuit is coupled to the frequency comparison circuit. The signal detecting circuit is configured to receive and detect the input signal, and the signal detecting circuit determines whether to enable the frequency comparison circuit according to the detection result. Furthermore, a method for generating a data recovery clock is also provided.
    Type: Grant
    Filed: March 28, 2013
    Date of Patent: April 28, 2015
    Assignee: Phison Electronics Corp.
    Inventors: Chih-Ming Chen, An-Chung Chen
  • Patent number: 9020341
    Abstract: An optical transmission system includes at least a first optical link to transmit a first data signal as a part of a multi-lane signal and a second optical link to transmit a second data signal as another part of the multi-lane signal; on the transmission side, a reference clock is constantly applied to the first data signal of the first optical link, and a delay clock is applied to the second data signal responsive to a control signal on the second optical link; on the receiving side, the phase of a first clock signal detected from the first data signal received on the first optical link and the phase of a second clock signal detected from the second data signal received on the second optical link are compared, and the control signal is detected from the comparison result.
    Type: Grant
    Filed: January 4, 2013
    Date of Patent: April 28, 2015
    Assignee: Fujitsu Limited
    Inventor: Tsuyoshi Yamamoto
  • Publication number: 20150110501
    Abstract: An optical modulator device directly-coupled to a driver circuit device. The optical modulator device can include a transmission line electrically coupled to an internal VDD, a first electrode electrically coupled to the transmission line, a second electrode electrically coupled to the first electrode and the transmission line. A wave guide can be operably coupled to the first and second electrodes, and a driver circuit device can be directly coupled to the transmission line and the first and second electrodes. This optical modulator and the driver circuit device can be configured without back termination.
    Type: Application
    Filed: December 26, 2014
    Publication date: April 23, 2015
    Inventor: Carl POBANZ
  • Patent number: 9002212
    Abstract: Provided is an optical line terminator (OLT) to recover packet data and a clock from an optical signal including a silent interval. The OLT may receive packet data and a clock from at least one optical network unit (ONU). Even in a silent interval in which the at least one ONU does not transmit packet data, the OLT may successfully recover the clock.
    Type: Grant
    Filed: August 19, 2011
    Date of Patent: April 7, 2015
    Assignee: Intellectual Discovery Co., Ltd.
    Inventors: Mun Seob Lee, Dong Soo Lee, Geun Yong Kim, Hark Yoo, Young Suk Lee, Sung Chang Kim, Jai Sang Koh, Jong Deog Kim
  • Patent number: 8989593
    Abstract: Consistent with an aspect of the present disclosure, an optical signal carrying data or information is supplied to photodetector circuitry that generates a corresponding analog signal. The analog signal may be amplified or otherwise processed and supplied to analog-to-digital conversion (ADC) circuitry, which samples the analog signal to provide a plurality of digital signals or samples. The timing of such sampling is in accordance with a clock signal supplied to the ADC circuitry. A phase detector is provided that detects and adjust the clock signal to have a desired phase based on frequency domain data that is output from a Fast Fourier transform (FFT) circuit that receives the digital samples. Preferably, the phase detector circuit is configured such that it need not receive all the frequency domain data output from the FFT at any given time in order to determine the clock phase.
    Type: Grant
    Filed: December 6, 2010
    Date of Patent: March 24, 2015
    Assignee: Infinera Corporation
    Inventors: Han Henry Sun, Kuang-Tsan Wu
  • Patent number: 8971701
    Abstract: A universal optical receiver may include an optical channel monitor configured to acquire spectral data for an optical signal on at least one selected optical channel, a tunable local oscillator configured to be tuned to a center frequency of the optical signal on the at least one selected optical channel, a storage device configured to store data associated with the optical signal responsive to acquisition of the spectral data and tuning of the tunable local oscillator, and processing circuitry configured to execute an algorithm that employs a plurality of binary distinctions based on physical characteristics of the optical signal and employs at least one calculation of figure of merit associated with a series of parameter values of the optical signal to identify a format of the optical signal.
    Type: Grant
    Filed: September 4, 2012
    Date of Patent: March 3, 2015
    Assignee: The Johns Hopkins University
    Inventors: Eric J. Adles, Michael L. Dennis, Raymond M. Sova, Joseph E. Sluz, Michael G. Taylor, Curtis R. Menyuk, John W. Zweck
  • Patent number: 8971703
    Abstract: A wavelength dispersion amount estimation method, a wavelength dispersion compensation circuit, and a receiving device which rapidly estimate and set a wavelength dispersion amount to compensate with high accuracy at the receiving device which compensates waveform distortion at an optical fiber transmission path.
    Type: Grant
    Filed: February 1, 2012
    Date of Patent: March 3, 2015
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Etsushi Yamazaki, Takayuki Kobayashi, Masahito Tomizawa, Riichi Kudo, Koichi Ishihara, Tadao Nakagawa, Mitsuteru Ishikawa
  • Patent number: 8971718
    Abstract: A clock and data recovery (CDR) circuit, a method of recovering a clock and data from a received raw data stream and a BI-PON optical network transceiver (ONT) receiver front-end incorporating the CDR circuit. In one embodiment, the CDR circuit includes: (1) a line rate CDR circuit having a voltage controlled oscillator, the line rate CDR circuit configured to recover a raw data stream at a receiving line rate, (2) a fixed-rate down-sampler coupled to the line rate CDR circuit and configured to down-sample the raw data stream based on a fixed-rate and (3) a variable-rate down-sampler coupled to the fixed-rate down-sampler and configured further to down-sample the raw data sample based on a variable-rate.
    Type: Grant
    Filed: June 1, 2012
    Date of Patent: March 3, 2015
    Assignee: Alcatel Lucent
    Inventors: Hungkei Chow, Dusan Suvakovic, Christophe Van Praet, Guy Torfs, Xin Yin, Zhisheng Li
  • Patent number: 8964722
    Abstract: A method for synchronizing a plurality of clocks arranged within a plurality of nodes of a packet-switching network comprises comparing parameters that relate to the plurality of clocks in order to determine master-slave relationships between the plurality of clocks, and exchanging time-stamped messages over the packet-switching network each time between a master clock and an associated slave clock to make the associated slave clock subservient to the master clock. A node of the packet-switching network comprises a frequency source controlled by a synchronous physical layer technology. The parameters that relate to a clock of the node comprise a parameter that relates to the frequency source to determine the master slave relationships based on one property of the frequency source.
    Type: Grant
    Filed: December 7, 2009
    Date of Patent: February 24, 2015
    Assignee: Alcatel Lucant
    Inventors: Michel Le Pallec, Dinh Thai Bui
  • Patent number: 8942561
    Abstract: One embodiment provides an Ethernet Passive Optical Network (EPON) system for clock transport. The system includes a reference clock configured to generate a frequency-reference signal, an optical line terminal (OLT) coupled to the reference clock, and an optical network unit (ONU). The OLT includes a clock generator configured to generate an OLT clock based on at least the frequency-reference signal. The ONU includes an optical transceiver, a clock recovery module, and a clock output mechanism. The optical transceiver is configured to transmit optical signals to and receive optical signals from the OLT. The clock-recovery module is configured to recover the frequency-reference signal from the received optical signals. The clock output mechanism is configured to output the recovered frequency-reference signal, thus facilitating transport of the frequency-reference signal over the EPON.
    Type: Grant
    Filed: October 6, 2009
    Date of Patent: January 27, 2015
    Assignee: Broadcom Corporation
    Inventors: Edward W. Boyd, Hidehiko Shibuya
  • Publication number: 20150010312
    Abstract: Apparatuses and methods for an optical data interface with electrical forwarded clock are provided. One example optical data interface (220, 320) can include a transmitter (224, 324) having a data input (232, 332) and a clock input (242, 342), and a receiver (226, 326) having a data output (271, 339) and a forwarded clock signal path (254, 376). An optical communication path (248, 348) is coupled between the data input (232, 332) and the data output (271, 339) and configured to communicate a data signal. An electrical communication path (236, 336) is coupled between the clock input (242, 342) and the forwarded clock signal path (254, 376). The electrical communication path (236, 336) is arranged to forward a clock signal used by the receiver (226, 326) as a reference for the optical data signal.
    Type: Application
    Filed: April 24, 2012
    Publication date: January 8, 2015
    Inventors: Daniel A. Berkram, Dacheng Zhou
  • Publication number: 20150003842
    Abstract: The present invention discloses a clock recovery circuit, an optical receiver, and a passive optical network device. In the clock recovery circuit provided by the embodiment of the present invention, a first signal indicating whether a data loss abnormality occurs in initial serial data is introduced at a side of a phase detector, and a phase adjustment control signal is output to a phase adjustor according to a state of the first signal; and the phase adjustor performs different types of phase adjustment according to a state of the initial serial data, so that a data sampler can recover an accurate clock when the initial serial data is normal and can implement smooth switching of output clock information in special cases such as initial serial data clock loss or recovery, and no great abrupt phase change occurs, thereby ensuring stable and reliable working of a system.
    Type: Application
    Filed: May 22, 2014
    Publication date: January 1, 2015
    Applicant: Huawei Technologies Co., Ltd.
    Inventor: Deqiang Chen
  • Patent number: 8917194
    Abstract: Methods and apparatus intelligently switching between line coding schemes based on context. In one exemplary embodiment, an High Definition Multimedia Interface (HDMI) system is configured to transmit control and video data according to an 8B/10B line coding protocol, and data island data according to TERC4 (TMDS (Transition Minimized Differential Signaling) Error Reduction Coding 4-bit). Various elements of the disclosed HDMI devices are configured to determine when a context switch occurs, and thereafter seamlessly transition between the appropriate line code protocol.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: December 23, 2014
    Assignee: Apple, Inc.
    Inventor: Colin Whitby-Strevens
  • Patent number: 8913895
    Abstract: In a method for controlling timing of a transmission signal from a network termination device having a receiver and a transmitter, a signal is received at the receiver of the network termination device, the signal having been transmitted in accordance with a predetermined bit rate. A core clock signal for the receiver is determined based on the predetermined bit rate at which the signal was transmitted, and the core clock signal is communicated to the transmitter of the network termination device. At the transmitter of the network termination device, a phase adjusted clock signal is generated, and the phase adjusted clock signal is set as the transmitter clock signal. The transmitter clock signal is offset from the core clock signal, and the transmission signal is transmitted from the transmitter of the network termination device based on the transmitter clock signal.
    Type: Grant
    Filed: June 14, 2012
    Date of Patent: December 16, 2014
    Assignee: Marvell International Ltd.
    Inventors: John M. Chiang, Cesar A. Johnston
  • Patent number: 8891973
    Abstract: A receiving unit using a voltage-controlled oscillator is allowed to compensate for the frequency characteristics of the voltage-controlled oscillator resulting from temperature change, without adding a capacitive element for temperature compensation. A receiving unit and an optical line terminal include a clock and data recovery circuit that extracts a clock signal and a data signal from a received signal, and have: a calibrator that calibrates an oscillation frequency of a voltage-controlled oscillator included in the clock and data recovery circuit; and a managing unit having a function of managing a schedule for receiving signals, the managing unit selecting a time where a duration of a certain state meets a time required for calibration by the calibrator to thereby output a reset signal (calibration instruction signal) to the calibrator, the state having no received signal (upstream signal) from which a clock signal and a data signal are to be extracted.
    Type: Grant
    Filed: July 6, 2010
    Date of Patent: November 18, 2014
    Assignees: Sumitomo Electric Industries, Ltd., Ensphere Solutions, Inc.
    Inventor: Naruto Tanaka
  • Patent number: 8891960
    Abstract: A method of communicating data between a network device and a data network to which the device is connected via an optical fiber data link in which the device is connected to the optical fiber data link and the connection is monitored to detect data communication at a first standard. If data communication is detected at the first standard, data communication is established using the first standard. If not, the connection is monitored at the second standard. If data communication is detected at the second standard, data communication is established using the second standard.
    Type: Grant
    Filed: October 10, 2008
    Date of Patent: November 18, 2014
    Assignee: PacketFront Systems AB
    Inventor: Charles Foster
  • Patent number: 8873689
    Abstract: A phase interpolator for a CDR circuit produces an output clock having level transitions between the level transitions on two input clocks. The input clocks drive cross-coupled differential amplifiers with an output that can be varied in phase by variable current throttling or steering, according to an input control value. The differential amplifiers produce an output signal with a transition spanning a time between the start of a transition on the leading input clock up to the end of the transition on the lagging input clock. The output clock is linear so long as the transitions on the two input clocks overlap. Active integrators each having an amplifier with a series resistance and capacitive feedback path are coupled to each input to the cross-coupled differential amplifiers, which enhances overlap of the input clock rise times and improves the linearity of the interpolated output signal.
    Type: Grant
    Filed: August 2, 2012
    Date of Patent: October 28, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tao Wen Chung, Chan-Hong Chern, Ming-Chieh Huang, Chih-Chang Lin, Yuwen Swei
  • Patent number: 8855496
    Abstract: A method and apparatus conduct an optical clock rate negotiation to support asymmetric clock rates for visible light communication (VLC) in a VLC device. A first frame that includes a receiver clock rate supported by a first VLC device is transmitted at a predetermined clock rate. A response frame that includes a receiver clock rate supported by a second VLC device is received from the second VLC device. A transmission clock rate of the first VLC device is selected based on the response frame from the second VLC device. Subsequent frames for data communication are transmitted to the second VLC device at the selected transmission clock rate of the first device. Alternatively, when conducting optical clock negotiation in the PHY layer, multiple clock rates are supported within a single frame.
    Type: Grant
    Filed: December 21, 2010
    Date of Patent: October 7, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sridhar Rajagopal, Eran Pisek, Farooq Khan, Ying Li
  • Patent number: 8842994
    Abstract: A method and system of distributing clock synchronization information within an optical communications network including a plurality of network elements, in which a first network element receives an ingress clock synchronization message, the ingress clock synchronization message including a clock synchronization message identifier and a correction field. The first network element inserts the clock synchronization message identifier into an optical channel frame overhead and inserts the ingress clock synchronization message into an optical channel frame payload. The first network element transmits the optical channel frame overhead and the optical channel frame payload to a second network element, and determines a transit time of the clock synchronization message identifier across each of the network elements. The second network element updates the correction field of the ingress clock synchronization message with said transit times to form an egress clock synchronization message.
    Type: Grant
    Filed: August 22, 2012
    Date of Patent: September 23, 2014
    Assignee: Telefonaktiebolaget L M Ericsson (publ)
    Inventors: Sergio Lanzone, Orazio Toscano, Stefano Ruffini
  • Publication number: 20140270805
    Abstract: A clock at a first network element that is connected to a second network element over an optical fiber link is aligned in time/phase using packet protocols such as PTP. The invention discloses how to correct the asymmetry error inherent in traditional packet-based time-transfer methods.
    Type: Application
    Filed: March 13, 2013
    Publication date: September 18, 2014
    Inventor: Sanjay Mani
  • Patent number: RE45193
    Abstract: An apparatus and method for extracting an optical clock signal are provided. The apparatus includes a first reflection filter selecting and reflecting only a first frequency component in an input optical signal; a first Fabry-Perot laser diode matching the first frequency component reflected by the first reflection filter with a predetermined output mode and outputting the first frequency component in the predetermined output mode; a second Fabry-Perot laser diode selecting a second frequency component in an input optical signal that has not been reflected but has been transmitted by the first reflection filter, matching the second frequency component with a predetermined output mode, and outputting the second frequency component in the predetermined output mode; and a photodetector receiving the first frequency component from the first Fabry-Perot laser diode and the second frequency component from the second Fabry-Perot laser diode and beating them to extract a clock signal.
    Type: Grant
    Filed: August 18, 2011
    Date of Patent: October 14, 2014
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Jaemyoung Lee, Je Soo Ko