Clock Recovery Patents (Class 398/155)
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Patent number: 8971718Abstract: A clock and data recovery (CDR) circuit, a method of recovering a clock and data from a received raw data stream and a BI-PON optical network transceiver (ONT) receiver front-end incorporating the CDR circuit. In one embodiment, the CDR circuit includes: (1) a line rate CDR circuit having a voltage controlled oscillator, the line rate CDR circuit configured to recover a raw data stream at a receiving line rate, (2) a fixed-rate down-sampler coupled to the line rate CDR circuit and configured to down-sample the raw data stream based on a fixed-rate and (3) a variable-rate down-sampler coupled to the fixed-rate down-sampler and configured further to down-sample the raw data sample based on a variable-rate.Type: GrantFiled: June 1, 2012Date of Patent: March 3, 2015Assignee: Alcatel LucentInventors: Hungkei Chow, Dusan Suvakovic, Christophe Van Praet, Guy Torfs, Xin Yin, Zhisheng Li
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Patent number: 8971701Abstract: A universal optical receiver may include an optical channel monitor configured to acquire spectral data for an optical signal on at least one selected optical channel, a tunable local oscillator configured to be tuned to a center frequency of the optical signal on the at least one selected optical channel, a storage device configured to store data associated with the optical signal responsive to acquisition of the spectral data and tuning of the tunable local oscillator, and processing circuitry configured to execute an algorithm that employs a plurality of binary distinctions based on physical characteristics of the optical signal and employs at least one calculation of figure of merit associated with a series of parameter values of the optical signal to identify a format of the optical signal.Type: GrantFiled: September 4, 2012Date of Patent: March 3, 2015Assignee: The Johns Hopkins UniversityInventors: Eric J. Adles, Michael L. Dennis, Raymond M. Sova, Joseph E. Sluz, Michael G. Taylor, Curtis R. Menyuk, John W. Zweck
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Patent number: 8971703Abstract: A wavelength dispersion amount estimation method, a wavelength dispersion compensation circuit, and a receiving device which rapidly estimate and set a wavelength dispersion amount to compensate with high accuracy at the receiving device which compensates waveform distortion at an optical fiber transmission path.Type: GrantFiled: February 1, 2012Date of Patent: March 3, 2015Assignee: Nippon Telegraph and Telephone CorporationInventors: Etsushi Yamazaki, Takayuki Kobayashi, Masahito Tomizawa, Riichi Kudo, Koichi Ishihara, Tadao Nakagawa, Mitsuteru Ishikawa
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Patent number: 8964722Abstract: A method for synchronizing a plurality of clocks arranged within a plurality of nodes of a packet-switching network comprises comparing parameters that relate to the plurality of clocks in order to determine master-slave relationships between the plurality of clocks, and exchanging time-stamped messages over the packet-switching network each time between a master clock and an associated slave clock to make the associated slave clock subservient to the master clock. A node of the packet-switching network comprises a frequency source controlled by a synchronous physical layer technology. The parameters that relate to a clock of the node comprise a parameter that relates to the frequency source to determine the master slave relationships based on one property of the frequency source.Type: GrantFiled: December 7, 2009Date of Patent: February 24, 2015Assignee: Alcatel LucantInventors: Michel Le Pallec, Dinh Thai Bui
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Patent number: 8942561Abstract: One embodiment provides an Ethernet Passive Optical Network (EPON) system for clock transport. The system includes a reference clock configured to generate a frequency-reference signal, an optical line terminal (OLT) coupled to the reference clock, and an optical network unit (ONU). The OLT includes a clock generator configured to generate an OLT clock based on at least the frequency-reference signal. The ONU includes an optical transceiver, a clock recovery module, and a clock output mechanism. The optical transceiver is configured to transmit optical signals to and receive optical signals from the OLT. The clock-recovery module is configured to recover the frequency-reference signal from the received optical signals. The clock output mechanism is configured to output the recovered frequency-reference signal, thus facilitating transport of the frequency-reference signal over the EPON.Type: GrantFiled: October 6, 2009Date of Patent: January 27, 2015Assignee: Broadcom CorporationInventors: Edward W. Boyd, Hidehiko Shibuya
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Publication number: 20150010312Abstract: Apparatuses and methods for an optical data interface with electrical forwarded clock are provided. One example optical data interface (220, 320) can include a transmitter (224, 324) having a data input (232, 332) and a clock input (242, 342), and a receiver (226, 326) having a data output (271, 339) and a forwarded clock signal path (254, 376). An optical communication path (248, 348) is coupled between the data input (232, 332) and the data output (271, 339) and configured to communicate a data signal. An electrical communication path (236, 336) is coupled between the clock input (242, 342) and the forwarded clock signal path (254, 376). The electrical communication path (236, 336) is arranged to forward a clock signal used by the receiver (226, 326) as a reference for the optical data signal.Type: ApplicationFiled: April 24, 2012Publication date: January 8, 2015Inventors: Daniel A. Berkram, Dacheng Zhou
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Publication number: 20150003842Abstract: The present invention discloses a clock recovery circuit, an optical receiver, and a passive optical network device. In the clock recovery circuit provided by the embodiment of the present invention, a first signal indicating whether a data loss abnormality occurs in initial serial data is introduced at a side of a phase detector, and a phase adjustment control signal is output to a phase adjustor according to a state of the first signal; and the phase adjustor performs different types of phase adjustment according to a state of the initial serial data, so that a data sampler can recover an accurate clock when the initial serial data is normal and can implement smooth switching of output clock information in special cases such as initial serial data clock loss or recovery, and no great abrupt phase change occurs, thereby ensuring stable and reliable working of a system.Type: ApplicationFiled: May 22, 2014Publication date: January 1, 2015Applicant: Huawei Technologies Co., Ltd.Inventor: Deqiang Chen
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Patent number: 8917194Abstract: Methods and apparatus intelligently switching between line coding schemes based on context. In one exemplary embodiment, an High Definition Multimedia Interface (HDMI) system is configured to transmit control and video data according to an 8B/10B line coding protocol, and data island data according to TERC4 (TMDS (Transition Minimized Differential Signaling) Error Reduction Coding 4-bit). Various elements of the disclosed HDMI devices are configured to determine when a context switch occurs, and thereafter seamlessly transition between the appropriate line code protocol.Type: GrantFiled: March 15, 2013Date of Patent: December 23, 2014Assignee: Apple, Inc.Inventor: Colin Whitby-Strevens
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Patent number: 8913895Abstract: In a method for controlling timing of a transmission signal from a network termination device having a receiver and a transmitter, a signal is received at the receiver of the network termination device, the signal having been transmitted in accordance with a predetermined bit rate. A core clock signal for the receiver is determined based on the predetermined bit rate at which the signal was transmitted, and the core clock signal is communicated to the transmitter of the network termination device. At the transmitter of the network termination device, a phase adjusted clock signal is generated, and the phase adjusted clock signal is set as the transmitter clock signal. The transmitter clock signal is offset from the core clock signal, and the transmission signal is transmitted from the transmitter of the network termination device based on the transmitter clock signal.Type: GrantFiled: June 14, 2012Date of Patent: December 16, 2014Assignee: Marvell International Ltd.Inventors: John M. Chiang, Cesar A. Johnston
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Patent number: 8891973Abstract: A receiving unit using a voltage-controlled oscillator is allowed to compensate for the frequency characteristics of the voltage-controlled oscillator resulting from temperature change, without adding a capacitive element for temperature compensation. A receiving unit and an optical line terminal include a clock and data recovery circuit that extracts a clock signal and a data signal from a received signal, and have: a calibrator that calibrates an oscillation frequency of a voltage-controlled oscillator included in the clock and data recovery circuit; and a managing unit having a function of managing a schedule for receiving signals, the managing unit selecting a time where a duration of a certain state meets a time required for calibration by the calibrator to thereby output a reset signal (calibration instruction signal) to the calibrator, the state having no received signal (upstream signal) from which a clock signal and a data signal are to be extracted.Type: GrantFiled: July 6, 2010Date of Patent: November 18, 2014Assignees: Sumitomo Electric Industries, Ltd., Ensphere Solutions, Inc.Inventor: Naruto Tanaka
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Patent number: 8891960Abstract: A method of communicating data between a network device and a data network to which the device is connected via an optical fiber data link in which the device is connected to the optical fiber data link and the connection is monitored to detect data communication at a first standard. If data communication is detected at the first standard, data communication is established using the first standard. If not, the connection is monitored at the second standard. If data communication is detected at the second standard, data communication is established using the second standard.Type: GrantFiled: October 10, 2008Date of Patent: November 18, 2014Assignee: PacketFront Systems ABInventor: Charles Foster
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Patent number: 8873689Abstract: A phase interpolator for a CDR circuit produces an output clock having level transitions between the level transitions on two input clocks. The input clocks drive cross-coupled differential amplifiers with an output that can be varied in phase by variable current throttling or steering, according to an input control value. The differential amplifiers produce an output signal with a transition spanning a time between the start of a transition on the leading input clock up to the end of the transition on the lagging input clock. The output clock is linear so long as the transitions on the two input clocks overlap. Active integrators each having an amplifier with a series resistance and capacitive feedback path are coupled to each input to the cross-coupled differential amplifiers, which enhances overlap of the input clock rise times and improves the linearity of the interpolated output signal.Type: GrantFiled: August 2, 2012Date of Patent: October 28, 2014Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tao Wen Chung, Chan-Hong Chern, Ming-Chieh Huang, Chih-Chang Lin, Yuwen Swei
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Optical clock rate negotiation for supporting asymmetric clock rates for visible light communication
Patent number: 8855496Abstract: A method and apparatus conduct an optical clock rate negotiation to support asymmetric clock rates for visible light communication (VLC) in a VLC device. A first frame that includes a receiver clock rate supported by a first VLC device is transmitted at a predetermined clock rate. A response frame that includes a receiver clock rate supported by a second VLC device is received from the second VLC device. A transmission clock rate of the first VLC device is selected based on the response frame from the second VLC device. Subsequent frames for data communication are transmitted to the second VLC device at the selected transmission clock rate of the first device. Alternatively, when conducting optical clock negotiation in the PHY layer, multiple clock rates are supported within a single frame.Type: GrantFiled: December 21, 2010Date of Patent: October 7, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Sridhar Rajagopal, Eran Pisek, Farooq Khan, Ying Li -
Patent number: 8842994Abstract: A method and system of distributing clock synchronization information within an optical communications network including a plurality of network elements, in which a first network element receives an ingress clock synchronization message, the ingress clock synchronization message including a clock synchronization message identifier and a correction field. The first network element inserts the clock synchronization message identifier into an optical channel frame overhead and inserts the ingress clock synchronization message into an optical channel frame payload. The first network element transmits the optical channel frame overhead and the optical channel frame payload to a second network element, and determines a transit time of the clock synchronization message identifier across each of the network elements. The second network element updates the correction field of the ingress clock synchronization message with said transit times to form an egress clock synchronization message.Type: GrantFiled: August 22, 2012Date of Patent: September 23, 2014Assignee: Telefonaktiebolaget L M Ericsson (publ)Inventors: Sergio Lanzone, Orazio Toscano, Stefano Ruffini
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Publication number: 20140270805Abstract: A clock at a first network element that is connected to a second network element over an optical fiber link is aligned in time/phase using packet protocols such as PTP. The invention discloses how to correct the asymmetry error inherent in traditional packet-based time-transfer methods.Type: ApplicationFiled: March 13, 2013Publication date: September 18, 2014Inventor: Sanjay Mani
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Publication number: 20140270802Abstract: A quantum mechanical synchronization system for a classical distributed computing system. Einstein-Podolsky-Rosen links are established providing entangled photons to provide the quantum synchronization. In one embodiment, the system includes a laser oscillator pump, a spontaneous parametric down-conversion element coupled to the laser oscillator pump, the spontaneous parametric down-conversion element having a first optical output and a second optical output, a first photodetector coupled to the first optical output, a first clock coupled to the first photodetector, a second photodetector coupled to the second optical output by an optical link, and a second clock coupled to the second photodetector.Type: ApplicationFiled: May 21, 2013Publication date: September 18, 2014Applicant: RAYTHEON COMPANYInventors: Steven J. Silverman, Nils Paz, John R. Harmon
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Patent number: 8831435Abstract: A system and method for synchronizing a clock signal. Data traffic is received through a first channel of a fiber optic. A clock signal is received through a second channel of the fiber optic. A clock at a node is disciplined with the clock signal. The clock signal is sent from the clock to one or more interfaces within a node.Type: GrantFiled: October 13, 2008Date of Patent: September 9, 2014Assignee: CenturyLink Intellectual Property LLCInventor: Michael Bugenhagen
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Patent number: 8811555Abstract: An integrated circuit (“IC”) may include clock and data recovery (“CDR”) circuitry for recovering data information from an input serial data signal. The CDR circuitry may include a reference clock loop and a data loop. A retimed (recovered) data signal output by the CDR circuitry is monitored by other control circuitry on the IC for a communication change request contained in that signal. Responsive to such a request, the control circuitry can change an operating parameter of the CDR circuitry (e.g., a frequency division factor used in either of the above-mentioned loops).Type: GrantFiled: February 4, 2010Date of Patent: August 19, 2014Assignee: Altera CorporationInventors: Kazi Asaduzzaman, Tim Tri Hoang, Tin H. Lai, Shou-Po Shih, Sergey Shumarayev
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Publication number: 20140226992Abstract: An object of the present invention is to provide a subscriber-side device, which can generate accurate time information and can synchronize a time with other device even if a power supply of a portion that receives a downlink signal is in an OFF state, and to provide an optical transmission system including the same. The subscriber-side device of the present invention corrects and outputs free-running time information, which is generated based on a free-running clock signal, by a time correction value generated based on a frequency deviation between a synchronization clock signal and the free-running clock signal. When the downlink signal sent from the station-side device is in a signal interruption state of being incapable of recognizing or receiving the downlink signal, the subscriber-side device corrects and outputs the free-running time information by a time correction value generated before the downlink signal turns to the signal interruption state.Type: ApplicationFiled: December 12, 2011Publication date: August 14, 2014Applicant: Mitsubishi Electric CorporationInventor: Koji Takahashi
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Patent number: 8805201Abstract: A time synchronization method and a time synchronization device in a passive optical network (PON), and a PON are provided. The method includes receiving a synchronization packet sent after time synchronization of an optical line terminal (OLT) with a master clock (MC) is achieved, wherein the synchronization packet carries a timestamp TMt1i determined after the time synchronization of the OLT is achieved, adjusting a local clock according to the timestamp to achieve time synchronization of an optical network unit/optical network terminal (ONU/ONT) with the OLT, and after the time synchronization of the OLT is achieved, instructing an slave clock (SC) to perform time synchronization. A time synchronization device and a time synchronization system for implementing the method in a PON are further provided.Type: GrantFiled: July 30, 2012Date of Patent: August 12, 2014Assignee: Huawei Technologies Co., Ltd.Inventors: Jun Zhao, Sanzhong Li, Meng Sui
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Patent number: 8781333Abstract: The invention relates to a clock recovery apparatus being configured to recover clock information from an input signal. The clock recovery apparatus comprises Fourier transforming means (201) being configured to transform the input signal into a frequency domain signal upon the basis of a Fourier transform, correlating means (215) being configured to correlate the frequency domain signal to obtain a correlation value associated with a certain frequency, and clock recovery means (217) being configured to determine whether the certain frequency corresponds to a clock frequency in order to recover the clock information.Type: GrantFiled: February 3, 2012Date of Patent: July 15, 2014Assignee: Huwei Technologies Co., Ltd.Inventors: Fabian Nikolaus Hauske, Chan Zhao
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Patent number: 8774621Abstract: In a communication line switching method for an optical communications system in which a station-side line terminal apparatus and user-side line terminal apparatuses are connected via a plurality of redundant physical lines, the discovery of the station-side optical line terminal registering the user-side line terminal apparatuses, wherein the registered user-side line terminal apparatuses monitoring a time stamp drift error that is generated when a difference between a time stamp included in a received signal and a local time measured by the own apparatus is larger than a value set in advance and, when the time stamp drift error occurs, shifting to a deregistered state and waiting for registration by the discovery. The station-side line terminal apparatus switches a physical line from a working physical line to a backup physical line of the physical lines.Type: GrantFiled: November 25, 2010Date of Patent: July 8, 2014Assignee: Mitsubishi Electric CorporationInventor: Hiroaki Mukai
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Patent number: 8761609Abstract: A receiver for fiber optic communications.Type: GrantFiled: November 2, 2010Date of Patent: June 24, 2014Assignee: ClariPhy Communications, Inc.Inventors: Oscar E. Agazzi, Diego E. Crivelli, Hugo S. Carrer, Mario R. Hueda, Martin I. del Barco, Pablo Gianni, Ariel Pola, Elvio Serrano, Alfredo Taddei, Alejandro Castrillon, Martin Serra, Ramiro Matteoda
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Patent number: 8755695Abstract: A burst transmission method and a receiver resetting method and apparatus in a Passive Optical Network (PON) are provided. A burst receiver resetting method in a PON includes: receiving a preamble sequence and synchronizing data; after synchronizing the data, continuing to receive the data, and matching a Burst Terminator (BT); and resetting a receiver after successfully matching the BT. Meanwhile, an apparatus for implementing the method and a corresponding burst data transmission method are provided. By using the burst receiver resetting method and apparatus in the PON and the corresponding burst transmission method at an Optical Network Unit (ONU) burst transmission end, a Reach Extender (RE) does not need to unpack upstream burst bandwidth allocation information carried in downstream data.Type: GrantFiled: September 25, 2013Date of Patent: June 17, 2014Assignee: Huawei Technologies Co., Ltd.Inventors: Jing Li, Dongning Feng, Dongyu Geng, Frank Effenberger
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Patent number: 8755687Abstract: A communication system comprising an emitter of weak light pulses, a detector which is capable of detecting single photons, and a source of a clock signal, wherein said emitter and detector are synchronized using said clock signal, the system further comprising a frequency divider for said clock signal to produce a reduced frequency clock signal and a clock regenerator for regenerating the original clock signal from the reduced frequency clock signal, the system further comprising a communication channel configured to communicate the clock signal between the emitter and detector, the clock signal being reduced before sending through said channel and reconstructed after it has exited said channel.Type: GrantFiled: May 21, 2012Date of Patent: June 17, 2014Assignee: Kabushiki Kaisha ToshibaInventors: James Dynes, Zhiliang Yuan, Andrew W. Sharpe, Andrew James Shields
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Patent number: 8737833Abstract: In a communication line switching method for an optical communications system in which a station-side line terminal apparatus and user-side line terminal apparatuses are connected via a plurality of redundant physical lines, the discovery of the station-side optical line terminal registering the user-side line terminal apparatuses, wherein the registered user-side line terminal apparatuses monitoring a time stamp drift error that is generated when a difference between a time stamp included in a received signal and a local time measured by the own apparatus is larger than a value set in advance and, when the time stamp drift error occurs, shifting to a deregistered state and waiting for registration by the discovery. The station-side line terminal apparatus switches a physical line from a working physical line to a backup physical line of the physical lines.Type: GrantFiled: November 25, 2010Date of Patent: May 27, 2014Assignee: Mitsubishi Electric CorporationInventor: Hiroaki Mukai
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Patent number: 8731198Abstract: In general, techniques are described for protecting optical networks from consecutive identical digit (CID) errors. An optical network device comprising a control unit and an interface may implement the techniques described in this disclosure. The control unit determines whether a data packet will result in a CID error prior to encapsulating at least a portion of the data packet to form a passive optical network (PON) frame and then, in response to the determination that the data packet will result in the CID error, modifies the data packet to form a modified data packet so that the modified data packet will not result in the CID error. The control unit encapsulates the modified data packet to form a PON frame. The control unit applies a scrambling polynomial to the PON frame to form a scrambled PON frame. The interface transmits the scrambled PON frame.Type: GrantFiled: February 2, 2012Date of Patent: May 20, 2014Assignee: Calix, Inc.Inventors: Christopher T. Bernard, Charles J. Eddleston
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Patent number: 8724995Abstract: Provided is a passive optical network system for operating a mixture of PONs with differing transmission speeds and is capable of reducing power consumption on the basis of the amount of signals being transmitted. The master station of the passive optical network system, which determines the amount and timing of signals sent thereto by each of a plurality of slave stations on the basis of the requests of the plurality of slave stations and receives signals from the plurality of slave stations via an optical fiber network, is equipped with a control unit that determines in each set cycle the amount, transmission timing, and transmission speed of the signals that each slave station is permitted to transmit to said master station on the basis of the amount of signals that each of the plurality of slave stations has requested to transmit, and that notifies such to each slave station.Type: GrantFiled: November 9, 2009Date of Patent: May 13, 2014Assignee: Hitachi, Ltd.Inventors: Tohru Kazawa, Akihiko Tsuchiya, Norihiro Sakamoto, Yusuke Yajima, Masatoshi Takihiro
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Patent number: 8718481Abstract: A method and a device are provided for phase recovery of at least two channels comprising the steps of (i) a phase is estimated for each channel; (ii) the phase estimated of each channel is superimposed by a coupling factor with at least one other phase estimated. Further, a communication system is suggested comprising such a device.Type: GrantFiled: April 8, 2009Date of Patent: May 6, 2014Assignee: Xieon Networks S.A.R.L.Inventors: Fabian Hauske, Maxim Kuschnerov, Berthold Lankl, Kittipong Piyawanno, Bernhard Spinnler
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Patent number: 8712247Abstract: A clock phase recovery apparatus includes a clock estimator for estimating a first clock signal and a second clock signal upon the basis of an input signal, the input signal comprising a first sub-signal according to a first optical polarization and a second sub-signal according to a second optical polarization, the first clock signal comprising a first clock magnitude and a first clock phase, the second clock signal comprising a second clock magnitude and a second clock phase, and a selector for selecting the first clock phase to form the estimated clock phase if the first clock magnitude is greater than the second clock magnitude, or for selecting the second clock phase to form the estimated clock phase if the second clock magnitude is greater than the first clock magnitude.Type: GrantFiled: February 9, 2012Date of Patent: April 29, 2014Assignee: Huawei Technologies Co., Ltd.Inventor: Fabian Nikolaus Hauske
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Patent number: 8712243Abstract: Systems and techniques for multiple bit rate optical data transmission. A passive optical network includes an optical line termination unit (OLT) connected to one or more optical network units (ONUs) by optical elements. The OLT is capable of performing downstream transmission to the ONUs at each of a variety of different bit rates, and each ONU performs upstream transmission at one or more bit rates. The OLT can sense a bit rate of a received transmission and change its operation so as to receive and process the transmission exhibiting the sensed bit rate. Each of the ONUs receives and processes downstream transmissions at one or more bit rates, but each ONU is capable of maintaining a phase and frequency lock to downstream transmissions at all bit rates supported by the OLT. One or more of the ONUs may also receive and process downstream transmissions exhibiting different or changed bit rates.Type: GrantFiled: December 17, 2004Date of Patent: April 29, 2014Assignee: Alcatel LucentInventors: Hungkei Keith Chow, Manyalibo Joseph Matthews, Dusan Suvakovic, Doutje T. Van Veen
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Publication number: 20140105614Abstract: Apparatus and method for receiving burst data signal without using external detection signal are disclosed. The apparatus can include a clock data recovery (CDR) circuit to generate a clock signal, and a detection circuit to detect an initial portion in the data recovered from the input signal. The CDR circuit can have a first mode that attempts to synchronize the clock signal with a reference data signal, and a second mode that attempts to synchronize the clock signal with the burst data signal and to recover data based on the clock signal. The apparatus can include a controller to conduct a process including, in sequence, setting the CDR circuit in the first mode, setting the CDR circuit in the second mode, and keeping the CDR circuit in the second mode when the detection circuit detects the initial portion in the recovered data.Type: ApplicationFiled: December 18, 2013Publication date: April 17, 2014Applicant: MegaChips CorporationInventors: Yoshinori NISHI, Masahiro Konishi
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Patent number: 8687968Abstract: A vector sum phase shifter includes a 90° phase shifter (1) which generates an in-phase signal (VINI) and a quadrature signal (VINQ) from an input signal (VIN), a four-quadrant multiplier (2I) which changes the amplitude of the in-phase signal (VINI) based on a control signal (CI), a four-quadrant multiplier (2Q) which changes the amplitude of the quadrature signal (VINQ) based on a control signal (CQ), a combiner (3) which combines the in-phase signal (VINI) and the quadrature signal (VINQ), and a control circuit (4). The control circuit (4) includes a voltage generator which generates a reference voltage, and a differential amplifier which outputs the difference signal between a control voltage (VC) and the reference voltage as the control signal (CI, CQ). The differential amplifier performs an analog operation of converting the control voltage (VC) into the control signal (CI, CQ) similar to a sine wave or a cosine wave.Type: GrantFiled: August 12, 2009Date of Patent: April 1, 2014Assignee: Nippon Telegraph and Telephone CorporationInventors: Hideyuki Nosaka, Munehiko Nagatani, Shogo Yamanaka, Kimikazu Sano, Koichi Murata, Kiyomitsu Onodera, Takatomo Enoki
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Patent number: 8687973Abstract: A voltage generator (400) includes a resistor ladder including resistors (4000-4008) which divide a supplied voltage to generate a plurality of reference voltages, a resistor (4009) provided between a power supply voltage (VCC) and one terminal of the resistor ladder, and a resistor (4010) provided between a power supply voltage (VEE) and the other terminal of the resistor ladder.Type: GrantFiled: August 12, 2009Date of Patent: April 1, 2014Assignee: Nippon Telegraph and Telephone CorporationInventors: Hideyuki Nosaka, Munehiko Nagatani, Shogo Yamanaka, Kimikazu Sano, Koichi Murata, Kiyomitsu Onodera, Takatomo Enoki
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Patent number: 8655191Abstract: A method, apparatus and system for providing clock and data recovery in a receiver for receiving a high speed coherent polarization division multiplexed optical signal using a digital signal processing block including a spectral domain spatial combiner are provided.Type: GrantFiled: June 29, 2009Date of Patent: February 18, 2014Assignee: Alcatel LucentInventors: Noriaki Kaneda, Andreas B. Leven, Stefan Weisser
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Patent number: 8649685Abstract: A light receiving device includes: a converter digitalizing an analog signal with a given sampling clock frequency, the analog signal being obtained through a photoelectric conversion of a received optical signal; a plurality of fixed distortion compensators compensating an output signal of the converter for waveform distortion with a fixed compensation amount that is different from each other; a plurality of phase shift detector circuits detecting a sampling phase shift from an output signal of the plurality of the fixed distortion compensators; a phase-adjusting-amount determiner determining a sampling phase adjusting amount with use of an output signal of the plurality of the phase shift detector circuits; and a phase adjusting circuit reducing a phase difference between the sampling clock frequency and the received optical signal based on a determination result of the phase-adjusting-amount determiner.Type: GrantFiled: December 23, 2010Date of Patent: February 11, 2014Assignee: Fujitsu LimitedInventors: Hisao Nakashima, Takeshi Hoshida
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Patent number: 8644713Abstract: An optical receiver, transmitter, transceiver or transponder for bursty, framed or continuous data. The optical receiver includes a burst mode clock recovery module that recovers the clock rapidly and with a small number of preamble or overhead bits at the front end of the data. A local clock is used for timing when the recovered clock is not available. Transitions between the recovered clock and local clock are smoothed out to avoid undesirable artifacts.Type: GrantFiled: November 12, 2010Date of Patent: February 4, 2014Assignee: Packet Photonics, Inc.Inventors: Henrik N. Poulsen, Daniel J. Blumenthal
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Patent number: 8630546Abstract: Techniques are disclosed that relate to synchronizing a clock on a network interface device with a clock on an optical line terminal (OLT). In one example, the technique to synchronizing the clocks may include monitoring one or more instances when the network interface device transmits information to the OLT and determining when a frame should be received by the network interface device based on the monitored one or more instances when the network interface device transmits information the OLT.Type: GrantFiled: November 1, 2010Date of Patent: January 14, 2014Assignee: Calix, Inc.Inventors: Christopher T. Bernard, Dean M. Dunnigan
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Patent number: 8600235Abstract: A first node receives a first phase modulated optical signal at a first wavelength from a master node. The first node also transmits a first amplitude modulated optical signal to the master node at the first wavelength using a portion of the first phase modulated optical signal as a light source.Type: GrantFiled: June 21, 2012Date of Patent: December 3, 2013Assignee: Verizon Business Global LLCInventors: Tiejun J. Xia, Glenn A. Wellbrock
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Patent number: 8600239Abstract: A clock at a first network element that is connected to a second network element over first and second optical links that are physically distinct from each other is aligned using optical timing signals having different wavelengths. Transit delays between the first and second network elements may be determined using the same optical timing signals.Type: GrantFiled: December 1, 2011Date of Patent: December 3, 2013Assignee: SymmetricomInventor: Sanjay Mani
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Patent number: 8571422Abstract: A burst transmission method and a receiver resetting method and apparatus in a Passive Optical Network (PON) are provided. A burst receiver resetting method in a PON includes: receiving a preamble sequence and synchronizing data; after synchronizing the data, continuing to receive the data, and matching a Burst Terminator (BT); and resetting a receiver after successfully matching the BT. Meanwhile, an apparatus for implementing the method and a corresponding burst data transmission method are provided. By using the burst receiver resetting method and apparatus in the PON and the corresponding burst transmission method at an Optical Network Unit (ONU) burst transmission end, a Reach Extender (RE) does not need to unpack upstream burst bandwidth allocation information carried in downstream data. Therefore, the complexity of the implementation of the RE is reduced, and the method is simple and effective.Type: GrantFiled: August 16, 2011Date of Patent: October 29, 2013Assignee: Huawei Technologies Co., Ltd.Inventors: Jing Li, Dongning Feng, Dongyu Geng, Frank Effenberger
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Patent number: 8565609Abstract: A system for distributing a reference oscillator signal includes a clock having a reference oscillator and a femtosecond laser stabilized by the reference oscillator. The system also includes at least one beamsplitter configured to split the femtosecond laser. The system further includes one or more remote nodes that are spaced from the clock. The remote nodes are configured to generate reference signals based on the split femtosecond laser.Type: GrantFiled: December 15, 2010Date of Patent: October 22, 2013Assignee: Raytheon CompanyInventors: Steven R. Wilkinson, Matthew T. Cashen, Todd O. Clatterbuck
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Patent number: 8565605Abstract: A system to convert upstream burst mode data into continuous mode data in a passive optical network (PON) is provided herein. The system includes a burst mode Serializer/Deserializer (SerDes) that recovers a clock and burst mode data from an Optical Network Unit (ONU). The burst mode unit recovers the burst mode data based on a start time of burst mode data transmission by the ONU and a round-trip time between the ONU and an Optical Line Terminal (OLT). The system further includes a continuous mode SerDes that is coupled to the burst mode SerDes. The continuous mode SerDes is configured to receive the recovered clock and recovered burst mode data from the burst mode SerDes and convert the burst mode data into continuous mode data by buffering and padding the burst mode data based on the recovered clock. The continuous mode Serdes is configured to transmit the continuous mode data to the OLT.Type: GrantFiled: December 14, 2010Date of Patent: October 22, 2013Assignee: Broadcom CorporationInventors: Ryan E. Hirth, Jaroslaw Wojtowicz
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Patent number: 8564407Abstract: A universal infrared receiving apparatus is provided. The universal infrared receiving apparatus includes a slicer, a non-volatile memory, a volatile memory and a comparison apparatus. The slicer slices a remote control command waveform into digital waveform data. The non-volatile memory pre-stores target waveform data. The volatile memory stores the digital waveform data and the target waveform data. The comparison apparatus, coupled to the volatile memory, compares the digital waveform data and the target waveform data to generate a comparison result.Type: GrantFiled: August 13, 2010Date of Patent: October 22, 2013Assignee: MStar Semiconductor, Inc.Inventors: Yu-Ming Lin, Kun-Nan Cheng
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Patent number: 8559826Abstract: Herein disclosed a digital image sender for transmitting a digital image signal including image signals for color image reproduction, a reference clock signal and parallel control signals, including: a parallel/serial converter configured to convert the parallel control signals into a serial control signal by time division multiplexing; a superposition element configured to superpose the serial control signal obtained by the conversion by said parallel/serial converter on the reference clock signal and output a resulting superposition signal; and an electro-optic converter configured to convert the superposition signal outputted from said superposition element from an electric signal into an optical signal.Type: GrantFiled: April 23, 2007Date of Patent: October 15, 2013Assignee: Sony CorporationInventors: Kazuhiro Hongo, Kazunari Yoshifuji
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Patent number: 8543005Abstract: Embodiments of the present invention relate to systems and methods for distributing an intentionally skewed optical-clock signal to nodes of a source synchronous computer system. In one system embodiment, a source synchronous system comprises a waveguide, an optical-system clock optically coupled to the waveguide, and a number of nodes optically coupled to the waveguide. The optical-system clock generates and injects a master optical-clock signal into the waveguide. The master optical-clock signal acquiring a skew as it passes between nodes. Each node extracts a portion of the master optical-clock signal and processes optical signals using the portion of the master optical-clock signal having a different skew for the respective extracting node.Type: GrantFiled: April 30, 2008Date of Patent: September 24, 2013Assignee: Hewlett-Packard Development Company, L.P.Inventors: Nathan L. Binkert, Norman P. Jouppi, Robert S. Schreiber, Jung Ho Ahn
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Patent number: 8538271Abstract: An apparatus comprising an optical receiver configured to receive an optical signal, and a combined level and clock recovery circuit coupled to the optical receiver and configured to update a signal threshold and a clock phase substantially simultaneously. Also included is an apparatus comprising at least one processor configured to implement a method comprising recognizing reception of a signal, and adjusting a threshold and a clock phase associated with the signal using a rising time for the signal and a falling time for the signal. Also included is a method comprising receiving a signal, and adjusting a threshold level of the signal to establish level recovery using a clock recovery scheme.Type: GrantFiled: November 23, 2009Date of Patent: September 17, 2013Assignee: Futurewei Technologies, Inc.Inventor: Frank J. Effenberger
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Patent number: 8538279Abstract: An apparatus comprising a nonlinear lookup unit (NL-LUU) configured to add a phase shift to a signal sample to compensate for pattern dependent phase distortion, and one or more first phase adjustment units coupled to NL-LUU and configured to remove from the signal sample a nonlinear phase error from the NL-LUU, wherein the signal sample corresponds to a received signal polarization component of a polarization multiplexed (PM) coherent signal in a PM coherent optical system.Type: GrantFiled: July 8, 2011Date of Patent: September 17, 2013Assignee: Futurewei Technologies, Inc.Inventors: Chuandong Li, Zhuhong Zhang, Fei Zhu, Yu Sheng Bai
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Patent number: 8526829Abstract: A PPM transmitter includes an optical clock generator for generating equally-spaced optical pulses with a sampling period T; an encoder for transforming an incoming waveform U(t) into a linear combination V(t) of U(t) and a delayed output V(t?kT) according to a rule V(t)=U(t)+aV(t?kT), where k is a positive integer, V(t) is voltage generated by the encoder and a is a coefficient; and an optical delay generator for delaying optical pulses generated by the optical clock generator in proportion to the voltage V(t), such that ?tn=bV(t), where b is another coefficient and where ?tn is the amount of delay imposed by the optical delay generator. The PPM transmitter functions with a PPM receiver for communicating data without the need to transmit or otherwise provide a clock signal. The PPM receiver decodes an original series of the delayed optical pulses Q(t) and a second series Q(t?ckT) delayed by ckT where c is a coefficient.Type: GrantFiled: August 25, 2010Date of Patent: September 3, 2013Assignee: HRL Laboratories, LLCInventors: Daniel Yap, Irina Ionova
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Patent number: RE45193Abstract: An apparatus and method for extracting an optical clock signal are provided. The apparatus includes a first reflection filter selecting and reflecting only a first frequency component in an input optical signal; a first Fabry-Perot laser diode matching the first frequency component reflected by the first reflection filter with a predetermined output mode and outputting the first frequency component in the predetermined output mode; a second Fabry-Perot laser diode selecting a second frequency component in an input optical signal that has not been reflected but has been transmitted by the first reflection filter, matching the second frequency component with a predetermined output mode, and outputting the second frequency component in the predetermined output mode; and a photodetector receiving the first frequency component from the first Fabry-Perot laser diode and the second frequency component from the second Fabry-Perot laser diode and beating them to extract a clock signal.Type: GrantFiled: August 18, 2011Date of Patent: October 14, 2014Assignee: Electronics and Telecommunications Research InstituteInventors: Jaemyoung Lee, Je Soo Ko