Mechanical Shock, Stress, Or Physical Damage Absorbing Or Shielding (e.g., Scratch Or Puncture-resistant Coating, Etc.) Patents (Class 427/96.5)
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Patent number: 8962069Abstract: A process for making an encapsulation structure comprising the following steps: 1) make at least one portion of material capable of releasing at least one gas when said material is heated, the portion of material communicating with the inside of a hermetically closed cavity of the encapsulation structure, 2) heat all or part of said portion of material such that at least part of the gas is released from said portion of material in the cavity, and in which said portion of material capable of releasing at least one gas when said material is heated comprises elements trapped in said portion of material, said trapped elements being released from said portion of material in gaseous form when said material is heated.Type: GrantFiled: September 6, 2012Date of Patent: February 24, 2015Assignee: Commissariat à l'énergie atomique et aux énergies alternativesInventors: Jean-Louis Pornin, Xavier Baillin, Charlotte Gillot, Laurent Vandroux
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Publication number: 20140355225Abstract: Formulated resin systems containing polymeric flood coat compositions are provided herein and characterized by having an initial mix thixotropic index from 1 to 5, and a gel time from 5 to 15 minutes such that when cured the compositions provide a Shore hardness from 15 A to 90 A, a thickness on horizontal surfaces from 20 mils to 75 mils, and a thickness on vertical surfaces from 4 mils to 20 mils. Electronic circuit assemblies flood coated with such formulated resin systems, and methods for protecting and supporting said assemblies, are also provided.Type: ApplicationFiled: May 31, 2014Publication date: December 4, 2014Applicant: Cytec Industries Inc.Inventors: Richard David Jordan, JR., Thomas C. Scanlon, IV
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Patent number: 8869391Abstract: A method for producing a wired circuit board includes the steps of preparing a metal supporting layer, forming an insulating layer on the metal supporting layer so as to form an opening, forming a conductive thin film on the insulating layer and on the metal supporting layer that is exposed from the opening of the insulating layer, heating the conductive thin film, forming a conductive pattern on the conductive thin film that is formed on the insulating layer, and forming a metal connecting portion to be continuous to the conductive pattern on the conductive thin film that is formed on the metal supporting layer exposing from the opening of the insulating layer.Type: GrantFiled: October 25, 2011Date of Patent: October 28, 2014Assignee: Nitto Denko CorporationInventors: Katsutoshi Kamei, Yuu Sugimoto, Hitoki Kanagawa
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Patent number: 8802183Abstract: The system of the present invention includes a conductive element, an electronic component, and a partial power source in the form of dissimilar materials. Upon contact with a conducting fluid, a voltage potential is created and the power source is completed, which activates the system. The electronic component controls the conductance between the dissimilar materials to produce a unique current signature. The system can also measure the conditions of the environment surrounding the system.Type: GrantFiled: July 11, 2011Date of Patent: August 12, 2014Assignee: Proteus Digital Health, Inc.Inventors: Jeremy Frank, Peter Bjeletich, Hooman Hafezi, Robert Azevedo, Robert Duck, Iliya Pesic, Benedict Costello, Eric Snyder
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Patent number: 8728568Abstract: The presently disclosed subject matter is directed to method for forming an encapsulant and coating electronic components such as those utilized in AMR technology with the encapsulant. The encapsulant comprises a wax, a tackifier, a polymer, a plasticizer, a thixotropic agent, and an antioxidant and is designed to protect electronic components from harsh environments such as those where high levels of humidity or corrosive liquids may be present. For example, the encapsulant exhibits minimal percent weight gain due to moisture vapor when subjected to temperatures ranging from about ?40° C. to about 70° C. and relative humidities ranging from 0% to 85% over a period of 200 days.Type: GrantFiled: January 16, 2012Date of Patent: May 20, 2014Assignee: Itron, Inc.Inventors: Satish D. Bhakta, Tom Chastek
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Patent number: 8567050Abstract: A dual-personality extended USB (EUSB) system supports both USB and EUSB memory cards using an extended 9-pin EUSB socket. Each EUSB device 101 includes a PCBA having four standard USB metal contact pads disposed on an upper side of a PCB, and several extended purpose contact springs that extend through openings defined in the PCB. A single-shot molding process is used to form both an upper housing portion on the upper PCB surface that includes ribs extending between adjacent contact pads, and a lower molded housing portion that is formed over passive components and IC dies disposed on the lower PCB surface. The passive components are mounted using SMT methods, and the IC dies are mounted using COB methods. The extended 9-pin EUSB socket includes standard USB contacts and extended use contacts that communicate with the PCBA through the standard USB metal contacts and the contact springs.Type: GrantFiled: October 14, 2011Date of Patent: October 29, 2013Assignee: Super Talent Technology, Corp.Inventors: Siew S. Hiew, Abraham C. Ma, Nan Nan
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Patent number: 8409658Abstract: In one embodiment, a meta-module having circuitry for two or more modules is formed on a substrate, which is preferably a laminated substrate. The circuitry for the different modules is initially formed on the single meta-module. Each module will have one or more component areas in which the circuitry is formed. A metallic structure is formed on or in the substrate for each component area to be shielded. A single body, such as an overmold body, is then formed over all of the modules on the meta-module. At least a portion of the metallic structure for each component area to be shielded is then exposed through the body by a cutting, drilling, or like operation. Next, an electromagnetic shield material is applied to the exterior surface of the body of each of the component areas to be shielded and in contact with the exposed portion of the metallic structures.Type: GrantFiled: December 7, 2007Date of Patent: April 2, 2013Assignee: RF Micro Devices, Inc.Inventors: David J. Hiner, Waite R. Warren, Jr., David Jandzinski
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Patent number: 8329248Abstract: An electrical component includes a conductive substrate, a tin layer formed on the substrate, and a barrier coating formed on the tin layer to impede tin whisker growth. The barrier coating includes a polymer matrix, and abrasive particles that are dispersed about the matrix.Type: GrantFiled: September 11, 2009Date of Patent: December 11, 2012Assignee: Honeywell International Inc.Inventors: Merrill M. Jackson, David Humphrey
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Patent number: 8183474Abstract: It consists of a microcomponent comprising a cavity (13) delimited by a cap (12) enclosing an active part (10) supported by a substrate (11). The cap (12) comprises a top wall (12a) comprising stiffening means with at least one projecting stiffening member (12b), said stiffening member (12b) being located between two recessed areas (12c) of the top wall (12a) and having one end (14) at a distance from the recessed areas (12c) without coming into contact with the substrate (11).Type: GrantFiled: May 21, 2007Date of Patent: May 22, 2012Assignee: Commissariat a l'Energie AtomiqueInventors: Charlotte Gillot, Jean-Louis Pornin, Emmanuelle Lagoutte, Fabrice Jacquet, Sebastien Hentz
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Patent number: 7972521Abstract: The present invention relates to a method of making a robust wafer level chip scale package and, in particular, a method that prevents cracking of the passivation layer during solder flow and subsequent multiple thermal reflow steps. In one embodiment, a passivation layer that is formed using an insulating material applied in a highly compressive manner is used. In another aspect, another layer is applied over the passivation layer to assist with preventing cracking of the passivation layer.Type: GrantFiled: March 12, 2007Date of Patent: July 5, 2011Assignee: Semiconductor Components Industries LLCInventors: Umesh Sharma, Harry Yue Gee, Phillip Gene Holland
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Patent number: 7744946Abstract: The present invention relates to organic siloxane resins and insulating films using the same. The insulating films are manufactured by using organic siloxane resins, wherein organic siloxane resins are hydrolysis-condensation polymers of silane compounds comprising one or more kinds of hydrosilane compounds. They have superior mechanical properties and a low electric property, and therefore, are properly usable for highly integrated semiconductor devices.Type: GrantFiled: April 16, 2004Date of Patent: June 29, 2010Assignee: LG Chem, Ltd.Inventors: Bum-gyu Choi, Min-jin Ko, Byung-ro Ko, Myung-sun Moon, Jung-won Kang, Hye-yeong Nam, Gwi-gwon Kang
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Patent number: 7723812Abstract: Embodiments of the present invention generally relate to a device that has an improved usable lifetime due to the presence of a lubricant that reduces the likelihood of stiction occurring between the various moving parts in an electromechanical device. Embodiments of the present invention also generally include a device, and a method of forming a device, that has one or more surfaces or regions that have a volume of lubricant disposed thereon that acts as a ready supply of “fresh” lubricant to prevent stiction occurring between interacting components found within the device. In one aspect, components within the volume of lubricant form a gas or vapor phase that reduces the chances of stiction-related failure in the formed device. In one example, aspects of this invention may be especially useful for fabricating and using micromechanical devices, such as MEMS devices, NEMS devices, or other similar thermal or fluidic devices.Type: GrantFiled: November 2, 2006Date of Patent: May 25, 2010Assignee: Miradia, Inc.Inventors: Dongmin Chen, Fulin Xiong, Spencer Worley
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Patent number: 7604833Abstract: Provided is a method of manufacturing an electronic part in which a circuit element (3) is formed on a surface of a ceramic substrate (1) and conductive balls (2) are used as terminals of the electronic part. After the ceramic substrate (1) and the conductive balls (2) are fixed, the ceramic substrate (1) is appropriately divided. For this, the manufacturing method includes: a first step of forming the circuit element(s) (3) on the surface of a large ceramic substrate (1) including division grooves (4) longitudinally and laterally provided on the surface thereof; a second step of fixing the conductive balls (2) to terminal portion of the circuit element(s) (3); and a third step of applying stress to the large ceramic substrate (1) to open the division grooves (4), to divide the substrate (1), and the first, second, and third steps are performed in the stated order.Type: GrantFiled: August 25, 2004Date of Patent: October 20, 2009Assignee: KOA CorporationInventor: Ryuusuke Suzuki
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Patent number: 7041331Abstract: Compositions suitable for use as underfill materials in an integrated circuit assembly are provided. Also provided are methods of preparing integrated circuit assemblies containing certain underfill materials as well as electronic devices containing such integrated circuit assemblies.Type: GrantFiled: April 2, 2004Date of Patent: May 9, 2006Assignee: Rohm and Haas Electronic Materials LLCInventors: Angelo A. Lamola, Nathaniel E. Brese
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Patent number: 6954985Abstract: A hole plugging method for a printed circuit board, a hole plugging device in accordance therewith and a manufacturing method in accordance therewith where a mask for selectively exposing a via hole, a through hole and a surface pattern of the printed circuit board is positioned on the board having the via hole and the through hole to electrically connect circuit patterns formed on the surface of the board and in the board and an insulating material is plugged in the via hole by abutting and pushing the material on the surface of the board. Therefore, the insulating material can be plugged smoothly without a void, the processing is simplified by plugging the insulating material just to the height of the circuit pattern in a space between the circuit patterns and accordingly, damage to the circuit pattern can be prevented.Type: GrantFiled: January 14, 2002Date of Patent: October 18, 2005Assignee: LG Electronics Inc.Inventors: Sung Gue Lee, Sung Sik Cho, Yong Il Kim, Yong Soon Jang, Ho Sung Choi, Sang Jin Kong, Young Hwan Kim