Vapor Or Gas Deposition Patents (Class 427/96.8)
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Publication number: 20110081503Abstract: A method of integrating a fluorine-based dielectric with a metallization scheme is described. The method includes forming a fluorine-based dielectric layer on a substrate, forming a metal-containing layer on the substrate, and adding a buffer layer or modifying a composition of the fluorine-based dielectric layer proximate an interface between the fluorine-based dielectric layer and the metal-containing layer.Type: ApplicationFiled: October 6, 2009Publication date: April 7, 2011Inventors: Jianping ZHAO, Lee CHEN
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Publication number: 20110076390Abstract: Methods are provided for multi-step Cu metal plating on a continuous Ru metal film in recessed features found in advanced integrated circuits. The use of a continuous Ru metal film prevents formation of undesirable micro-voids during Cu metal filling of high-aspect-ratio recessed features, such as trenches and vias, and enables formation of large Cu metal grains that include a continuous Cu metal layer plated onto the continuous Ru metal film. The large Cu grains lower the electrical resistivity of the Cu filled recessed features and increase the reliability of the integrated circuit.Type: ApplicationFiled: September 30, 2009Publication date: March 31, 2011Applicants: TOKYO ELECTRON LIMITED, NOVELLUS SYSTEMS, INC.Inventors: Frank M. Cerio, JR., Shigeru Mizuno, Jonathan Reid, Thomas Ponnuswamy
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Patent number: 7910177Abstract: A method for growing films on substrates using sequentially pulsed precursors and reactants, system and devices for performing the method, semiconductor devices so produced, and machine readable media containing the method.Type: GrantFiled: July 31, 2006Date of Patent: March 22, 2011Assignee: Mosaid Technologies IncorporatedInventor: Weimin Li
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Publication number: 20110052797Abstract: Techniques for nitridation of copper (Cu) wires. In one aspect, a method for nitridation of a Cu wire is provided. The method includes the following step. The Cu wire and trimethylsilylazide (TMSAZ) in a carrier gas are contacted at a temperature, pressure and for a length of time sufficient to form a nitridized layer on one or more surfaces of the Cu wire. The Cu wire can be part of a wiring structure and can be embedded in a dielectric media. The dielectric media can comprise an ultra low-k dielectric media.Type: ApplicationFiled: August 26, 2009Publication date: March 3, 2011Applicant: International Business Machines CorporationInventors: Fenton Read McFeely, Chih-Chao Yang, John Jacob Yurkas
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Publication number: 20110045171Abstract: Techniques for forming a ruthenium (Ru) capping layer on a copper (Cu) wire are provided. In one aspect, a method of forming a Ru capping layer on at least one exposed surface of a Cu wire embedded in a dielectric structure includes the following steps. A first Ru layer is selectively deposited onto the Cu wire and the dielectric structure by chemical vapor deposition (CVD) for a period of time during which selective nucleation of the Ru occurs on the surface of the Cu wire. Any nucleated Ru present on the dielectric structure is oxidized. The oxidized Ru and an aqueous acid are contacted to remove the oxidized Ru from the dielectric structure based on a selectivity of the aqueous acid in dissolving the oxidized Ru. A second Ru layer is selectively deposited onto the first Ru layer by CVD to produce a thicker Ru layer.Type: ApplicationFiled: August 19, 2009Publication date: February 24, 2011Applicant: International Business Machines CorporationInventors: Fenton Read McFeely, Chih-Chao Yang, John Jcobs Yurkas
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Publication number: 20110036625Abstract: Multilayer printed wiring boards superior in formation of an ultrafine wiring, which can form a conductive layer superior in peel strength on a flat insulating layer surface, can be prepared by a method including the following steps (A)-(E): (A) a step of laminating a film with a metal film, wherein a metal film layer is formed on a support layer, on an internal-layer circuit substrate via a curable resin composition layer, or laminating an adhesive film with a metal film, wherein a curable resin composition layer is formed on a metal film layer of the film with a metal film, on an internal-layer circuit substrate; (B) a step of curing a curable resin composition layer to form an insulating layer; (C) a step of removing a support layer; (D) a step of removing a metal film layer; and (E) a step of forming a metal film layer on an insulating layer surface by electroless plating.Type: ApplicationFiled: August 27, 2010Publication date: February 17, 2011Applicant: AJINOMOTO CO., INC.Inventors: HIROHISA NARAHASHI, SHIGEO NAKAMURA, TADAHIKO YOKOTA
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Patent number: 7879400Abstract: There is provided a substrate processing apparatus equipped with a metallic component, with at least a part of its metallic surface exposed to an inside of a processing chamber and subjected to baking treatment at a pressure less than atmospheric pressure. As a result of this baking treatment, a film which does not react with various types of reactive gases, and which can block the out diffusion of metals, is formed on the surface of the above-mentioned metallic component.Type: GrantFiled: October 10, 2007Date of Patent: February 1, 2011Assignee: Hitachi Kokusal Electric Inc.Inventors: Takahiro Maeda, Kiyohiko Maeda, Takashi Ozaki
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Publication number: 20110008525Abstract: Present embodiments are directed to a system and method for condensing and curing organic materials within a deposition chamber. Present embodiments may include condensing an organic component from a gas phase into a liquid phase on a target surface within the deposition chamber, wherein the gas phase of the organic component might be mixed with an inert gas. Further, present embodiments may include solidifying the liquid phase of the organic component into a solid phase within the deposition chamber using an inert plasma formed from the inert gas.Type: ApplicationFiled: July 10, 2009Publication date: January 13, 2011Applicant: General Electric CompanyInventors: George Theodore Dalakos, Christian Maria Anton Heller, Ahmet Gun Erlat
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Publication number: 20110000785Abstract: The present invention provides an inventive biosensor that includes multiple regions in which the electrical pattern is formed from different electrically conductive materials. The present invention also provides an inventive method for mass producing biosensors as just described. In one embodiment of this method, first and second different electrically conductive materials are deposited side by side on a portion of an electrically insulating base material, and a plurality of electrical patterns is formed on the portion of the base material. Each electrical pattern includes a first region formed from the first electrically conductive material electrically connected to a second region formed from the second electrically conductive material.Type: ApplicationFiled: April 29, 2010Publication date: January 6, 2011Inventors: Raghbir Singh Bhullar, Mike Celenatano, Said K. El-Rahaiby
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Patent number: 7858510Abstract: Protective caps residing at an interface between metal lines and dielectric diffusion barrier (or etch stop) layers are used to improve electromigration performance of interconnects. Protective caps are formed by depositing a first layer of aluminum-containing material over an exposed copper line by treating an oxide-free copper surface with an organoaluminum compound in an absence of plasma at a substrate temperature of at least about 350° C. The formed aluminum-containing layer is passivated either partially or completely in a chemical conversion which forms Al—N, Al—O or both Al—O and Al—N bonds in the layer. Passivation is performed in some embodiments by contacting the substrate having an exposed first layer with an oxygen-containing reactant and/or nitrogen-containing reactant in the absence of plasma. Protective caps can be formed on substrates comprising exposed ULK dielectric.Type: GrantFiled: January 19, 2010Date of Patent: December 28, 2010Assignee: Novellus Systems, Inc.Inventors: Ananda Banerji, George Andrew Antonelli, Jennifer O'loughlin, Mandyam Sriram, Bart van Schravendijk, Seshasayee Varadarajan
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Patent number: 7838073Abstract: Tantalum precursors useful in depositing tantalum nitride or tantalum oxides materials on substrates, by processes such as chemical vapor deposition and atomic layer deposition. The precursors are useful in forming tantalum-based diffusion barrier layers on microelectronic device structures featuring copper metallization and/or ferroelectric thin films.Type: GrantFiled: May 4, 2010Date of Patent: November 23, 2010Assignee: Advanced Technology Materials, Inc.Inventors: Tianniu Chen, Chongying Xu, Thomas H. Baum
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Patent number: 7829135Abstract: In the process of forming, on a substrate, a multi-layered circuit pattern with layers each having a portion made of the same material throughout the different layers in the direction in which the different layers are stacked, the position of nozzles with respect to the substrate when at least one of the layers is formed is shifted from that when the other layers are formed.Type: GrantFiled: June 6, 2006Date of Patent: November 9, 2010Assignee: Canon Kabushiki KaishaInventors: Yuji Tsuruoka, Takashi Mori, Nobuhito Yamaguchi, Masao Furukawa, Seiichi Kamiya
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Publication number: 20100266751Abstract: This invention concerns a process for producing oxide thin film on a substrate by an ALD type process. According to the process, alternating vapour-phase pulses of at least one metal source material, and at least one oxygen source material are fed into a reaction space and contacted with the substrate. According to the invention, an yttrium source material and a zirconium source material are alternately used as the metal source material so as to form an yttrium-stabilised zirconium oxide (YSZ) thin film on a substrate.Type: ApplicationFiled: June 22, 2010Publication date: October 21, 2010Applicant: ASM International N.V.Inventor: Matti Putkonen
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Patent number: 7785658Abstract: A method for forming a metal wiring structure includes: (i) providing a multi-layer structure including an exposed wiring layer and an exposed insulating layer in a reaction space; (ii) introducing an —NH2 or >NH terminal at least on an exposed surface of the insulating layer in a reducing atmosphere; (iii) introducing a reducing compound to the reaction space and then purging a reaction space; (iv) introducing a metal halide compound to the reaction space and then purging the reaction space; (v) introducing a gas containing N and H and then purging the reaction space; (vi) repeating steps (iii) to (v) in sequence to produce a metal-containing barrier layer; and (vii) forming a metal film on the metal-containing barrier layer.Type: GrantFiled: March 3, 2006Date of Patent: August 31, 2010Assignee: ASM Japan K.K.Inventors: Hiroshi Shinriki, Akira Shimizu
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Publication number: 20100215842Abstract: Tantalum precursors useful in depositing tantalum nitride or tantalum oxides materials on substrates, by processes such as chemical vapor deposition and atomic layer deposition. The precursors are useful in forming tantalum-based diffusion barrier layers on microelectronic device structures featuring copper metallization and/or ferroelectric thin films.Type: ApplicationFiled: May 4, 2010Publication date: August 26, 2010Applicant: ADVANCED TECHNOLOGY MATERIALS, INC.Inventors: Tianniu CHEN, Chongying XU, Thomas H. BAUM
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Publication number: 20100209597Abstract: Silicon is selectively oxidized relative to a metal-containing material in a partially-fabricated integrated circuit. In some embodiments, the silicon and metal-containing materials are exposed portions of a partially-fabricated integrated circuit and may form part of, e.g., a transistor. The silicon and metal-containing material are oxidized in an atmosphere containing an oxidant and a reducing agent. In some embodiments, the reducing agent is present at a concentration of about 10 vol % or less.Type: ApplicationFiled: February 5, 2010Publication date: August 19, 2010Applicant: ASM International N.V.Inventors: Jerome Noiray, Ernst H.A. Granneman
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Patent number: 7763311Abstract: A method for depositing a thin film on a substrate in a vapor deposition system is described. Prior to the deposition process, the substrate is provided within the vapor deposition system and coupled to an upper surface of a substrate holder within the vapor deposition system, whereby the substrate is heated to a deposition temperature in a first gaseous atmosphere. Thereafter, the first gaseous atmosphere is displaced by a second gaseous atmosphere, and the pressure is adjusted to a deposition pressure. The second gaseous atmosphere comprises a gaseous composition that is substantially the same as the carrier gas utilized to transport film precursor vapor to the substrate and the optional dilution gas utilized to dilute the carrier gas and film precursor vapor.Type: GrantFiled: March 28, 2007Date of Patent: July 27, 2010Assignee: Tokyo Electron LimitedInventor: Kenji Suzuki
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Publication number: 20100181545Abstract: A non-volatile memory cell and the fabrication method thereof are provided. The non-volatile memory cell comprises a top electrode, a bottom electrode and an oxide layer disposed between the top electrode and the bottom electrode. The oxide layer comprises a relatively low oxygen content layer adjacent to the bottom electrode, a relatively high oxygen content layer adjacent to the top electrode, and a transition layer disposed between the relatively high and the relatively low oxygen content layers. The transition layer has an oxygen concentration within a range between those of the relatively high and the relatively low oxygen content layers.Type: ApplicationFiled: April 8, 2009Publication date: July 22, 2010Applicant: NANYA TECHNOLOGY CORP.Inventors: Chun-I Hsieh, Chang-Rong Wu
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Patent number: 7713876Abstract: A method for integrating a Ru layer with bulk Cu in semiconductor manufacturing. The method includes depositing a Ru layer onto a substrate in a chemical vapor deposition process, modifying the deposited Ru layer by oxidation, or nitridation, or a combination thereof, depositing an ultra thin Cu layer onto the modified Ru layer, and plating a Cu layer onto the ultra thin Cu layer.Type: GrantFiled: September 28, 2005Date of Patent: May 11, 2010Assignee: Tokyo Electron LimitedInventor: Kenji Suzuki
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Patent number: 7695765Abstract: Methods of preparing a carbon doped oxide (CDO) layer with a low dielectric constant (<3.2) and low residual stress without sacrificing important integration properties such as refractive index and etch rate are provided. The methods involve, for instance, providing a substrate to a deposition chamber and exposing it to TMSA, followed by igniting and maintaining a plasma in a deposition chamber using radio frequency power having high and low frequency components or one frequency component only, and depositing the carbon doped oxide film under conditions in which the resulting dielectric layer has a net tensile stress of less than about 40 MPa, a hardness of at least about 1 GPa, and a SiC:SiOx bond ratio of not greater than about 0.75.Type: GrantFiled: November 12, 2004Date of Patent: April 13, 2010Assignee: Novellus Systems, Inc.Inventors: Keith Fox, Carole Mars, Willis Kirkpatrick, Easwar Srinivasan
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Publication number: 20100085801Abstract: The invention generally encompasses methods of forming thin films molecular based devices, and devices formed therefrom. Some embodiments relate to molecular memory cells, molecular memory arrays, electronic devices including molecular memory, and processing systems and methods for producing molecular memories. More particularly, the present invention encompasses methods and molecular based devices comprising a wetting layer and redox-active molecules.Type: ApplicationFiled: October 1, 2009Publication date: April 8, 2010Inventors: Thomas A. Sorenson, Brian Eastep, Lee Gaherty, Timothy L. Snow
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Patent number: 7693597Abstract: A substrate processing method for removing a resist film from a substrate having the resist film formed thereon comprises maintaining the inner region of the chamber at a prescribed temperature by putting a substrate in a chamber, denaturing the resist film by supplying ozone and a water vapor in such a manner that ozone is supplied into the chamber while a water vapor is supplied into the chamber at a prescribed flow rate, the amount of ozone relative to the amount of the water vapor being adjusted such that the dew formation within the chamber is prevented, and processing the substrate with a prescribed liquid material so as to remove the denatured resist film from the substrate.Type: GrantFiled: October 5, 2005Date of Patent: April 6, 2010Assignee: Tokyo Electron LimitedInventors: Mitsunori Nakamori, Tadashi Iino, Noritaka Uchida, Takehiko Orii
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Publication number: 20100078605Abstract: A method for forming an embedded passive device module comprises depositing a first amount of an alkali silicate material, co-depositing an amount of embedded passive device material with the amount of alkali silicate material; and thermally processing the amount of alkali silicate material and the amount of embedded passive device material at a temperature sufficient to cure the amount of alkali silicate material and the amount of embedded passive device material and form a substantially moisture free substrate.Type: ApplicationFiled: September 29, 2008Publication date: April 1, 2010Inventors: Nathan P. Lower, Ross K. Wilcoxon, Alan P. Boone, Nathaniel P. Wyckoff, Brandon C. Hamilton
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Patent number: 7678421Abstract: A method for increasing deposition rates of metal layers from metal-carbonyl precursors by mixing a vapor of the metal-carbonyl precursor with CO gas. The method includes providing a substrate in a process chamber of a deposition system, forming a process gas containing a metal-carbonyl precursor vapor and a CO gas, and exposing the substrate to the process gas to deposit a metal layer on the substrate by a thermal chemical vapor deposition process.Type: GrantFiled: September 18, 2007Date of Patent: March 16, 2010Assignees: Tokyo Electron Limited, International Business Machines CorporationInventors: Kenji Suzuki, Emmanuel P. Guidotti, Gerrit J. Leusink, Fenton R. McFeely, Sandra G. Malhotra
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Publication number: 20100021656Abstract: An interconnect structure which includes a metal-containing cap located atop each conductive feature that is present within a dielectric material is provided in which a surface region of the metal-containing cap is oxidized prior to the subsequent deposition of any other dielectric material thereon. Moreover, metal particles that are located on the surface of the dielectric material between the conductive features are also oxidized at the same time as the surface region of the metal-containing cap. This provides a structure having a reduced leakage current. In accordance with the present invention, the oxidation step is performed after electroless plating of the metal-containing cap and prior to the deposition of a dielectric capping layer or an overlying interlayer or intralevel dielectric material.Type: ApplicationFiled: October 5, 2009Publication date: January 28, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jeffrey P. Gambino, Jason P. Gill, Sean Smith, Jean E. Wynne
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Patent number: 7651723Abstract: A process chamber is provided which includes a gate configured to align barriers with an opening of the gate and an opening of the process chamber such that the two openings are either sealed or provide an air passage to the chamber. A method is provided and includes sealing an opening of a chamber with a gate latch and exposing a topography to a first set of process steps, opening the gate latch such that an air passage is provided to the process chamber, and exposing the topography to a second set of process steps without allowing liquids within the chamber to flow through the air passage. A substrate holder comprising a clamping jaw with a lever and a support member coupled to the lever is also contemplated herein. A process chamber with a reservoir arranged above a substrate holder is also provided herein.Type: GrantFiled: January 10, 2005Date of Patent: January 26, 2010Assignee: Lam Research CorporationInventors: Igor C. Ivanov, Weiguo Zhang
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Publication number: 20100015800Abstract: A film forming method includes a first step of supplying a carbonyl material including a metallic element onto a surface of a substrate to be processed in a form of gas phase molecules along with a suppressor gas suppressing a decomposition of the carbonyl material, wherein a partial pressure of the suppressor gas is set to a first partial pressure at which the decomposition of the carbonyl material is suppressed; and a second step of changing the partial pressure of the suppressor gas in the surface of the substrate to a second partial pressure which causes the decomposition of the carbonyl material to thereby deposit the metallic element on the surface of the substrate.Type: ApplicationFiled: September 28, 2009Publication date: January 21, 2010Applicant: TOKYO ELECTRON LIMITEDInventors: Masamichi HARA, Tatsuo Hatano
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Patent number: 7638161Abstract: A method and apparatus for controlling dopant concentration during borophosphosilicate glass film deposition on a semiconductor wafer to reduce consumption of nitride on the semiconductor wafer. In one embodiment of the invention, the method starts by placing a substrate having a nitride layer in a reaction chamber and providing a silicon source, an oxygen source and a boron source into the reaction chamber while delaying providing a phosphorous source into the reaction chamber to form a borosilicate glass layer over the nitride layer. The method continues by providing the silicon, oxygen, boron and phosphorous sources into the reaction chamber to form a borophosphosilicate film over the borosilicate glass layer.Type: GrantFiled: July 20, 2001Date of Patent: December 29, 2009Assignee: Applied Materials, Inc.Inventors: Kevin Mukai, Shankar Chandran
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Publication number: 20090293946Abstract: The present invention discloses a mixed-type heterojunction thin-film solar cell structure and a method for fabricating the same. Firstly, a conductive substrate and a template are provided, and the template has a substrate and an inorganic wire array formed on the substrate. Next, a conjugate polymer layer is formed on the conductive substrate. Next, the inorganic wire array is embedded into the conjugate polymer layer. Next, the substrate is separated from the inorganic wire array. Then, an electrode layer is formed over the inorganic wire array and the conjugate polymer layer. The solar cell structure of the present invention has advantages of flexibility, high energy conversion efficiency and low fabrication cost.Type: ApplicationFiled: August 14, 2008Publication date: December 3, 2009Inventors: Ching-Fuh Lin, Chieh-Yu Hsiao, Jiun-Jie Chao
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Publication number: 20090286066Abstract: An electronics component is disclosed herein. The electronics component include a substrate and a plurality of single-walled carbon nanotubes (SWNTs) formed on said substrate, wherein said plurality of SWNTs form a patterned, dense and high-quality arrays of single-walled carbon nanotubes (SWNTs) on quartz wafers by using FeCl3/polymer as catalytic precursors and chemical vapor deposition (CVD) of methane. With the assistance of polymer, the catalysts may be well-patterned on the wafer surface by simple photolithography or polydimethylsiloxane (PDMS) stamp microcontact printing (?CP).Type: ApplicationFiled: April 24, 2009Publication date: November 19, 2009Inventors: Peter J. Burke, Weiwei Zhou, Christopher M. Rutherglen
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Patent number: 7604834Abstract: The present invention discloses a method including: providing a substrate; and sequentially stacking layers of two or more diamond-like carbon (DLC) films over the substrate to form a composite dielectric film, the composite dielectric film having a k value of about 1.5 or lower, the composite dielectric film having a Young's modulus of elasticity of about 25 GigaPascals or higher.Type: GrantFiled: April 8, 2008Date of Patent: October 20, 2009Assignee: Intel CorporationInventor: Kramadhati V. Ravi
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Patent number: 7560136Abstract: Methods of using thin metal layers to make Carbon Nanotube Films, Layers, Fabrics, Ribbons, Elements and Articles are disclosed. Carbon nanotube growth catalyst is applied on to a surface of a substrate, including one or more thin layers of metal. The substrate is subjected to a chemical vapor deposition of a carbon-containing gas to grow a non-woven fabric of carbon nanotubes. Portions of the non-woven fabric are selectively removed according to a defined pattern to create the article. A non-woven fabric of carbon nanotubes may be made by applying carbon nanotube growth catalyst on to a surface of a wafer substrate to create a dispersed monolayer of catalyst. The substrate is subjected to a chemical vapor deposition of a carbon-containing gas to grow a non-woven fabric of carbon nanotubes in contact and covering the surface of the wafer and in which the fabric is substantially uniform density.Type: GrantFiled: January 13, 2003Date of Patent: July 14, 2009Assignee: Nantero, Inc.Inventors: Jonathan W. Ward, Thomas Rueckes, Brent M. Segal
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Publication number: 20090142227Abstract: In a method for producing a parylene coating on a substrate containing an integrated electronic component which is e.g. an x-ray detector, the following steps are provided: vaporization of parylene; pyrolyzation of the vaporized parylene; polymerization of the pyrolyzed parylene, the polymerized parylene being deposited on a cooled substrate. The method provides controllable, patterned deposition of parylene on the cooled and/or heated substrate, the advantage being that x-ray converters, for example, can be anticorrosively encapsulated and a penetration depth of the parylene between phosphor needles or storage phosphor needles can be controlled, resulting in an improved resolution and improved modulation transfer function of electronic components.Type: ApplicationFiled: June 19, 2006Publication date: June 4, 2009Inventors: Manfred Fuchs, Karsten Heuser, Ralph Patzold, Markus Schild
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Publication number: 20090133901Abstract: [Summary] [Problem] To provide a conductive pattern formation method in which a fine pattern can be formed in a simple way at low cost. [Means for solving problem] A flat plate having a convex pattern on its surface is provided so as to oppose a substrate, a fluid body including conductive particles and a gas bubble generating agent is supplied into a gap between the substrate and the flat plate, and thereafter, the fluid body is heated for generating gas bubbles from the gas bubble generating agent included in the fluid body. The fluid body is forced out of the gas bubbles as the gas bubbles generated from the gas bubble generating agent grow, so as to self-assemble between the convex pattern formed on the flat plate and the substrate owing to interfacial force, and an aggregate of the conductive particles included in the fluid body having self-assembled is made into a conductive pattern formed on the substrate.Type: ApplicationFiled: August 11, 2005Publication date: May 28, 2009Inventors: Seiji Karashima, Takashi Kitae, Seiichi Nakatani
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Publication number: 20090116193Abstract: A method for manufacturing a substrate board with high efficiency of heat conduction and electrical isolation is disclosed. The method comprises the steps of: providing a substrate layer with an arrangement surface and a heat-dissipating surface; executing an anodic treatment on the arrangement surface and the heat-dissipating surface to respectively form a first anodic treatment layer and a second anodic treatment layer; forming a heat conduction and electrical isolation layer on the second anodic treatment layer; and forming a diamond like carbon (DLC) layer on the heat conduction and electrical isolation layer. The heat expansion coefficient of the substrate layer is greater than that of the second anodic treatment layer, the heat conduction and electrical isolation layer, and the DLC layer in turn.Type: ApplicationFiled: January 4, 2008Publication date: May 7, 2009Inventor: Yu-Hsueh Lin
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Patent number: 7524766Abstract: To obtain a conductive metal film having superior step coverage, adhesiveness, and high productivity. A conductive metal film or metal oxidized film suitable as a capacitor electrode is formed on a substrate by performing an excited-gas supplying step after a source gas supplying step. In the source gas supplying step, gas obtained by vaporizing an organic source is supplied to the substrate, and the gas thus supplied is allowed to be adsorbed on the substrate. In the excited-gas supplying step, oxygen or nitrogen containing gas excited by plasma is supplied to the substrate to decompose the source adsorbed on the substrate, thus forming a film. An initial film-forming stop is a step of forming the film by repeating the source gas supplying step and the excited-gas supplying step once or multiple times. A desired thickness can be obtained by one step of the initial film-forming step.Type: GrantFiled: July 15, 2003Date of Patent: April 28, 2009Assignee: Hitachi Kokusai Electric Inc.Inventors: Hideharu Itatani, Sadayoshi Horii, Masayuki Asai, Atsushi Sano
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Publication number: 20090081374Abstract: An atomic-layer-deposition process for forming a patterned thin film comprising providing a substrate, applying a deposition inhibitor material to the substrate, wherein the deposition inhibitor material is an organosiloxane compound; and patterning the deposition inhibitor material either after step (b) or simultaneously with applying the deposition inhibitor material to provide selected areas of the substrate effectively not having the deposition inhibitor material. The thin film is substantially deposited only in the selected areas of the substrate not having the deposition inhibitor material.Type: ApplicationFiled: September 26, 2007Publication date: March 26, 2009Inventors: Cheng Yang, Lyn M. Irving, David H. Levy, Peter J. Cowdery-Corvan, Diane C. Freeman
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Patent number: 7507434Abstract: An approach is provided for laminating layers for a flexible printed circuit board. The approach includes a method and apparatus for providing a base substrate and the surface of the base substrate is treated by radiating ion beams using a gas mixture including oxygen and argon to improve adhesive strength and heat resistance. A tie layer can be formed on the based film to prevent a metal conductive layer from diffusion and to increase the adhesive strength.Type: GrantFiled: August 1, 2005Date of Patent: March 24, 2009Assignee: Toray Saehan Inc.Inventors: Jeong Cho, Young Kwan Lee, Young Seop Kim
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Publication number: 20090075488Abstract: The present invention provides metal-containing compounds that include at least one ?-diketiminate ligand, and methods of making and using the same. In certain embodiments, the metal-containing compounds include at least one ?-diketiminate ligand with at least one fluorine-containing organic group as substituent. In other certain embodiments, the metal-containing compounds include at least one ?-diketiminate ligand with at least one aliphatic group as a substituent selected to have greater degrees of freedom than the corresponding substituent in the ?-diketiminate ligands of certain metal-containing compounds known in the art. The compounds can be used to deposit metal-containing layers using vapor deposition methods. Vapor deposition systems including the compounds are also provided. Sources for ?-diketiminate ligands are also provided.Type: ApplicationFiled: October 7, 2008Publication date: March 19, 2009Applicant: MICRON TECHNOLOGY, INC.Inventors: Dan Millward, Timothy A. Quick
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Publication number: 20090057149Abstract: A method for manufacturing a biosensor is provided. The method may include positioning a shadow mask containing a pattern of a plurality of feature sets over a substantially planar base layer containing a plurality of registration points. The method may also include forming at least one of the plurality of feature sets on the substantially planar base layer by selectively depositing a layer of a conductive material on the substantially planar base layer by passing the conductive material through the pattern of the shadow mask and removing the shadow mask from the substantially planar base layer. Alternatively, the method may include providing a laminate structure including a substantially planar base layer containing a plurality of registration points and a photoresist layer containing a pattern of a plurality of feature sets.Type: ApplicationFiled: November 11, 2008Publication date: March 5, 2009Inventors: Greta Wegner, Natasha Popovich
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Publication number: 20090057271Abstract: A manufacturing method of a metal interconnection is provided. A dielectric layer having an opening therein is formed on a substrate and a barrier layer is then formed on the dielectric layer by performing an ALD process. An Al layer and an Al/Cu layer are formed on the substrate by performing a chemical vapor deposition process and a physical vapor deposition process sequentially, and the Al/Cu layer fills the opening through hot-reflow. A metal line and a plug are formed at the same time after patterning the metal layers and the barrier layer by photolithography and etching processes. Alternatively, the metal layers and the barrier layer outside the opening are removed by a chemical mechanical process, so as to form a plug. The manufacturing method simplifies the processes of forming the metal interconnection and is adapted to the metal interconnection having the opening at a relatively high aspect ratio.Type: ApplicationFiled: February 4, 2008Publication date: March 5, 2009Applicant: POWERCHIP SEMICONDUCTOR CORP.Inventor: I-Chern Kao
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Publication number: 20090061080Abstract: A method for forming a metal/metal oxide structure that includes forming metal oxide regions, e.g. ruthenium oxide regions, at grain boundaries of a metal layer, e.g., platinum. Preferably, the metal oxide regions are formed by diffusion of oxygen through grain boundaries of the metal layer, e.g., platinum, to oxidize a metal layer thereon, e.g, ruthenium layer. The structure is particularly advantageous for use in capacitor structures and memory devices, such as dynamic random access memory (DRAM) devices.Type: ApplicationFiled: October 9, 2008Publication date: March 5, 2009Applicant: MICRON TECHNOLOGY, INC.Inventors: Cem Basceri, Gurtej Sandhu
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Patent number: 7498060Abstract: The invention provides a method of controlling the spatial distribution, shape and size of films of conjugated organic molecules that can be used to grow single layers of organic molecules on silicon oxide nanostructures. The silicon oxide nanostructures are produced using an anodic oxidation process. The organisation of the molecules on the oxide nanostructures is dependent on the kinetic parameters of the latter (evaporation rate, diffusion coefficient) and on the interactions with the silicon (anodic) oxide regions. The molecules form domains which exactly reproduce the lateral size and the shape of the oxide nanostructures. The invention provides a powerful method of performing a bottom-up construction of wires, electrodes and charge transfer zones in nanoscale devices.Type: GrantFiled: September 7, 2005Date of Patent: March 3, 2009Inventors: Fabio Biscarini, Ricardo García García
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Publication number: 20090039415Abstract: In one embodiment, the method of forming a dielectric layer includes supplying a first precursor at a temperature less than 400 degrees Celsius to a chamber including a substrate. The first precursor includes dysprosium. A first reaction gas is supplied to the chamber to react with the first precursor. A second precursor is supplied at a temperature less than 400 degrees Celsius to the chamber, and the second precursor includes scandium. A second reaction gas is supplied to the chamber to react with the second precursor.Type: ApplicationFiled: May 28, 2008Publication date: February 12, 2009Inventors: Hoonsang Choi, Bongjin Kuh, Sunjung Kim, Youngsun Kim, Seunghwan Lee, Sangwook Lim, Chunhyung Chung
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Patent number: 7488435Abstract: The present invention relates to novel 1,3-diimine copper complexes and the use of 1,3-diimine copper complexes for the deposition of copper on substrates or in or on porous solids in an Atomic Layer Deposition process.Type: GrantFiled: August 7, 2006Date of Patent: February 10, 2009Assignee: E. I. du Pont de Nemours and CompanyInventor: Kyung-Ho Park
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Patent number: 7473637Abstract: The use of atomic layer deposition (ALD) to form a conductive titanium nitride layer produces a reliable structure for use in a variety of electronic devices. The structure is formed by depositing titanium nitride by atomic layer deposition onto a substrate surface using a titanium-containing precursor chemical such as TDEAT, followed by a mixture of ammonia and carbon monoxide or carbon monoxide alone, and repeating to form a sequentially deposited TiN structure. Such a TiN layer may be used as a diffusion barrier underneath another conductor such as aluminum or copper, or as an electro-migration preventing layer on top of an aluminum conductor. ALD deposited TiN layers have low resistivity, smooth topology, high deposition rates, and excellent step coverage and electrical continuity.Type: GrantFiled: July 20, 2005Date of Patent: January 6, 2009Assignee: Micron Technology, Inc.Inventors: Brenda D Kraus, Eugene P. Marsh
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Publication number: 20080251388Abstract: A method of preparing a highly thermally conductive circuit substrate includes the steps of preparing a metallic substrate, producing an insulated layer on a surface of the metallic substrate, producing an intermediate medium layer on a surface of the insulated layer, and producing an electrically conductive main layer on a surface of the intermediate medium layer.Type: ApplicationFiled: July 10, 2007Publication date: October 16, 2008Applicant: Cosmos Vacuum Technology Corp.Inventors: Hsu-Tan HUANG, Chung-Lin Chou
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Publication number: 20080254232Abstract: An interconnect structure for integrated circuits incorporates a layer of cobalt nitride that facilitates the nucleation, growth and adhesion of copper wires. The cobalt nitride may deposited on a refractory metal nitride or carbide layer, such as tungsten nitride or tantalum nitride, that serves as a diffusion barrier for copper and also increases the adhesion between the cobalt nitride and the underlying insulator. The cobalt nitride may be formed by chemical vapor deposition from a novel cobalt amidinate precursor. Copper layers deposited on the cobalt nitride show high electrical conductivity and can serve as seed layers for electrochemical deposition of copper conductors for microelectronics.Type: ApplicationFiled: April 9, 2008Publication date: October 16, 2008Applicant: PRESIDENT AND FELLOWS OF HARVARD COLLEGEInventors: Roy G. GORDON, Hoon KIM, Harish BHANDARI
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Publication number: 20080241358Abstract: A method is provided for low temperature catalyst-assisted atomic layer deposition of silicon-containing films such as SiO2 and SiN. The method includes exposing a substrate surface containing X—H functional groups to a first R1—X—R2 catalyst and a gas containing silicon and chlorine to form an X/silicon/chlorine complex on the surface, and forming a silicon-X layer terminated with the X—H functional groups by exposing the X/silicon/chlorine complex on the substrate surface to a second R1—X—R2 catalyst and a X—H functional group precursor. The method further includes one or more integrated in-situ reactive treatments that reduce or eliminate the need for undesired high-temperature post-deposition processing. One reactive treatment includes hydrogenating unreacted X—H functional groups and removing carbon and chlorine impurities from the substrate surface. Another reactive treatment saturates the silicon-X layer with additional X—H functional groups.Type: ApplicationFiled: March 30, 2007Publication date: October 2, 2008Applicant: TOKYO ELECTON LIMITEDInventors: Raymond Joe, Meenakshisundaram Gandhi
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Publication number: 20080241357Abstract: A method for depositing a thin film on a substrate in a vapor deposition system is described. Prior to the deposition process, the substrate is provided within the vapor deposition system and coupled to an upper surface of a substrate holder within the vapor deposition system, whereby the substrate is heated to a deposition temperature in a first gaseous atmosphere. Thereafter, the first gaseous atmosphere is displaced by a second gaseous atmosphere, and the pressure is adjusted to a deposition pressure. The second gaseous atmosphere comprises a gaseous composition that is substantially the same as the carrier gas utilized to transport film precursor vapor to the substrate and the optional dilution gas utilized to dilute the carrier gas and film precursor vapor.Type: ApplicationFiled: March 28, 2007Publication date: October 2, 2008Applicant: TOKYO ELECTRON LIMITEDInventor: Kenji Suzuki