With Posttreatment Of Coating Or Coating Material Patents (Class 427/97.6)
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Publication number: 20150104562Abstract: A fully additive method for forming multilayer electrical interconnects for printed electronic and/or optoelectronic devices is disclosed. Electrical interconnects are fabricated by directly ink-jet printing a dielectric material with selective interconnection holes, and then ink jet printing conductive patterns and filling the interconnection holes with conductive material to form multilayer interconnects. A method for manufacturing a multilayer printed electronic system utilizing the invention is also disclosed. Other embodiments are described and claimed.Type: ApplicationFiled: October 10, 2013Publication date: April 16, 2015Applicant: OMEGA OPTICS, INC.Inventors: Harish Subbaraman, Ray T. Chen
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Patent number: 8986819Abstract: A non-catalytic palladium precursor composition is disclosed, including a palladium salt and an organoamine, wherein the composition is substantially free of water. The composition permits the use of solution processing methods to form a palladium layer on a wide variety of substrates, including in a pattern to form circuitry or pathways for electronic devices.Type: GrantFiled: October 16, 2013Date of Patent: March 24, 2015Assignee: Xerox CorporationInventors: Yiliang Wu, Ping Liu
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Publication number: 20150070855Abstract: A circuit board includes a ceramics substrate composed of ceramics and a conductor portion provided on the ceramics substrate. The conductor portion is composed of a stacked body including, in order from the ceramics substrate side, an under layer that contains a Group 6 element and a glass material, and a metal layer that contains a low-melting-point metal. A portion of the low-melting-point metal constituting the metal layer migrates to the under layer.Type: ApplicationFiled: September 10, 2014Publication date: March 12, 2015Inventors: Tetsuro MIYAO, Tetsuya OTSUKI, Hideki ISHIGAMI, Yukihiko SHIOHARA, Hidefumi NAKAMURA
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Publication number: 20150060119Abstract: A conductive structure comprises a plurality of first nanowires and a plurality of second nanowires. The first nanowires extend along a first direction substantially. The second nanowires extend along a second direction substantially, and at least a part of the second nanowires electrical connect to the first nanowires. The included angle between the first and second directions is nonzero. A manufacturing method of the conductive structure is also disclosed.Type: ApplicationFiled: November 27, 2013Publication date: March 5, 2015Applicant: National Tsing Hua UniversityInventors: Hao-Wu LIN, Kai-Ming CHIANG, Jung-Hao CHANG, Cheng-Yu HUANG, Chih-Wei LU
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Publication number: 20150060132Abstract: An object to be achieved by the present invention is to provide a conductive pattern having such a level of adhesion that a conductive layer containing a conductive substance such as silver does not separate from a primer layer with time. The present invention relates to a conductive pattern including a conductive layer (A) containing a compound (a1) having a basic nitrogen atom-containing group and a conductive substance (a2); a primer layer (B) containing a compound (b1) having a functional group [X]; and a substrate layer (C), the conductive layer (A), the primer layer (B), and the substrate layer (C) being stacked, in which a bond is formed by reacting the basic nitrogen atom-containing group of the compound (a1) contained in the conductive layer (A) with the functional group [X] of the compound (b1) contained in the primer layer (B).Type: ApplicationFiled: March 8, 2013Publication date: March 5, 2015Applicant: DIC CORPORATIONInventors: Akira Murakawa, Jun Shirakami, Wataru Fujikawa, Yukie Saitou
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Patent number: 8840967Abstract: The present invention relates to a method for manufacturing a printed circuit board including a flame retardant insulation layer. The printed circuit board of the present invention exhibits excellent thermal stability and excellent mechanical strength, is suitable for imprinting lithography process, provides improved reliability by reducing coefficient of thermal expansion, and has excellent adhesion between circuit patterns and an insulation layer.Type: GrantFiled: September 16, 2011Date of Patent: September 23, 2014Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Jae-Choon Cho, Myeong-Ho Hong, Hwa-Young Lee, Hee-Sun Chun, Choon-Keun Lee
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Patent number: 8815332Abstract: An apparatus, comprising two conductive surfaces or layers and a nanostructure assembly bonded to the two conductive surfaces or layers to create electrical or thermal connections between the two conductive surfaces or layers, and a method of making same.Type: GrantFiled: August 9, 2012Date of Patent: August 26, 2014Assignee: Smoltek ABInventors: Mohammad Shafiqul Kabir, Andrzej Brud
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Patent number: 8808790Abstract: A method of manufacturing a submillimetric electroconductive grid coated with an overgrid on a substrate includes: the production of a mask having submillimetric openings by the deposition of a solution of colloidal polymeric nanoparticles that are stabilized and dispersed in a solvent, the polymeric particles having a glass transition temperature Tg and the drying of the masking layer at a temperature below the Tg until the mask, with straight edges, is obtained, the formation of the electroconductive grid by a deposition of electroconductive material, referred to as grid material, a heat treatment of the masking layer with the grid material at a temperature greater than or equal to 0.Type: GrantFiled: September 25, 2009Date of Patent: August 19, 2014Assignee: Saint-Gobain Glass FranceInventors: Georges Zagdoun, Bernard Nghiem, Eddy Royer
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Patent number: 8808791Abstract: A method is provided which includes forming a metal layer and converting at least a portion of the metal layer to a hydrated metal oxide layer. Another method is provided which includes selectively depositing a dielectric layer upon another dielectric layer and selectively depositing a metal layer adjacent to the dielectric layer. Consequently, a microelectronic topography is formed which includes a metal feature and an adjacent dielectric portion comprising lower and upper layers of hydrophilic and hydrophobic material, respectively. A topography including a metal feature having a single layer with at least four elements lining a lower surface and sidewalls of the metal feature is also provided herein. The fluid/s used to form such a single layer may be analyzed by test equipment configured to measure the concentration of all four elements. In some cases, the composition of the fluid/s may be adjusted based upon the analysis.Type: GrantFiled: October 17, 2013Date of Patent: August 19, 2014Assignee: Lam Research CorporationInventors: Igor C. Ivanov, Weiguo Zhang, Artur Kolics
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Patent number: 8802183Abstract: The system of the present invention includes a conductive element, an electronic component, and a partial power source in the form of dissimilar materials. Upon contact with a conducting fluid, a voltage potential is created and the power source is completed, which activates the system. The electronic component controls the conductance between the dissimilar materials to produce a unique current signature. The system can also measure the conditions of the environment surrounding the system.Type: GrantFiled: July 11, 2011Date of Patent: August 12, 2014Assignee: Proteus Digital Health, Inc.Inventors: Jeremy Frank, Peter Bjeletich, Hooman Hafezi, Robert Azevedo, Robert Duck, Iliya Pesic, Benedict Costello, Eric Snyder
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Publication number: 20140187112Abstract: Disclosed herein are a prepreg, including: an inorganic fiber, an organic fiber, or a hybrid fiber obtained by mix-weaving the inorganic fiber and the organic fiber, coated with a thermally conductive component or impregnated with a thermally conductive component; and a cross-linkable resin for impregnating the fiber therewith, a method for manufacturing the same, and a copper clad laminate using the same, so that the prepreg and the copper clad laminate can maintain a low coefficient of thermal expansion and a high modulus of elasticity and have excellent heat radiation property.Type: ApplicationFiled: December 24, 2013Publication date: July 3, 2014Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Sang Hyun Shin, Joon Seok Kang, Jang Bae Son, Kwang Jik Lee, Hye Sook Shin, Hyun Chul Jung
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Publication number: 20140138131Abstract: An article includes a patterned substrate including a substrate surface with an inorganic electro-conductive trace adjacent thereto (wherein the substrate and the inorganic material of the trace each has an index of refraction), and a layer including a polymerized acrylate matrix adjacent to at least a portion of the surface of the substrate and the inorganic electro-conductive trace, wherein the layer has an index of refraction that is within ±10% of the average of the indices of refraction of the substrate and the inorganic material of the trace.Type: ApplicationFiled: March 15, 2013Publication date: May 22, 2014Applicant: 3M INNOVATIVE PROPERTIES COMPANYInventors: ENCAI HAO, ABDUJABAR K. DIRE, ALBERT I. EVERAERTS, TAO LIU, ROSS E. BEHLING, GUY D. JOLY
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Publication number: 20140141238Abstract: An object of the present invention is to provide a conductive coating film formed on a polyimide-based insulating substrate by using a metal powder paste which can exhibit a good conductivity and good adhesion to the insulating substrate. By forming a resin cured layer having a solvent-soluble content of not more than 20% by weight and a thickness of not more than 5 ?m on a polyimide-based insulating substrate; forming a metal powder-containing coating layer on the resin cured layer by using a metal powder paste; and then subjecting the resulting coating layer to heat treatment with superheated steam, it is possible to obtain a conductive coating film which can exhibit a good conductivity and good adhesion to the insulating substrate.Type: ApplicationFiled: May 17, 2012Publication date: May 22, 2014Applicants: TOYOBO CO., LTD., TODA KOGYO CORPORATIONInventors: Takeshi Yatsuka, Chiho Ito, Yasuo Kakihara, Hirotoshi Kizumoto, Koji Shoki
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Publication number: 20140072150Abstract: A microelectromechanical microphone and method of manufacturing the same are disclosed. The microphone has a moveable diaphragm and a fixed backplate that create a variable capacitance. A fixed anchor electrically coupled to the diaphragm has an electrode that measures the variable capacitance, but also measures an unwanted, additive, parasitic capacitance. Various embodiments include a reference electrode, manufactured in the same deposition layer as the diaphragm or anchor, that measures only the parasitic capacitance. A circuit is provided either on-chip or off-chip that subtracts the capacitance measured at the reference electrode from that measured at the anchor, thereby producing only the desired variable capacitance as output. Because the reference electrode is deposited at the same time as the diaphragm or anchor, only minimal changes are required to existing manufacturing techniques.Type: ApplicationFiled: September 11, 2012Publication date: March 13, 2014Applicant: ANALOG DEVICES, INC.Inventors: Fang Liu, Kuang L. Yang
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Publication number: 20140057428Abstract: A layer of material having a low thermal conductivity is coated over a substrate. A film of conductive ink is then coated over the layer of material having the low thermal conductivity, and then sintered. The film of conductive ink does not absorb as much energy from the sintering as the film of conductive ink coated over the layer of material having the low thermal conductivity. The layer of material having the low thermal conductivity maybe a polymer, such as polyimide.Type: ApplicationFiled: November 7, 2013Publication date: February 27, 2014Applicant: APPLIED NANOTECH HOLDINGS, INC.Inventors: Zvi Yaniv, Mohshi Yang, Peter B. Laxton
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Publication number: 20140035168Abstract: A bonding pad for thermocompression bonding of a carrier material to a further carrier material includes a base layer and a top layer. The base layer is made of metal, is deformable, and is connected to the carrier material. The metal is nickel-based. The top layer is metallic and is connected directly to the base layer. The top layer is arranged at least on a side of the base layer which faces away from the carrier material. The top layer has a smaller layer thickness than the base layer. In at least one embodiment, the top layer has a greater oxidation resistance than the base layer.Type: ApplicationFiled: July 30, 2013Publication date: February 6, 2014Applicant: Robert Bosch GmbHInventors: Christoph Schelling, David Borowsky
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Patent number: 8623450Abstract: For a method for producing a flexible circuit configuration in the form of a layer sequence of at least one insulating layer and at least one conductive layer, typically multiple insulating layers (N1, N2, N3, NF) and multiple structured conductive layers (L1, L2), the layer sequence for the flexible circuit configuration is deposited on a rigid substrate so that the adhesion of the layer sequence with respect to the substrate is less in an inner area, in which at least one, preferably multiple flexible circuit configurations are created, than in an edge area (RB) which surrounds the inner area (ZB). An intermediate layer can advantageously be deposited for this purpose in the edge area, which causes a stronger adhesion of the layer sequence over the edge area than the inner area, which is not provided with an intermediate layer.Type: GrantFiled: October 1, 2010Date of Patent: January 7, 2014Assignee: Cicor Management AGInventors: Ernst Feurer, Bruno Holl, Alexander Kaiser, Karin Ruess
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Publication number: 20130344232Abstract: A method of forming a conductive feature on a three-dimensional object may include depositing a composition comprising nanoparticles onto a portion of the three-dimensional object, and annealing the composition to form the conductive feature. In another embodiment, a method of forming a conductive feature on a three-dimensional object may include printing a composition comprising nanoparticles to produce a contiguous line over a non-planar portion of the three-dimensional object, and heating the composition to form a conductive feature that has conductivity throughout.Type: ApplicationFiled: June 22, 2012Publication date: December 26, 2013Applicant: XEROX CORPORATIONInventors: Naveen CHOPRA, Yiliang WU, Ping LIU, Barkev KEOSHKERIAN, Michelle CHRETIEN
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Publication number: 20130333675Abstract: A sensor assembly with a protective coating and a method of applying the coating is disclosed. The sensor assembly includes a sensor, a first conductive lead extending from the sensor, a second conductive lead extending from the sensor, and a protective coating encapsulating the sensor and portions of the first conductive lead and the second conductive lead proximate to the sensor, wherein the protective coating comprises a fluoroelastomeric polymer. The coating is applied by immersing the sensor assembly into a cooled fluoroelastomeric polymer and then withdrawing the sensor assembly.Type: ApplicationFiled: June 13, 2012Publication date: December 19, 2013Applicant: General Electric CompanyInventor: John David Seaton
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Patent number: 8609201Abstract: An infrared energy oxidizing and/or curing process includes an infrared oxidation zone having an infrared energy source operable to emit infrared energy that oxidizes a conductive thin film deposited or established on a glass substrate to establish a light transmissive or transparent conductive thin film for manufacturing of a touch panel. Optionally, the infrared energy curing process provides an in-line infrared energy curing process that oxidizes the conductive thin film on the glass substrate as the glass substrate is moved past the infrared energy source. Optionally, the infrared energy curing process bonds a thick film silver frit electrode pattern to the conductively coated glass substrate. Optionally, the infrared energy curing process reduces the transparent conductive thin film.Type: GrantFiled: July 2, 2008Date of Patent: December 17, 2013Assignee: TPK Touch Solutions Inc.Inventor: Catherine A. Getz
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Patent number: 8603588Abstract: Disclosed is a composition comprising a hydrolysate of an alkoxysilane compound, a hydrolysate of a siloxane compound represented by Formula (1), a surfactant, and an element having an electronegativity of 2.5 or less. In Formula (1), RA and RB independently represent a hydrogen atom, a phenyl group, —CaH2a+1, —(CH2)b(CF2)cCF3 or —CdH2d?1, RA and RB are not both hydrogen atoms simultaneously, RC and RD independently represent a single bond that links a silicon atom and an oxygen atom to form a cyclic siloxane structure, or each independently represent a hydrogen atom, a phenyl group, —CaH2a+1, —(CH2)b(CF2)cCF3, or —CdH2d?1, a represents an integer of 1 to 6, b represents an integer of 0 to 4, c represents an integer of 0 to 10, d represents an integer of 2 to 4, and n represents an integer of 3 or greater.Type: GrantFiled: March 30, 2009Date of Patent: December 10, 2013Assignee: Mitsui Chemicals, Inc.Inventors: Kazuo Kohmura, Hirofumi Tanaka
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Patent number: 8592038Abstract: The invention relates to a decorative coating having at least one layer of two-component paint and one protective resin surface layer. The resin is translucent or transparent and the two-component paint has at least one first component of prepolymer type based on bisphenol and epichlorohydrin and at least one second component of polyamine type. Another subject of the invention is the use of such a coating for covering surfaces such as a floor or a worktop or a sink or sanitary ware of wash basin, shower cubicle, etc. type.Type: GrantFiled: November 12, 2008Date of Patent: November 26, 2013Inventors: Rocco Palazzolo, Moktar Mejladi
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Patent number: 8586133Abstract: A method is provided which includes forming a metal layer and converting at least a portion of the metal layer to a hydrated metal oxide layer. Another method is provided which includes selectively depositing a dielectric layer upon another dielectric layer and selectively depositing a metal layer adjacent to the dielectric layer. Consequently, a microelectronic topography is formed which includes a metal feature and an adjacent dielectric portion comprising lower and upper layers of hydrophilic and hydrophobic material, respectively. A topography including a metal feature having a single layer with at least four elements lining a lower surface and sidewalls of the metal feature is also provided herein. The fluid/s used to form such a single layer may be analyzed by test equipment configured to measure the concentration of all four elements. In some cases, the composition of the fluid/s may be adjusted based upon the analysis.Type: GrantFiled: July 2, 2012Date of Patent: November 19, 2013Assignee: Lam Research CorporationInventors: Igor C. Ivanov, Weiguo Zhang, Artur Kolics
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Publication number: 20130299223Abstract: Disclosed are a printed circuit board and a method for manufacturing the same. The method for manufacturing the printed circuit board includes forming a base circuit board including a cavity circuit pattern in a cavity region on upper and lower portions of a substrate and internal circuit layers outside the cavity region, forming a cavity separation layer on the cavity circuit pattern, forming at least one pair of an insulating layer and a circuit layer on the base circuit board, cutting the insulating layer and the cavity separation layer provided on an etch stop pattern by controlling a focal length of a laser beam such that the laser beam reaches a surface of the base circuit board, and removing the insulating layer by separating the cavity separation layer to form the cavity. The cavity separation layer is formed on the cavity circuit pattern, and the resultant structure is cut to the cavity separation layer by using a laser so that the insulating layer is separated.Type: ApplicationFiled: July 1, 2011Publication date: November 14, 2013Applicant: LG INNOTEK CO., LTD.Inventors: Jae Hyoun Yoo, Hyung Jong Kim, Jun Soo Park, Ki Yong Lee, Jin Goo Jeon
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Patent number: 8501279Abstract: A process for production of a flexible laminated sheet having one or more laminated bodies each provided with a metal foil formed on one side of a resin film, the process comprising a coating step in which a varnish containing a polyamic acid and a solvent is coated onto the metal foil to form a coated film, a holding step in which the coated film formed on the metal foil is held, a drying step in which at least a portion of the solvent in the varnish is removed to form a layer composed of a resin composition, and a resin film-forming step in which the layer composed of the resin composition is heated to form a resin film containing a polyimide resin. The conditions for each step from the coating step up to the resin film-forming step are adjusted based on a target for the content of metal elements in the resin film.Type: GrantFiled: October 19, 2006Date of Patent: August 6, 2013Assignee: Hitachi Chemical Company, Ltd.Inventors: Masahiko Suzuki, Kazuhito Obata, Katsuyuki Masuda, Kenichi Tomioka, Masaki Takeuchi, Sumio Yoshida, Hirokazu Suzuki, Yoshitsugu Matsuura
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Patent number: 8479387Abstract: In a method of manufacturing a three-dimensional (3D) circuit device, conducting circuits are formed on a non-conductive base through electroplating. The non-conductive base, and a circuit pattern section, at least one conducting junction and at least one current-guiding junction provided on the base are formed through double injection molding process. An electrically conductive interface layer is formed on the circuit pattern section and the junctions; and then, metal circuits are formed on the circuit pattern section through electroplating. By providing the conducting junction and the current-guiding junction, when forming metal circuits through electroplating, electroplating current can be evenly distributed over the circuit pattern section to form metal coating with uniform thickness, which enables upgraded production efficiency and reduced cost in manufacturing a 3D circuit device.Type: GrantFiled: October 20, 2010Date of Patent: July 9, 2013Assignee: Kuang Hong Precision Co., Ltd.Inventor: Cheng-Feng Chiang
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Publication number: 20130169382Abstract: Disclosed herein are a common mode filter and a method for manufacturing the same. The common mode filter includes a first insulator sheet; a first circuit layer having a first-layered first coil and a first-layered second coil alternately and separately arranged; a second insulator sheet laminated on the first circuit layer; and a second circuit layer having a second-layered first coil and a second-layered second coil alternately and separately arranged, the second-layered first coil being connected to the first-layered first coil and the second-layered second coil being connected to the first-layered second coil through the plurality of penetration holes.Type: ApplicationFiled: May 15, 2012Publication date: July 4, 2013Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Jin Gu Kim, Jong Yun Lee, Young Do Kweon, Chang Bae Lee, Young Seuck Yoo
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Publication number: 20130161085Abstract: Disclosed herein are a printed circuit board (PCB) and a method for manufacturing the same. The PCB includes a base substrate, a circuit layer formed on the base substrate and including a connection pad, a solder resist layer formed on an upper portion of the base substrate and having an opening exposing the connection pad, a metal post formed on upper portions of the connection pad and the solder resist layer and having a plurality of diameters, and a seed layer formed on the upper portion of the solder resist layer and inner walls of the opening along an interface of the metal post.Type: ApplicationFiled: February 22, 2012Publication date: June 27, 2013Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Hueng Jae Oh, Boo Yang Jung, Dae Young Lee, Jin Won Choi
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Patent number: 8415252Abstract: A metal interconnect structure provides high adhesive strength between copper atoms in a copper-containing structure and a self-aligned copper encapsulation layer, which is selectively deposited only on exposed copper surfaces. A lower level metal interconnect structure comprises a first dielectric material layer and a copper-containing structure embedded in a lower metallic liner. After a planarization process that forms the copper-containing structure, a material that forms Cu—S bonds with exposed surfaces of the copper-containing structure is applied to the surface of the copper-containing structure. The material is selectively deposited only on exposed Cu surfaces, thereby forming a self-aligned copper encapsulation layer, and provides a high adhesion strength to the copper surface underneath. A dielectric cap layer and an upper level metal interconnect structure can be subsequently formed on the copper encapsulation layer.Type: GrantFiled: January 7, 2010Date of Patent: April 9, 2013Assignee: International Business Machines CorporationInventors: Tien-Jen Cheng, Abhishek Dube, Zhengwen Li, Huilong Zhu
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Publication number: 20130037311Abstract: A base material or composite material such as graphite, may be combined with another material, such as aluminum oxide or polyimide, to produce a new insulating thermal management material. The base material may be impregnated with another metal to create a composite base material.Type: ApplicationFiled: August 9, 2012Publication date: February 14, 2013Applicant: APPLIED NANOTECH HOLDINGS, INC.Inventors: NAN JIANG, ZVI YANIV
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Patent number: 8318254Abstract: A copolymer deposited with particles of catalytic metal is disclosed in the present invention, which is formed from an ethylenically unsaturated monomer and a hydrophilic monomer, and the catalytic metal is Au, Ag, Pd, Pt or Ru. The copolymer is hydrophilic when the temperature is lower than a specific temperature, and will become hydrophobic when the temperature is greater than the specific temperature. The present invention also discloses a method for forming a metal layer on a substrate via electroless plating, which includes contacting the substrate with an ink composition, drying the ink composition on the substrate, and contacting the dried ink composition with an electroless plating solution, wherein the ink composition contains the copolymer of the present invention in an aqueous phase. The present invention further discloses a method for forming metal conductors in through holes of a substrate.Type: GrantFiled: October 30, 2008Date of Patent: November 27, 2012Assignee: National Defense UniversityInventors: Yuh Sung, Ming-Der Ger, Chang-Ping Chang, Chun-Chieh Tseng, Wen-Ding Chen
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Publication number: 20120285734Abstract: Provided is a roughened copper foil which has excellent properties in forming a fine patterned-circuit and good transmission properties in a high-frequency range and show high adhesiveness to a resin base and good chemical resistance. A surface-roughened copper foil, which is obtained by roughening at least one face of a base copper foil (untreated copper foil) so as to increase the surface roughness (Rz) thereof, relative to the surface roughness (Rz) of said base copper foil, by 0.05-0.3 ?m and has a roughened surface with a surface roughness (Rz) after roughening of 1.1 ?m or less, wherein said roughened surface comprises roughed grains in a sharp-pointed convex shape which have a width of 0.3-0.8 ?m, a height of 0.4-1.8 ?m and an aspect ratio [height/width] of 1.2-3.5.Type: ApplicationFiled: January 21, 2011Publication date: November 15, 2012Applicant: Furukawa Electric Co., Ltd.Inventors: Takeo Uno, Satoshi Fujisawa
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Patent number: 8287943Abstract: The invention relates to the preparation of multilayer microcomponents which comprise one or more films, each consisting of a material M selected from metals, metal alloys, glasses, ceramics and glass-ceramics. The method consists in depositing on a substrate one or more films of an ink P, and one or more films of an ink M, each film being deposited in a predefined pattern selected according to the structure of the microcomponent, each film of ink P and each film of ink M being at least partially consolidated before deposition of the next film; effecting a total consolidation of the films of ink M partially consolidated after their deposition, to convert them to films of material M; totally or partially removing the material of each of the films of ink P. An ink P consists of a thermoset resin containing a mineral filler or a mixture comprising a mineral filler and an organic binder. An ink M consists of a mineral material precursor of the material M and an organic binder.Type: GrantFiled: January 5, 2007Date of Patent: October 16, 2012Assignee: Centre National de la Recherche ScientifiqueInventors: Claude Lucat, Francis Menil, Hélène Debeda-Hickel, Patrick Ginet
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Publication number: 20120163752Abstract: Disclosed herein is a method for manufacturing a printed circuit board with optical waveguides capable of reducing light loss by forming a bent portion having a changing pattern shape on a core layer and attaching a reflective member thereto to increase reflectivity. The method for manufacturing a printed circuit board with optical waveguides includes; (a) forming a lower clad layer on a base substrate; (b) applying a core material onto the lower clad layer; (c) performing exposure on the core material using a photo mask having a pattern; (d) performing development on the core material subjected to the exposure and forming a bent portion having a changing pattern shape to form a core layer; (e) applying an upper clad layer onto the lower clad layer having the core layer formed thereon; (f) performing exposure and development on the upper clad layer to expose a reflective portion of the machined bent portion to the outside; and (g) attaching a reflective member to the reflective portion exposed to the outside.Type: ApplicationFiled: June 8, 2011Publication date: June 28, 2012Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Sanghoon Kim, Joonsung Kim, Hanseo Cho
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Patent number: 8197884Abstract: Process for producing a solar absorber coating, which comprises the steps: coating of a substrate with a titanium precursor solution to produce a titanium dioxide layer by the sol-gel technique and heat treatment of the coated substrate to pyrolyse and crystallize the layer, characterized in that silver ions are added to the titanium precursor solution prior to coating in such an amount that the heat-treated layer has a proportion by mass of silver in the range from 10% to 80% and pyrolysis and crystallization of the layer are carried out with illumination of the layer with visible light.Type: GrantFiled: June 19, 2007Date of Patent: June 12, 2012Assignee: Zyrus Beteiligungsgesellschaft mbH & Co. Patente I KGInventor: Mohammed Es-Souni
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Publication number: 20120103662Abstract: Disclosed herein are a printed circuit board including a first low-viscosity solder resist layer formed on one surface of a substrate having circuit patterns formed thereon and a second high-viscosity solder resist layer stacked on the first solder resist layer, thereby being advantageous in controlling the deviation in application thickness of solder resist (SR), while having excellent adhesion to the substrate, and a manufacturing method thereof.Type: ApplicationFiled: March 18, 2011Publication date: May 3, 2012Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Chang Bo Lee, Cheol Ho Choi, Yoong Oh
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Publication number: 20120031656Abstract: Provided are a substrate for a printed wiring board, and a printed wiring board, which are not limited in size because vacuum equipment is not necessary for the production, in which an organic adhesive is not used, and which can include a conductive layer (copper foil layer) having a sufficiently small thickness. Also provided are a method for producing the substrate for a printed wiring board, and a method for producing the printed wiring board. A substrate 1 for a printed wiring board includes an insulating base 11, a first conductive layer 12 that is stacked on the insulating base 11, and a second conductive layer 13 that is stacked on the first conductive layer 12, in which the first conductive layer 12 is a coating layer composed of a conductive ink containing metal particles, and the second conductive layer 13 is a plating layer.Type: ApplicationFiled: April 13, 2010Publication date: February 9, 2012Inventors: Yoshio Oka, Takashi Kasuga, Issei Okada, Katsunari Mikage, Naota Uenishi, Yasuhiro Okuda
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Publication number: 20120021224Abstract: Methods for making composite membranes (graphene/graphene oxide platelet composite membranes) and methods of aligned transfer of such composite membranes to substrates are shown. Compositions and devices that include such composite membranes are further shown.Type: ApplicationFiled: June 2, 2011Publication date: January 26, 2012Applicant: CLEAN ENERGY LABS, LLCInventors: William Neil Everett, William Martin Lackowski, Joseph F. Pinkerton
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Publication number: 20110315438Abstract: A method for producing a laminated base material includes applying a liquid composition containing a solvent and a liquid crystal polyester to a substrate; and forming a covering material by removing the solvent. The substrate includes a conductor forming a circuit pattern on an insulating layer. The liquid composition covers the conductor. The polyester includes 30-50 mol % of (1), 25-35 mol % of (2), and 25-35 mol % of (3): -0-Ar1-00-??(1) —CO—Ar2-00-??(2) —X—Ar3—Y—??(3) wherein Ar1 is a phenylene or naphthylene group, Ar2 is a phenylene or naphthylene group, or (4), Ar3 is a phenylene group or (4), and X and Y each independently represent 0 or NH; and hydrogen atoms in Ar1, Ar2, or Ar3 are each substitutable with a halogen atom, or an alkyl or aryl group; —Ar11—Z—Ar12—??(4) wherein Ar11 and Ar12 each independently represent a phenylene or naphthylene group and Z represents 0, CO, or SO2.Type: ApplicationFiled: June 24, 2011Publication date: December 29, 2011Applicant: SUMITOMO CHEMICAL COMPANY, LIMITEDInventors: Toyonari ITO, Changbo SHIM
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Publication number: 20110278055Abstract: In a method of manufacturing a three-dimensional (3D) circuit device, conducting circuits are formed on a non-conductive base through electroplating. The non-conductive base, and a circuit pattern section, at least one conducting junction and at least one current-guiding junction provided on the base are formed through double injection molding process. An electrically conductive interface layer is formed on the circuit pattern section and the junctions; and then, metal circuits are formed on the circuit pattern section through electroplating. By providing the conducting junction and the current-guiding junction, when forming metal circuits through electroplating, electroplating current can be evenly distributed over the circuit pattern section to form metal coating with uniform thickness, which enables upgraded production efficiency and reduced cost in manufacturing a 3D circuit device.Type: ApplicationFiled: October 20, 2010Publication date: November 17, 2011Applicant: KUANG HONG PRECISION CO., LTD.Inventor: CHENG-FENG CHIANG
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METHOD FOR PREVENTING OR REDUCING SILVER MIGRATION IN THE CROSSOVER AREAS OF A MEMBRANE TOUCH SWITCH
Publication number: 20110281024Abstract: Disclosed is the use of carbon layers as barriers to prevent silver migration in circuitry crossovers, either over a bottom circuitry layer and/or beneath subsequent circuit layers.Type: ApplicationFiled: November 11, 2010Publication date: November 17, 2011Applicant: E. I. DU PONT DE NEMOURS AND COMPANYInventors: John C. Crumpton, Robert Paul Waldrop -
Publication number: 20110274829Abstract: For a method for producing a flexible circuit configuration in the form of a layer sequence of at least one insulating layer and at least one conductive layer, typically multiple insulating layers (N1, N2, N3, NF) and multiple structured conductive layers (L1, L2), the layer sequence for the flexible circuit configuration is deposited on a rigid substrate so that the adhesion of the layer sequence with respect to the substrate is less in an inner area, in which at least one, preferably multiple flexible circuit configurations are created, than in an edge area (RB) which surrounds the inner area (ZB). An intermediate layer can advantageously be deposited for this purpose in the edge area, which causes a stronger adhesion of the layer sequence over the edge area than the inner area, which is not provided with an intermediate layer.Type: ApplicationFiled: October 1, 2010Publication date: November 10, 2011Applicant: Cicor Management AGInventors: Ernst Feurer, Bruno Holl, Alexander Kaiser, Karin Ruess
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Patent number: 8039400Abstract: A conductive barrier material of a metallization system of a semiconductor device may be formed on the basis of one or more deposition/etch cycles, thereby providing a reduced material thickness in the bevel region, while enhancing overall thickness uniformity in the active region of the semiconductor substrate. In some illustrative embodiments, two or more deposition/etch cycles may be used, thereby providing the possibility to select reduced target values for the barrier thickness in the die regions, while also obtaining a significantly reduced thickness in the bevel region.Type: GrantFiled: April 6, 2009Date of Patent: October 18, 2011Assignee: GLOBALFOUNDRIES Inc.Inventors: Frank Koschinsky, Matthias Lehr, Holger Schuehrer
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Patent number: 8021712Abstract: The present invention relates to a wafer formed with an evaluation element and capable of improving productivity and a manufacturing method of an electronic component using the same. In a wafer according to the present invention, a plurality of elements connected to electrode films through lead-out conductive films are arranged and a chip area is defined for cutting out the plurality of elements in a given number. In the wafer, at least one evaluation element is formed in an area outside the chip area. The lead-out conductive films extend to the outside area and are connected to the evaluation elements. With this wafer, since the lead-out conductor is shared between the element and the evaluation element, the electrode film connected therewith can be shared, too.Type: GrantFiled: March 18, 2009Date of Patent: September 20, 2011Assignee: TDK CorporationInventors: Osamu Nakazawa, Nozomu Hachisuka, Tetsuya Hiraki
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Publication number: 20110214909Abstract: An enhanced substrate for making a printed circuit board (PCB) includes a hydrophobic silane coating of a silane composition intermixed with a silane coupling agent applied to a glass fiber substrate. The silane coupling agent is applied to the surface of the substrate for coupling the substrate to a varnish coating. Applying the silane coupling agent to the surface of the substrate creates surface silanols, which are implicated in conductive anodic filament (CAF) growth. A silane composition, which reacts with the surface silanols, is applied to the surface of the substrate having the silane coupling agent applied thereto to form the hydrophobic silane coating. The surface presented by the hydrophobic silane coating/substrate is hydrophobic and essentially silanol-free. This surface is then dried, and varnish is applied thereto. Then, the substrate, hydrophobic silane coating and varnish are subjected to curing conditions to define the PCB.Type: ApplicationFiled: March 5, 2010Publication date: September 8, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Dylan Joseph Boday, Joseph Kuczynski
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Patent number: 7989081Abstract: A resin composite copper foil comprising a copper foil and a resin layer containing a block copolymer polyimide and a maleimide compound, the resin layer being formed on one surface of the copper foil, a production process thereof, a copper-clad laminate using the resin composite copper foil, a production process of a printed wiring board using the copper-clad laminate, and a printed wiring board obtained by the above process.Type: GrantFiled: January 25, 2007Date of Patent: August 2, 2011Assignees: Mitsubishi Gas Chemical Company, Inc., PI R&D Co., Ltd.Inventors: Mitsuru Nozaki, Morio Gaku, Yasuo Tanaka, Eiji Nagata, Yasuo Kikuchi, Masashi Yano
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Publication number: 20110180309Abstract: A metallic liner stack including at least a Group VIIIB element layer and a CuMn alloy layer is deposited within a trench in a dielectric layer. Copper is deposited on the metallic liner stack and planarized to form a conductive interconnect structure, which can be a metal line, a metal via, or a combination thereof. The deposited copper and the metallic liner stack are annealed before or after planarization. The Mn atoms are gettered by the Group VIIIB element layer to form a metallic alloy liner including Mn and at least one of Group VIIIB elements. Mn within the metallic alloy liner combines with oxygen during the anneal to form MnO, which acts as a strong barrier to oxygen diffusion, thereby enhancing the reliability of the conductive interconnect structure.Type: ApplicationFiled: January 26, 2010Publication date: July 28, 2011Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.Inventors: Daniel C. Edelstein, Takeshi Nogami, Kazumichi Tsumura, Takamasa Usui
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Publication number: 20110139491Abstract: The present invention discloses an electrode of a biosensor, a manufacturing method thereof, and a biosensor thereof. The electrode of the biosensor comprises a flexible insulation layer, a resin layer, a first metal layer, a second metal layer, a third metal layer and a fourth metal layer. The resin layer is disposed between the flexible insulating layer and the first metal layer. The second metal layer is disposed between the first metal layer and the third metal layer, and the fourth metal layer is disposed on the third metal layer. The material of the first metal layer comprises copper foil. The material of the second metal layer comprises palladium. The material of the third metal layer comprises nickel, and the material of the fourth metal layer comprises gold or palladium. The electrode further comprises a biological active substance immobilized on the surface of the plurality of metal layers.Type: ApplicationFiled: June 4, 2010Publication date: June 16, 2011Applicants: BIOSENSORS ELECTRODE TECHNOLOGY CO., LTD.Inventor: YEN HSIANG CHANG
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Patent number: 7951446Abstract: There is provided a hard-to-sinter constraining green sheet and a method of manufacturing a multilayer ceramic substrate using the same. The hard-to-sinter constraining green sheet disposed at least one of top and bottom surfaces of a non-sintered multi-layer ceramic substrate, the hard-to-sinter constraining green sheet including: a first constraining layer having a surface to be positioned on the multi-layer ceramic substrate, the first constraining layer including a first organic binder and a first inorganic powder having a spherical shape or a quasi-spherical shape; and a second constraining layer bonded to a top surface of the first constraining layer and including a second organic binder and a second inorganic powder having a flake shape, the second constraining layer having a powder packing density lower than that of the first constraining layer.Type: GrantFiled: November 5, 2008Date of Patent: May 31, 2011Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Beom Joon Cho, Jong Myeon Lee, Myung Whun Chang
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Publication number: 20110120761Abstract: Epoxy resin compositions which comprise an epoxy resin (A), an active ester compound (B), and a triazine-containing cresol novolac resin (C), when cured and roughened, exhibit a roughed surface which has a high adhesion strength to a metal plated conductor, even though the roughness of the roughed surface is small, and provide an insulating layer which has a low coefficient of linear expansion and a low dielectric loss tangent.Type: ApplicationFiled: November 22, 2010Publication date: May 26, 2011Applicant: AJINOMOTO CO. INC.Inventor: Kenji KAWAI