Activating Or Catalyst Pretreatment Patents (Class 427/99.1)
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Patent number: 11028479Abstract: A method of forming a tungsten film on a surface of a target substrate having a base film is performed by repeating a cycle plural times. The cycle includes alternately supplying a tungsten chloride gas and a reducing gas for reducing the tungsten chloride gas, with a purge interposed therebetween, into a process container in which the target substrate is accommodated and that is maintained under a depressurized atmosphere. The method includes setting a supply flow rate of the tungsten chloride gas and a time of the cycle such that a ratio of a thickness of the base film etched by repeating the cycle the plural times to a thickness of the base film before repeating the cycle the plural times becomes smaller than a predetermined ratio in a state where an integrated flow rate of the tungsten chloride gas per one cycle is kept substantially constant.Type: GrantFiled: November 26, 2018Date of Patent: June 8, 2021Assignee: TOKYO ELECTRON LIMITEDInventors: Katsumasa Yamaguchi, Takashi Sameshima
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Patent number: 9181622Abstract: The present invention relates to a process for metallizing electrically nonconductive plastic surfaces of articles. During the process, the rack to which the said articles are fastened is subjected to a treatment for protection against metallization. Subsequently, the articles are metallized by means of known processes, wherein the racks remain free of metal.Type: GrantFiled: March 15, 2013Date of Patent: November 10, 2015Assignee: Atotech Deutschland GmbHInventor: Hermann Middeke
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Patent number: 8911608Abstract: The present invention provides a circuit creation technology that improves conductive line manufacture by adding active and elemental palladium onto the surface of a substrate. The palladium is disposed in minute amounts on the surface and does not form a conductive layer by itself, but facilitates subsequent deposition of a metal onto the surface, according to the pattern of the palladium, to form the conductive lines.Type: GrantFiled: May 13, 2010Date of Patent: December 16, 2014Assignee: SRI InternationalInventors: Sunity Sharma, Jaspreet Singh Dhau
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Patent number: 8828131Abstract: Disclosed is a catalyst application solution for plating an insulating portion of an object to be plated that comprises the insulating portion. The catalyst application solution is characterized by containing a water-soluble palladium compound, a reducer, a dispersant, catechol, a copper antioxidant and a buffering agent, and by having a pH of not less than 4.Type: GrantFiled: August 5, 2010Date of Patent: September 9, 2014Assignee: C. Uyemura & Co., Ltd.Inventors: Hisamitsu Yamamoto, Tetsuji Ishida
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Patent number: 8784638Abstract: A resin board that consists of at least one of a mixture of a plurality of types of resins having different degrees of susceptibility to erosion by an ozone solution, and a resin having, in a molecule, a plurality of types of components having different degrees of susceptibility to erosion by the ozone solution is treated with ozone water to form a reformed layer, and a catalyst metal is adsorbed by the reformed layer so as to form a resin-metal composite layer, on which a plating process is performed. In the resin board, a component or components that is/are likely to be eroded on by the ozone solution dissolves into the ozone solution, and pores or clearances on the order of nanometers are formed between the component(s) and a component or components that is/are less likely to be eroded by the ozone solution. With the plating deposited in the pores or clearances, the adhesion strength is improved due to an anchoring effect.Type: GrantFiled: October 18, 2012Date of Patent: July 22, 2014Assignee: Toyota Jidosha Kabushiki KaishaInventors: Takeshi Bessho, Kyoko Kumagai, Takashi Yoshida, Manabu Osamura, Toshihisa Shimo
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Patent number: 8703232Abstract: The present disclosure describes an article and a method of forming a microstructure. The method includes providing a substrate having a structured surface region comprising one or more recessed features with recessed surfaces. The structured surface region is substantially free of plateaus. The method includes disposing a fluid composition comprising a functional material and a liquid onto the structured surface region. The method includes evaporating liquid from the fluid composition. The functional material collects on the recessed surfaces such that a remainder of the structured surface region is substantially free of the functional material.Type: GrantFiled: June 25, 2009Date of Patent: April 22, 2014Assignee: 3M Innovative Properties CompanyInventors: Matthew S. Stay, Mikhail L. Pekurovsky, Cristin E. Moran, Matthew H. Frey
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Patent number: 8642117Abstract: A liquid composition for forming an activator-containing layer on a substrate, for activating a chemical reaction to produce a solid layer on the substrate, comprises activator, surfactant and solvent and/or binder. The liquid composition is deposited on a surface of a substrate, desirably by inkjet printing. The layer is used to activate a chemical reaction to produce a solid layer on the substrate surface, e.g. a layer of conductive metal. The surfactant in the liquid composition has beneficial effects on the behavior of the liquid composition when applied to certain substrates.Type: GrantFiled: May 16, 2006Date of Patent: February 4, 2014Assignee: Conductive Inkjet Technology LimitedInventor: Martyn Robinson
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Patent number: 8349394Abstract: A method of forming an electrode having an electrochemical catalyst layer is disclosed, which comprises providing a substrate with a conductive layer formed on the surface of a substrate, conditioning the surface of the substrate, immersing the substrate in a solution containing polymer-capped noble metal nanoclusters dispersed therein to form a polymer-protected electrochemical catalyst layer on the conditioned surface of the substrate, and thermally treating the polymer-protected electrochemical catalyst layer at a temperature approximately below 300° C.Type: GrantFiled: June 18, 2008Date of Patent: January 8, 2013Assignee: Tripod Technology CorporationInventors: Chao Peng, Jo-Lin Lan, Ya-Huei Chang, Wen-Chi Hsu, Hai-Peng Cheng, Shien-Ping Feng, Wen-Hsiang Chen, Tzu-Chien Wei
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Publication number: 20120321781Abstract: The present invention discloses a process for electroless plating of nickel onto copper features of a printed circuit board which suppresses extraneous nickel plating. The process comprises the steps i) activation of the copper features with palladium ions; ii) removal of excessive palladium ions or precipitates formed thereof with a pre-treatment composition comprising at least two different types of acids wherein one type is an organic amino carboxylic acid and iii) electroless plating of nickel.Type: ApplicationFiled: March 12, 2010Publication date: December 20, 2012Inventor: Elisabeth Zettelmeyer
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Patent number: 8323739Abstract: A method for forming a metal pattern on a substrate via printing and electroless plating is disclosed, which includes printing a pattern on the substrate with an ink composition, drying the printed pattern, and contacting the dried pattern with an electroless plating solution. The ink composition either contains components (i), (ii) and (iii), components (i) and (iv), or components (i) and (v), which are dissolved or dispersed in a solvent, wherein (i) is a binder; (ii) is a sulfate terminated polymer of an ethylenically unsaturated monomer; (iii) is a catalytic metal precursor; (iv) is a polymer of an ethylenically unsaturated monomer deposited with particles of catalytic metal; and (v) is a copolymer of an ethylenically unsaturated monomer and a hydrophilic monomer deposited with particles of catalytic metal. The binder (i) is a water swellable resin. The catalytic metal may be Au, Ag, Pd, Pt or Ru.Type: GrantFiled: November 8, 2007Date of Patent: December 4, 2012Assignee: National Defense UniversityInventors: Yuh Sung, Ming-Der Ger, Chang-Ping Chang, Chun-Chieh Tseng, Wen-Ding Chen
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Publication number: 20120171363Abstract: Disclosed is a catalyst application solution for plating an insulating portion of an object to be plated that comprises the insulating portion. The catalyst application solution is characterized by containing a water-soluble palladium compound, a reducer, a dispersant, catechol, a copper antioxidant and a buffering agent, and by having a pH of not less than 4.Type: ApplicationFiled: August 5, 2010Publication date: July 5, 2012Applicant: C. UYEMURA & CO., LTD.Inventors: Hisamitsu Yamamoto, Tetsuji Ishida
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Patent number: 8163331Abstract: A terminal to, most commonly, a ceramic capacitor, most commonly a multilayer ceramic capacitor (MLCC), is formed by electroless plating, also known as electroless deposition or simply as electrodeposition. In the MLCC having a multiple parallel interior plates brought to, and exposed at, at least one, first, surface, an electrically-conductive first-metal layer, preferably Cu, is electrolessly deposited upon this first surface directly in contact with, mechanically connected to, and electrically connected to, the edges of these interior plates. Lateral growth of the electrolessly-deposited first-metal is sufficient to span from exposed plate to exposed plate, electrically connecting the plates. One or more top layers, preferably one of Ni and one of Sn and Pb, are deposited, preferably by plating and more preferably by electrolytic plating, on top of the electrolessly-deposited Cu.Type: GrantFiled: March 12, 2008Date of Patent: April 24, 2012Assignee: Presidio Components, Inc.Inventor: Hung Van Trinh
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Patent number: 8124174Abstract: Part or whole of an electroless gold plating film of a plated film laminate including an electroless nickel plating film, an electroless palladium plating film and an electroless gold plating film is formed by an electroless gold plating using an electroless gold plating bath including a water-soluble gold compound, a complexing agent, formaldehyde and/or a formaldehyde-bisulfite adduct, and an amine compound represented by the following general formula R1—NH—C2H4—NH—R2 or R3—(CH2—NH—C2H4—NH—CH2)n—R4. The method of the invention does not need two types of baths, a flash gold plating bath and a thick gold plating bath for thickening. Gold plating films of different thicknesses suited for solder bonding or wire bonding can be formed using only one type of gold plating bath.Type: GrantFiled: April 14, 2008Date of Patent: February 28, 2012Assignee: C. Uyemura & Co., Ltd.Inventors: Seigo Kurosaka, Yukinori Oda, Akira Okada, Ayumi Okubo, Masayuki Kiso
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Publication number: 20110256363Abstract: A surface metal film material including, in this order, a substrate, a polymer layer that receives a plating catalyst or a precursor thereof, and a metal film formed by plating, wherein, when x ?m represents surface roughness (Ra) at the interface between the substrate and the polymer layer, and y ?m represents surface roughness (Ra) at the interface between the polymer layer and the metal film, x>y and 5 ?m>x>0.1 ?m, and wherein, when T ?m represents a thickness of the polymer layer, T and x satisfy the relationship 2x?T.Type: ApplicationFiled: December 8, 2009Publication date: October 20, 2011Applicant: FUJIFILM CORPORATIONInventor: Masataka Satou
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Publication number: 20110212260Abstract: Some embodiments include methods of forming conductive material within high aspect ratio openings and low aspect ratio openings. Initially, the high aspect ratio openings may be filled with a first conductive material while the low aspect ratio openings are only partially filled with the first conductive material. Additional material may then be selectively plated over the first conductive material within the low aspect ratio openings relative to the first conductive material within the high aspect ratio openings. In some embodiments, the additional material may be activation material that only partially fills the low aspect ratio opening, and another conductive material may be subsequently plated onto the activation material to fill the low aspect ratio openings.Type: ApplicationFiled: May 7, 2011Publication date: September 1, 2011Applicant: Micron Technology, Inc.Inventor: Nishant Sinha
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Patent number: 7959977Abstract: A substrate processing method and apparatus can securely carry out a pre-plating treatment that enables uniform plating in the necessary area of the surface of a substrate. The substrate processing method carries out a cleaning treatment and a catalyst-imparting treatment of a surface of a substrate as pre-plating treatments and then electroless plates a metal film on the catalyst-imparted surface of the substrate. The cleaning treatment is carried out in a wider area of the surface of the substrate than that area to which a catalyst is imparted by the catalyst-imparting treatment.Type: GrantFiled: April 30, 2010Date of Patent: June 14, 2011Assignee: Ebara CorporationInventors: Seiji Katsuoka, Masahiko Sekimoto, Toshio Yokoyama, Teruyuki Watanabe, Takahiro Ogawa, Kenichi Kobayashi, Mitsuru Miyazaki, Yasuyuki Motojima
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Patent number: 7897198Abstract: Electroless plating is performed to deposit conductive materials on work pieces such as partially fabricated integrated circuits. Components of an electroless plating bath are separately applied to a work piece by spin coating to produce a very thin conductive layer (in the range of a few hundred angstroms). The components are typically a reducing agent and a metal source.Type: GrantFiled: September 3, 2002Date of Patent: March 1, 2011Assignee: Novellus Systems, Inc.Inventors: Heung L. Park, Eric G. Webb, Jonathan D. Reid, Timothy Patrick Cleary
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Patent number: 7889298Abstract: A transparent conductive film including an indium oxide, a tin oxide and at least one lanthanoid metal oxide, the film including a portion connected to a conductor, and at least the connection portion having crystallinity.Type: GrantFiled: October 31, 2006Date of Patent: February 15, 2011Assignee: Idemitsu Kosan Co. Ltd.Inventors: Satoshi Umeno, Akira Kaijo, Kazuyoshi Inoue, Nobuo Tanaka, Tokie Tanaka, legal representative
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Patent number: 7691433Abstract: The invention relates to a method for a structured application of molecules on a strip conductor and to a molecular memory matrix. The inventive method makes it possible, for the first time, to economically and simply apply any number of molecular memory elements on the strip conductor in a structured and targeted way, thereby making available, also for the first time, a memory matrix at a molecular level.Type: GrantFiled: November 30, 2005Date of Patent: April 6, 2010Assignee: Forschungszentrum Julich GmbHInventors: Stephan Kronholz, Silvia Karthäuser
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Patent number: 7632535Abstract: The present invention relates to an electrocatalytic coating and an electrode having the coating thereon, wherein the coating is a mixed metal oxide coating, preferably ruthenium, titanium and tin or antimony oxides. The coating uses water as a solvent that provides for a smoother surface than alcohol based solvents. The electrocatalytic coating can be used especially as an anode component of an electrolysis cell and in particular a cell for the electrolysis of aqueous chlor-alkali solutions.Type: GrantFiled: May 7, 2004Date of Patent: December 15, 2009Assignee: De Nora Tech, Inc.Inventors: Richard C. Carlson, Kenneth L. Hardee, Dino F. DiFranco, Michael S. Moats
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Patent number: 7604835Abstract: A method for manufacturing a wiring substrate includes the steps of (a) providing a first surface-active agent in first and second areas and of a substrate, (b) providing a second surface-active agent in the first area of the substrate, (c) providing a catalyst on the second surface-active agent, and (d) depositing a metal layer on the catalyst to thereby form a wiring composed of the metal layer along the first area.Type: GrantFiled: February 3, 2005Date of Patent: October 20, 2009Assignee: Seiko Epson CorporationInventors: Hidemichi Furihata, Satoshi Kimura, Minoru Marumo
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Patent number: 7585540Abstract: A method for manufacturing a wiring substrate includes the steps of: (a) patterning a surface-active agent on a substrate having first and second areas to be remained on the first area; (b) removing residues of the surface-active agent in the second area by wet-etching with an alkali; (c) patterning a catalyst to be remained on one of the second area of the substrate and the surface-active agent; and (d) depositing a metal layer on the catalyst to thereby form a wiring.Type: GrantFiled: March 28, 2005Date of Patent: September 8, 2009Assignee: Seiko Epson CorporationInventors: Hidemichi Furiata, Satoshi Kimura, Minoru Marumo
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Patent number: 7579046Abstract: Smart curing by coupling a catalyst to one or more surface(s) of one or more microelectronic element(s) is generally described. In this regard, according to one example embodiment, a catalyst is coupled to one or more surface(s) of one or more microelectronic element(s) to promote polymerization of an adhesive brought in contact with the catalyst.Type: GrantFiled: December 30, 2005Date of Patent: August 25, 2009Assignee: Intel CorporationInventors: Stephen E. Lehman, Jr., Vijay S. Wakharkar
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Patent number: 7537799Abstract: An ink-jettable composition including a palladium aliphatic amine complex solvated in a liquid vehicle can be used in formation of electronic devices. The ink-jettable composition containing a palladium aliphatic amine complex can be jetted onto a substrate in a predetermined pattern. A second composition can also be applied to the substrate using ink-jet printing or other printing techniques, wherein the second composition is applied onto at least a portion of the predetermined pattern. The second composition can include a reducing agent which is capable of reducing the palladium aliphatic amine complex to palladium metal, typically upon the application of heat. The described ink-jettable palladium complex compositions can be stable over a wide range of conditions and allow for the formation electronic devices on a variety of substrates.Type: GrantFiled: July 11, 2003Date of Patent: May 26, 2009Assignee: Hewlett-Packard Development Company, L.P.Inventor: Tom Etheridge
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Publication number: 20090123642Abstract: The present invention discloses a thermosetting epoxy resin composition containing an epoxy resin having two or more epoxy groups in one molecule, a hardener having two or more functional groups that reacts with the epoxy groups in one molecule, and a photopolymerization initiator, and a method of forming a conductive film, a method of forming a conductive pattern, and a method of manufacturing a multilayered wiring board using the epoxy resin composition.Type: ApplicationFiled: November 6, 2006Publication date: May 14, 2009Applicant: FUJIFILM CorporationInventor: Hiroshi Sato
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Patent number: 7305761Abstract: A method for manufacturing a wiring substrate includes the steps of: (a) forming a ground layer precursor having reactive groups including nitrogen atoms in first and second areas of a substrate; (b) irradiating light energy to remove the reactive groups from the ground layer precursor to thereby form a ground layer charged in cathode; (c) patterning a cationic surface-active agent of anode to be left on the first area of the substrate with the ground layer as a ground; (d) providing a catalyst at the surface-active agent; and (e) forming a wiring along the first area of the substrate by precipitating a metal layer to the catalyst.Type: GrantFiled: March 28, 2005Date of Patent: December 11, 2007Assignee: Seiko Epson CorporationInventors: Satoshi Kimura, Hidemichi Furihata
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Publication number: 20070218192Abstract: A method of manufacturing an interconnect substrate having a linear interconnect by electroless plating without using a plating resist, the method including: (a) forming a plurality of rows of linear catalyst layers on a substrate; and (b) depositing a metal on the linear catalyst layers by electroless plating to form a plurality of rows of linear metal layers, at least one of the rows of linear catalyst layers having a line width of 2 micrometers or less, and a total line width of the linear catalyst layers on the substrate being 10 micrometers or more.Type: ApplicationFiled: March 9, 2007Publication date: September 20, 2007Inventors: Satoshi Kimura, Hidemichi Furihata, Toshihiko Kaneda
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Publication number: 20070218193Abstract: A method of manufacturing an interconnect substrate by electroless plating which causes a metal to be deposited without using a plating resist, the method including: (a) immersing a substrate in a catalyst solution including palladium, hydrogen peroxide, and hydrochloric acid to form a catalyst layer on the substrate; and (b) depositing a metal on the catalyst layer by immersing the substrate in an electroless plating solution to form a metal layer.Type: ApplicationFiled: March 9, 2007Publication date: September 20, 2007Inventors: Satoshi Kimura, Hidemichi Furihata
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Patent number: 7063762Abstract: A method of making a circuitized substrate such as a laminate chip carrier in which a polymer, e.g., Teflon, is used as a dielectric layer and a promotion adhesion layer of a polymer is used to securely adhere a conductive layer thereto which is deposited by plating. The resulting product is thus able to provide extremely narrow conductive circuitry for subsequent connections, e.g., to a semiconductor chip. Electroless plating is the preferred plating method with the dielectric immersed in a solution of conductive monomers, e.g., pyrrole monomer, the solution also possibly containing a seed material such as palladium-tin.Type: GrantFiled: August 20, 2003Date of Patent: June 20, 2006Assignee: Endicott Interconnect Technologies, Inc.Inventors: Elizabeth Foster, Gregory Kevern, Anita Sargent
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Patent number: 7011862Abstract: An object of the invention is to prevent the color on a surface of a plated metal layer from changing. The invention is a wiring substrate obtained by forming a wiring conductor made of a metal having a high melting point on an insulator, and coating a surface of the wiring conductor with an electroless plated metal layer, wherein the electroless plated metal layer contains an element of Group 1B and is free from lead.Type: GrantFiled: November 9, 2004Date of Patent: March 14, 2006Assignee: Kyocera CorporationInventors: Yoshihiro Hosoi, Yasuo Fukuda