Immersion Metal Plating From Solution (e.g., Electroless Plating, Etc.) Patents (Class 427/99.5)
  • Patent number: 8276270
    Abstract: The present invention is directed to a method for manufacturing a printed circuit board in which a plurality of conductive layers forming a wiring pattern are laminated in the state where they are put between insulating layers, and a printed circuit board formed thereby. The printed circuit board manufacturing method for the present invention includes a step of forming a via fill (17) to allow electroless plating liquid to be in contact with the surface of the wiring pattern exposed to a bottom part of a via hole (14) formed at a insulating layer to laminate plating metallic film from the bottom part to a opening part of the via hole (14), to form the via fill (17), and a step of forming a wiring pattern to form electroless plating metallic film (20) serving as the wiring pattern onto a substrate where the via fill (17) is formed.
    Type: Grant
    Filed: April 22, 2008
    Date of Patent: October 2, 2012
    Assignee: C. Uyemura & Co., Ltd.
    Inventors: Teruyuki Hotta, Shushi Morimoto, Takahiro Ishizaki, Hisamitsu Yamamoto
  • Publication number: 20120244276
    Abstract: A method for generating a surface that can be bonded with gold wire. The surface is obtained by first depositing an exchange palladium layer made of the electrolyte on conductors of printed circuit boards, in particular on conductors made of copper or conductive paste. The exchange palladium layer is then reinforced with a palladium layer, deposited from a chemical palladium electrolyte. In order to protect the palladium, an exchange gold layer is then applied. An exchange palladium bath is used, comprising an organic brightener.
    Type: Application
    Filed: November 6, 2010
    Publication date: September 27, 2012
    Applicant: Doduco GmbH
    Inventors: Jochen Heber, Erwin Marka, Walter Macht, Silke Oelschlaeger
  • Patent number: 8268725
    Abstract: A modified coffee-stain method for producing self-organized line structures and other very fine features that involves disposing a solution puddle on a target substrate, and then controlling the peripheral boundary shape of the puddle using a control structure that contacts the puddle's upper surface. The solution is made up of a fine particle solute dispersed in a liquid solvent wets and becomes pinned to both the target substrate and the control structure. The solvent is then caused to evaporate at a predetermined rate such that a portion of the solute forms a self-organized “coffee-stain” line structure on the target substrate surface that is contacted by the peripheral puddle boundary. The target structure is optionally periodically raised to generate parallel lines that are subsequently processed to form, e.g., TFTs for large-area electronic devices.
    Type: Grant
    Filed: October 7, 2010
    Date of Patent: September 18, 2012
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Sanjiv Sambandan, Robert A. Street, Ana Claudia Arias
  • Patent number: 8262917
    Abstract: A fabrication method for a multilayer printed circuit board includes: forming a first circuit-forming pattern and a first insulation layer, into which the first circuit-forming pattern is inserted, on a first carrier; forming inner circuit patterns and inner insulation layers over the first insulation layer, and forming inner vias connecting the inner circuit patterns positioned on different insulation layers; forming a second circuit-forming pattern on a second carrier and inserting the second circuit-forming pattern into a second insulation layer on an outermost side; removing the first carrier and the second carrier; forming circuit-forming grooves by removing the first circuit-forming pattern and the second circuit-forming pattern, and forming via-forming indentations connected with the circuit-forming grooves; and forming outer circuit patterns and outer vias by filling the circuit-forming grooves and the via-forming indentations with a conductive material.
    Type: Grant
    Filed: March 18, 2008
    Date of Patent: September 11, 2012
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventor: Ryoichi Watanabe
  • Patent number: 8257781
    Abstract: A main reservoir holds cool reactant liquid. A reaction vessel for treating a substrate is connected to the main reservoir by a feed conduit. A heater is configured to heat reactant liquid in the feed conduit before the liquid enters the reaction vessel. Preferably, the heater is a microwave heater. A recycle conduit connects the reaction vessel with the main reservoir. Preferably, a recycle cooler cools reactant liquid in the recycle conduit before the liquid returns to the main reservoir. Preferably, an accumulation vessel is integrated in the feed conduit for accumulating, heating, conditioning and monitoring reactant liquid before it enters the reaction vessel. Preferably, a recycle accumulator vessel is integrated in the recycle conduit to accommodate reactant liquid as it empties out of the reaction vessel.
    Type: Grant
    Filed: August 11, 2005
    Date of Patent: September 4, 2012
    Assignee: Novellus Systems, Inc.
    Inventors: Eric G. Webb, Steven T. Mayer, David Mark Dinneen, Edmund B. Minshall, Christopher M. Bartlett, R. Marshall Stowell, Mark T. Winslow, Avishai Kepten, Jingbin Feng, Norman D. Kaplan, Richard K. Lyons, John B. Alexy
  • Patent number: 8252364
    Abstract: The present invention provides a method of forming a metal pattern and a metal pattern obtained by the method. The method includes the steps of (I) forming on a substrate a polymer layer in which a polymer having a functional group that interacts with an electroless plating catalyst or a precursor thereof is chemically bonded directly to the substrate in a pattern form, (II) adding the electroless plating catalyst or precursor thereof to the polymer layer, and (III) forming a metal layer in the pattern form by electroless plating.
    Type: Grant
    Filed: November 29, 2004
    Date of Patent: August 28, 2012
    Assignee: FUJIFILM Corporation
    Inventors: Takeyoshi Kano, Koichi Kawamura
  • Patent number: 8202576
    Abstract: A method of forming a metal film, the method including: (a) forming a primer layer on a substrate by applying a first polymer including a unit having a cyano group in a side chain; (b) forming a polymer layer on the surface of the primer layer by applying a second polymer, the second polymer having a functional group that interacts with an electroless plating catalyst or a precursor thereof and a polymerizable group; (c) applying the electroless plating catalyst or the precursor thereof to the polymer layer; and (d) forming a metal film on the polymer layer by performing electroless plating.
    Type: Grant
    Filed: June 30, 2009
    Date of Patent: June 19, 2012
    Assignee: FUJIFILM Corporation
    Inventors: Masaaki Inoue, Tetsunori Matsumoto
  • Patent number: 8182594
    Abstract: An electroless nickel plating liquid capable of forming an underbarrier metal for metal bumps or solder bumps by electroless nickel plating with a uniform film thickness on silicon wafers composed of multiple IC chips contains a water-soluble nickel salt, a reducing agent, a complexing agent, and a pH buffer, wherein_lead ion is contained at 0.01-1 ppm, cobalt ion is contained at 0.01-1 ppm, and a sulfur compound is contained at 0.01-1 ppm.
    Type: Grant
    Filed: September 26, 2006
    Date of Patent: May 22, 2012
    Assignee: Nippon Mining & Metals Co., Ltd.
    Inventors: Eiji Hino, Masashi Kumagai
  • Patent number: 8178156
    Abstract: A surface treatment process for a circuit board is provided. The circuit board includes a substrate, a first circuit layer disposed on an upper surface of the substrate, and a second circuit layer disposed on a lower surface of the substrate. The first circuit layer is electrically connected to the second circuit layer. In the surface treatment process for the circuit board, a first oxidation protection layer and a second oxidation protection layer are respectively formed on a portion of the first circuit layer and a portion of the second circuit layer by immersion. Afterwards, the first circuit layer exposed by the first oxidation protection layer is subjected to black oxidation to form a black oxide layer. The thickness of the first oxidation protection layer is thinner than or equal to the thickness of the black oxide layer.
    Type: Grant
    Filed: January 12, 2009
    Date of Patent: May 15, 2012
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventor: Chien-Hao Wang
  • Patent number: 8163400
    Abstract: The present invention provides a plated article that has a thin seed layer having a uniform thickness, formed by electroless plating and allowing formation of ultrafine wiring, and that avoids the complicated formation of a bilayer of a barrier layer and a catalytic metal layer prior to forming the seed layer. The present invention also provides a method for manufacturing the plated article. The plated article has an alloy thin film formed on a substrate and containing a catalytically active metal (A) for electroless plating and a metal (B) capable of undergoing displacement plating with a metal ion contained in an electroless plating solution, and a metal thin film formed on the alloy thin film by electroless displacement and reduction plating. The alloy thin film of the catalytically active metal (A) and the metal (B) capable of displacement plating has a composition comprising 5at% to 40at% of the metal (A).
    Type: Grant
    Filed: July 18, 2008
    Date of Patent: April 24, 2012
    Assignee: Nippon Mining & Metals Co., Ltd.
    Inventors: Atsushi Yabe, Junichi Ito, Yoshiyuki Hisumi, Junnosuke Sekiguchi, Toru Imori
  • Patent number: 8163331
    Abstract: A terminal to, most commonly, a ceramic capacitor, most commonly a multilayer ceramic capacitor (MLCC), is formed by electroless plating, also known as electroless deposition or simply as electrodeposition. In the MLCC having a multiple parallel interior plates brought to, and exposed at, at least one, first, surface, an electrically-conductive first-metal layer, preferably Cu, is electrolessly deposited upon this first surface directly in contact with, mechanically connected to, and electrically connected to, the edges of these interior plates. Lateral growth of the electrolessly-deposited first-metal is sufficient to span from exposed plate to exposed plate, electrically connecting the plates. One or more top layers, preferably one of Ni and one of Sn and Pb, are deposited, preferably by plating and more preferably by electrolytic plating, on top of the electrolessly-deposited Cu.
    Type: Grant
    Filed: March 12, 2008
    Date of Patent: April 24, 2012
    Assignee: Presidio Components, Inc.
    Inventor: Hung Van Trinh
  • Patent number: 8151456
    Abstract: The method of producing a substrate comprises the steps of: forming a through-hole in a base member; plating the base member so as to coat an inner face of the through-hole with a plated layer; applying photo resist on the base member; optically exposing and developing the photo resist so as to form a resist pattern, which coats at least a planar area of the through-hole; and etching an electrically conductive layer formed on the surface of the base member. The resist pattern is formed so as to separate an area of exposing the conductive layer a prescribed distance away from an edge of the through-hole, and the prescribed length is longer than a distance of etching a side face of the conductive layer in the etching step.
    Type: Grant
    Filed: July 18, 2008
    Date of Patent: April 10, 2012
    Assignee: Fujitsu Limited
    Inventors: Yasutomo Maehara, Kenji Iida, Tomoyuki Abe, Shin Hirano, Takashi Nakagawa, Hideaki Yoshimura, Seigo Yamawaki, Norikazu Ozaki
  • Patent number: 8147904
    Abstract: A method for manufacturing a metal clad laminate having a film and a metal layer formed of a foundation layer and an upper layer includes the steps of forming the foundation layer on at least a part of a surface of the film by plating to obtain a first laminate; forming the upper layer on the first laminate by plating to obtain a second laminate; and heating the second laminate to obtain the metal clad laminate. Further, the film is a flexible thermoplastic polymer film, the foundation layer is formed of a nickel alloy, the upper layer is formed of copper, at least one of the foundation layer and the upper layer has a compression stress before the step of heating the second laminate, and the metal clad laminate shrinks in a planar direction of the film during the step of heating the second laminate.
    Type: Grant
    Filed: September 9, 2009
    Date of Patent: April 3, 2012
    Assignee: Furukawa Electric Co., Ltd.
    Inventors: Satoru Zama, Kenichi Ohga
  • Patent number: 8133578
    Abstract: A microstructure that comprises an insulating base material having through micropores filled with metal at a high filling ratio and that can be used as an anisotropically conductive member is provided. The microstructure comprises an insulating base material having through micropores with a pore size of from 10 to 500 nm at a density of from 1×106 to 1×1010 pores/mm2, a metal being filled into the through micropores at a filling ratio of at least 80%.
    Type: Grant
    Filed: December 24, 2008
    Date of Patent: March 13, 2012
    Assignee: Fujifilm Corporation
    Inventor: Yusuke Hatanaka
  • Patent number: 8128987
    Abstract: A method for electroless deposition from a deposition solution in a working chamber, where the process can include heating the deposition solution to its boiling point and subsequently reducing the temperature of the deposition solution to a working temperature range that is between approximately 1% and approximately 25% below the boiling point of said solution under a predetermined pressure; and the process also can include heating the deposition solution while filling an enclosed area of the chamber such that the deposition solution reaches its boiling point immediately after the enclosed area is filled.
    Type: Grant
    Filed: May 26, 2005
    Date of Patent: March 6, 2012
    Assignee: Lam Research Corp.
    Inventors: Igor C. Ivanov, Jonathan Weiguo Zhang, Artur Kolics
  • Patent number: 8124174
    Abstract: Part or whole of an electroless gold plating film of a plated film laminate including an electroless nickel plating film, an electroless palladium plating film and an electroless gold plating film is formed by an electroless gold plating using an electroless gold plating bath including a water-soluble gold compound, a complexing agent, formaldehyde and/or a formaldehyde-bisulfite adduct, and an amine compound represented by the following general formula R1—NH—C2H4—NH—R2 or R3—(CH2—NH—C2H4—NH—CH2)n—R4. The method of the invention does not need two types of baths, a flash gold plating bath and a thick gold plating bath for thickening. Gold plating films of different thicknesses suited for solder bonding or wire bonding can be formed using only one type of gold plating bath.
    Type: Grant
    Filed: April 14, 2008
    Date of Patent: February 28, 2012
    Assignee: C. Uyemura & Co., Ltd.
    Inventors: Seigo Kurosaka, Yukinori Oda, Akira Okada, Ayumi Okubo, Masayuki Kiso
  • Patent number: 8094456
    Abstract: To provide a polishing pad which is insusceptible to clogging of groove with abrasive particles and grinding dusts during polishing, and leads to little decrease in polishing rate even after long-term continuous use. A polishing pad of the present invention has a polishing layer formed of polyurethane resin foam having fine-cells, and asperity structure formed in a polishing surface of the polishing layer, and is featured in that the polyurethane resin foam is a reaction cured product between isocyanate-terminated prepolymer containing high-molecular-weight polyol component and isocyanate component, and a chain extender, and contains a silicon-based surfactant having combustion residue of not less than 8 wt %.
    Type: Grant
    Filed: January 9, 2007
    Date of Patent: January 10, 2012
    Assignee: Toyo Tire & Rubber Co., Ltd.
    Inventors: Takeshi Fukuda, Junji Hirose, Masato Doura
  • Patent number: 8061032
    Abstract: A process for fabricating a metallic component is disclosed. The process includes performing multiple electroforming steps on an object to form metallic layers. The process includes performing between the electroforming steps masking and patterning steps using a non-conductive material. The resulting metallic component has either a single layer or multiple layers of cooling or heat transfer channels, which may be at right angles in adjacent layers. The non-conductive material can be removed during the process by a solvent or by melting. The object on which the metallic component is formed may be a flat or shaped mandrel from which the metallic component can be removed. The metallic component is particularly useful in forming optical components for use in extreme ultraviolet (EUV) systems and in cooling and heat transfer systems.
    Type: Grant
    Filed: November 23, 2004
    Date of Patent: November 22, 2011
    Assignee: Media Lario S.R.L.
    Inventors: Robert David Banham, Arnoldo Valenzuela
  • Patent number: 8025953
    Abstract: The present invention provides a method for preparing a conductive pattern, comprising a pattern forming step of forming a conductive pattern on a substrate; and a blackening processing step of blackening the surface of the conductive pattern by immersing the conductive pattern in an aqueous solution containing reducing metal ions to oxidize the surface of the conductive pattern, and a conductive pattern prepared therefrom.
    Type: Grant
    Filed: December 15, 2006
    Date of Patent: September 27, 2011
    Assignee: LG Chem, Ltd.
    Inventors: Dong Wook Lee, In Seok Hwang, Seung Wook Kim, Hyun Seok Choi
  • Patent number: 7989029
    Abstract: A method for reducing porosity of metal layers on a substrate may comprise depositing a precursor onto at least a portion of the substrate, and adding metal layers over the precursor comprising at least one cycle, wherein each cycle comprises: depositing a metal layer over the precursor, and exposing the metal layer to a breath-out solution.
    Type: Grant
    Filed: June 20, 2008
    Date of Patent: August 2, 2011
    Assignee: SRI International
    Inventors: Jaspreet Singh Dhau, Sunity K. Sharma
  • Publication number: 20110168430
    Abstract: [Problems] To provide a method of forming metal wiring capable of forming metal wiring of ultrathin film and an electronic part including the metal wiring of ultrathin film. [Solving Means] A compound having an ethoxysilane group or a methoxysilane group and a thiol group is used. A number of metal particles each having a surface previously covered with the compound by chemical bond of the thiol group of the compound are prepared. The metal particles are fixed to a base surface by chemically bonding a silanol group produced by hydrolyzing the ethoxysilane group or the methoxysilane group to the base surface, the metal wiring being to be formed on the base surface. The metal wiring may be formed only from the metal particles, or electroless plating is performed by using the metal particles as a catalyst to thickly provide the same type or a different type of metal.
    Type: Application
    Filed: September 11, 2008
    Publication date: July 14, 2011
    Inventor: Takuya Hata
  • Publication number: 20110139494
    Abstract: A method for manufacturing an embedded wiring board is provided. An activating insulation layer is formed, in which the activating insulation layer includes a plurality of catalyst particles, and covers a first wiring layer. An intaglio pattern and at least one blind via partially exposing the first wiring layer are formed on the activating insulation layer, in which some of the catalyst particles are activated and exposed in the intaglio pattern and the blind via. The activating insulation layer is dipped in a first chemical plating solution, and a solid conductive pillar is formed in the blind via through electroless plating. The activating insulation layer is dipped in a second chemical plating solution after the solid conductive pillar is formed, and a second wiring layer is formed in the intaglio pattern through the electroless plating. Components of the first chemical plating solution and the second chemical plating solution are different.
    Type: Application
    Filed: January 29, 2010
    Publication date: June 16, 2011
    Applicant: UNIMICRON TECHNOLOGY CORP.
    Inventors: Chen-Po Yu, Chai-Liang Hsu
  • Patent number: 7959977
    Abstract: A substrate processing method and apparatus can securely carry out a pre-plating treatment that enables uniform plating in the necessary area of the surface of a substrate. The substrate processing method carries out a cleaning treatment and a catalyst-imparting treatment of a surface of a substrate as pre-plating treatments and then electroless plates a metal film on the catalyst-imparted surface of the substrate. The cleaning treatment is carried out in a wider area of the surface of the substrate than that area to which a catalyst is imparted by the catalyst-imparting treatment.
    Type: Grant
    Filed: April 30, 2010
    Date of Patent: June 14, 2011
    Assignee: Ebara Corporation
    Inventors: Seiji Katsuoka, Masahiko Sekimoto, Toshio Yokoyama, Teruyuki Watanabe, Takahiro Ogawa, Kenichi Kobayashi, Mitsuru Miyazaki, Yasuyuki Motojima
  • Patent number: 7897198
    Abstract: Electroless plating is performed to deposit conductive materials on work pieces such as partially fabricated integrated circuits. Components of an electroless plating bath are separately applied to a work piece by spin coating to produce a very thin conductive layer (in the range of a few hundred angstroms). The components are typically a reducing agent and a metal source.
    Type: Grant
    Filed: September 3, 2002
    Date of Patent: March 1, 2011
    Assignee: Novellus Systems, Inc.
    Inventors: Heung L. Park, Eric G. Webb, Jonathan D. Reid, Timothy Patrick Cleary
  • Patent number: 7892651
    Abstract: A resin composite metal foil comprising a metal foil and a layer of a block copolymer polyimide resin formed on one surface of the metal foil, a metal-foil-clad laminate using the above resin composite metal foil, a printed wiring board using the above metal-foil-clad laminate, and a process for the production of a printed wiring board comprising removing an external layer metal foil of a metal-foil-clad laminate and forming a conductor layer on an external layer insulating layer by plating, wherein the metal-foil-clad laminate comprises a layer of a block copolymer polyimide resin which layer is in contact with the external layer metal foil.
    Type: Grant
    Filed: September 13, 2005
    Date of Patent: February 22, 2011
    Assignees: Mitsubishi Gas Chemical Company, Inc., PI R&D Co., Ltd.
    Inventors: Takabumi Omori, Mitsuru Nozaki, Eiji Nagata, Masashi Yano
  • Publication number: 20110039019
    Abstract: The invention is directed to a solution and process for improving the solderability of a metal surface. In one embodiment, the invention is a silver deposit solution comprising an acid, a source of silver ions, and an additive selected from among pyrroles, triazoles, and tetrazoles, as well as derivatives and mixtures of those components. In another embodiment, the silver deposit solution also includes a 6-membered heterocyclic ring compound, wherein three members of the 6-membered heterocyclic ring are nitrogen atoms. Still another embodiment is a process for improving the solderability of a metal surface which involves applying a silver deposit solution as previously described to a metal surface.
    Type: Application
    Filed: August 3, 2010
    Publication date: February 17, 2011
    Inventor: Roger F. Bernards
  • Patent number: 7875110
    Abstract: An electroless plating composition comprising succinic acid, potassium carbonate, a source of cobalt metal ions, a reducing agent, and water is provided. An optional buffering agent may also be included in the composition. The composition may be used to deposit cobalt metal in or on semiconductor substrate surfaces including vias, trenches, and interconnects.
    Type: Grant
    Filed: February 16, 2010
    Date of Patent: January 25, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Rita J. Klein, Adam J. Regner, III
  • Publication number: 20110014361
    Abstract: One embodiment of the present invention is a method of electroless deposition of cap layers for fabricating an integrated circuit. The method includes controlling the composition of an electroless deposition bath so as to substantially maintain the electroless deposition properties of the bath. Other embodiments of the present invention include electroless deposition solutions. Still another embodiment of the present invention is a composition used to recondition an electroless deposition bath.
    Type: Application
    Filed: March 24, 2010
    Publication date: January 20, 2011
    Inventor: Artur Kolics
  • Publication number: 20100291488
    Abstract: A method for manufacturing a cone board including: preparing a core insulation layer including one or more resins selected from the group consisting of epoxy resins and bismaleimide triazine resins; and forming a first nickel layer on at least one surface of the core insulation layer by electroless plating
    Type: Application
    Filed: July 27, 2010
    Publication date: November 18, 2010
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Soon-Oh Jung, Cheol-Ho Choi, Chang-Hyun Nam, Hong-Won Kim, Seung-Chul Kim
  • Publication number: 20100282500
    Abstract: Provided is an ultra-thin copper foil to which a carrier foil is attached, including: a carrier foil, a peeling layer, and an ultra-thin copper foil, wherein the peeling layer includes a first metal A having peelability, a second metal B and a third metal C facilitating coating of the first metal, wherein the amount (a) of the first metal A is in a range of about 30 to about 89% by total weight of the peeling layer, the amount (b) of the second metal B is in a range of about 10 to about 60% by total weight of the peeling layer, and the amount (c) of the third metal C is in a range of about 1 to about 20% by total weight of the peeling layer.
    Type: Application
    Filed: December 23, 2008
    Publication date: November 11, 2010
    Applicant: ILJIN COPPER FOIL CO., LTD.
    Inventors: Jong Ho Ryu, Chang Yol Yang, Joung Ah Kang
  • Publication number: 20100273014
    Abstract: A method for producing a metal-clad substrate, the method including: (a) forming, on a substrate, a resin layer containing a plating catalyst or a precursor thereof, which resin layer satisfies the following requirement 1; and (b) performing plating on the resin layer, Requirement 1: the resin layer contains the plating catalyst or a precursor thereof within a portion extending from a surface to a depth of 25 nm of the resin layer, in an amount in the range of 3×10?20 mol/nm3 to 30×10?20 mol/nm3 in terms of a content of a metal element thereof.
    Type: Application
    Filed: December 24, 2008
    Publication date: October 28, 2010
    Applicant: FUJIFILM CORPORATION
    Inventor: Shiki Ueki
  • Publication number: 20100233360
    Abstract: A method of transferring an electronic material and a method of manufacturing an electronic device using the method of transferring the electronic material. The method of transferring the electronic material includes dipping a template, on which an electronic material layer is formed, into a liquid medium, separating the electronic material layer from the template, and floating the electronic material layer on a surface of the liquid medium; raising up the electronic material layer floated on the surface of the liquid medium by using a target substrate and transferring the electronic material layer on the target substrate; and fixing the electronic material layer to the target substrate.
    Type: Application
    Filed: February 4, 2010
    Publication date: September 16, 2010
    Applicant: Korea University Research and Business Foundation
    Inventors: Cheol Jin LEE, Sun Kug KIM
  • Publication number: 20100190029
    Abstract: Provided are a metal layer laminate that includes a roughened metal surface layer having a surface profile capable of strongly adhering to resin materials even when the surface roughness is small, and a simple method for producing a metal layer laminate having good adhesion to resin materials such as a resin substrate for a metal layer and an insulating resin film formed on the surface of a metal wiring portion. The metal layer laminate includes a metal layer, a resin thin film, and a roughened metal surface layer, wherein the resin thin film and the roughened metal surface layer are formed on the surface of the metal layer, a fractal-shaped interface structure appears between the resin thin film and the roughened metal surface layer, when the metal layer laminate is cut in a normal direction, and the interface structure has a fractal dimension of 1.05 to 1.
    Type: Application
    Filed: June 9, 2008
    Publication date: July 29, 2010
    Applicant: FUJIFILM CORPORATION
    Inventor: Shiki Ueki
  • Publication number: 20100155108
    Abstract: The present invention relates to an electroless nickel plating solution composition, a flexible printed circuit board and a manufacturing method thereof, and more particularly, to an electroless nickel plating solution composition, a flexible printed circuit board and a manufacturing method thereof capable of simultaneously satisfying plating characteristics respectively required for a pad unit and external connection units of the flexible printed circuit board by forming a nickel plating layer having a vertical growth structure with the electroless nickel plating solution composition including a water-soluble nickel compound, a reducing agent, a complexing agent and a vertical growth inducer.
    Type: Application
    Filed: May 28, 2009
    Publication date: June 24, 2010
    Applicants: SAMSUNG ELECTRO-MECHANICS CO., LTD., YMT CO., LTD.
    Inventors: Chul Min Lee, Sung Wook Chun, Dek Gin Yang, Kyung Jin Heo, Young Ho Lee, Dong-Gi An
  • Publication number: 20100098905
    Abstract: A method of manufacturing a non-shrinking ceramic substrate according to an aspect of the invention may include: preparing a ceramic laminate having a via electrode therein; firing the ceramic laminate so that a void is formed at the interface between the via electrode and the ceramic laminate; and performing plating to fill the void with a conductive material.
    Type: Application
    Filed: May 29, 2009
    Publication date: April 22, 2010
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jin Waun KIM, Seung Gyo Jeong
  • Publication number: 20100044096
    Abstract: A mechanism is disclosed for providing horizontally split vias are provided in printed wiring boards (PWBs) and other substrates. In one embodiment, the substrate includes a plurality of insulator layers and internal conductive traces. First and second through-holes extend completely through the substrate and respectively pass through first/second ones and third/fourth ones of the internal conductive traces, which are at different depths within the substrate. Photolithographic techniques are used to generate plated-through-hole (PTH) plugs of controlled, variable depth in the through-holes before first/second conductive vias are plated onto the first through-hole and before third/fourth conductive vias are plated onto the second through-hole. The depth of these PTH plugs is controlled (e.g.
    Type: Application
    Filed: August 19, 2008
    Publication date: February 25, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Joseph Kuczynski, Kevin Albert Splittstoesser, Timothy Jerome Tofil, Paul Alan Vermilyea
  • Patent number: 7655282
    Abstract: A method of forming a patterned thin film comprises the step of forming a frame having an undercut near the bottom thereof on an electrode film, and the plating step of forming the patterned thin film by plating through the use of the frame. The patterned thin film includes a plurality of linear portions disposed side by side. Each of the linear portions has a portion close to the electrode film. This portion has a width greater than the width of the remaining portion of each of the linear portions.
    Type: Grant
    Filed: January 30, 2007
    Date of Patent: February 2, 2010
    Assignee: TDK Corporation
    Inventor: Akifumi Kamijima
  • Patent number: 7651723
    Abstract: A process chamber is provided which includes a gate configured to align barriers with an opening of the gate and an opening of the process chamber such that the two openings are either sealed or provide an air passage to the chamber. A method is provided and includes sealing an opening of a chamber with a gate latch and exposing a topography to a first set of process steps, opening the gate latch such that an air passage is provided to the process chamber, and exposing the topography to a second set of process steps without allowing liquids within the chamber to flow through the air passage. A substrate holder comprising a clamping jaw with a lever and a support member coupled to the lever is also contemplated herein. A process chamber with a reservoir arranged above a substrate holder is also provided herein.
    Type: Grant
    Filed: January 10, 2005
    Date of Patent: January 26, 2010
    Assignee: Lam Research Corporation
    Inventors: Igor C. Ivanov, Weiguo Zhang
  • Publication number: 20100003399
    Abstract: Disclosed is an electroless plating solution exhibiting a good plating metal filling performance even for larger trenches or vias of several to one hundred and tens of ?m, in a manner free from voids or seams, and allowing maintenance of stabilized performance for prolonged time. The electroless plating solution contains at least a water-soluble metal salt, a reducing agent for reducing metal ions derived from the water-soluble metal salt, and a chelating agent. In addition, the electroless plating solution contains a sulfur-based organic compound as a leveler having at least one aliphatic cyclic group or aromatic cyclic group to which may be linked at least one optional substituent. The aliphatic cyclic group or the aromatic cyclic group contains optional numbers of carbon atoms, oxygen atoms, phosphorus atoms, sulfur atoms and nitrogen atoms.
    Type: Application
    Filed: June 25, 2009
    Publication date: January 7, 2010
    Applicant: C. UYEMURA & CO., LTD.
    Inventors: TERUYUKI HOTTA, TAKAHIRO ISHIZAKI, TOMOHIRO KAWASE, MASAHARU TAKEUCHI
  • Patent number: 7604835
    Abstract: A method for manufacturing a wiring substrate includes the steps of (a) providing a first surface-active agent in first and second areas and of a substrate, (b) providing a second surface-active agent in the first area of the substrate, (c) providing a catalyst on the second surface-active agent, and (d) depositing a metal layer on the catalyst to thereby form a wiring composed of the metal layer along the first area.
    Type: Grant
    Filed: February 3, 2005
    Date of Patent: October 20, 2009
    Assignee: Seiko Epson Corporation
    Inventors: Hidemichi Furihata, Satoshi Kimura, Minoru Marumo
  • Patent number: 7585541
    Abstract: A printed circuit board is by formed by laminating an interlaminar insulating layer on a conductor circuit of a substrate, in which the conductor circuit is comprised of an electroless plated film and an electrolytic plated film and a roughened layer is formed on at least a part of the surface of the conductor circuit.
    Type: Grant
    Filed: September 19, 2006
    Date of Patent: September 8, 2009
    Assignee: IBIDEN Co., Ltd.
    Inventors: Yoshinori Wakihara, Kazuhito Yamada
  • Publication number: 20090145652
    Abstract: The present invention has for its object to provide a process for manufacturing multilayer printed circuit boards which is capable of simultaneous via hole filling and formation of conductor circuit and via holes of good crystallinity and uniform deposition can be constructed on a substrate and high-density wiring and highly reliable conductor connections can be realized without annealing.
    Type: Application
    Filed: September 26, 2008
    Publication date: June 11, 2009
    Applicant: IBIDEN CO., LTD.
    Inventors: Honchin En, Tohru Nakai, Takeo Oki, Naohiro Hirose, Kouta Noda
  • Patent number: 7497932
    Abstract: The present invention provides an electro-chemical deposition system that is designed with a flexible architecture that is expandable to accommodate future designs and gap fill requirements and provides satisfactory throughput to meet the demands of other processing systems. The electro-chemical deposition system generally comprises a mainframe having a mainframe wafer transfer robot, a loading station disposed in connection with the mainframe, one or more processing cells disposed in connection with the mainframe, and an electrolyte supply fluidly connected to the one or more electrical processing cells. Preferably, the electro-chemical deposition system includes a spin-rinse-dry (SRD) station disposed between the loading station and the mainframe, a rapid thermal anneal chamber attached to the loading station, and a system controller for controlling the electro-chemical deposition process and the components of the electro-chemical deposition system.
    Type: Grant
    Filed: June 27, 2006
    Date of Patent: March 3, 2009
    Assignee: Applied Materials, Inc.
    Inventors: Yezdi Dordi, Donald J. Olgado, Ratson Morad, Peter Hey, Mark Denome, Michael Sugarman, Anna Marie Lloyd, legal representative, Joseph Stevens, Dan Marohl, Ho Seon Shin, Eugene Ravinovich, Robin Cheung, Ashok K. Sinha, Avi Tepman, Dan Carl, George Birkmaier, Mark Lloyd
  • Publication number: 20090020315
    Abstract: A method for making multilayer printed circuits includes a) coating a non-metallized substrate with a solution which creates a light sensitive surface on the substrate, b) imaging the coated substrate with a circuit design, c) developing the imaged substrate, d) directly plating the developed image onto the coated substrate, e) coating the plated substrate with a liquid photoimageable cover coat, f) imaging the coated plated substrate with a predesigned circuitry, g) developing the liquid photoimageable cover coat, and repeating steps a) through d). Steps e) through g) are then repeated followed by steps a) through d) until a desired number of layers is achieved for the multilayer circuit. The method may be automated by having a conveyer like system which automatically unrolls and directs a roll of non-metallized substrate through various coating, imaging, developing, and plating stations.
    Type: Application
    Filed: June 18, 2008
    Publication date: January 22, 2009
    Inventor: Steven Lee Dutton
  • Publication number: 20090014411
    Abstract: A fabrication method for a multilayer printed circuit board includes: forming a first circuit-forming pattern and a first insulation layer, into which the first circuit-forming pattern is inserted, on a first carrier; forming inner circuit patterns and inner insulation layers over the first insulation layer, and forming inner vias connecting the inner circuit patterns positioned on different insulation layers; forming a second circuit-forming pattern on a second carrier and inserting the second circuit-forming pattern into a second insulation layer on an outermost side; removing the first carrier and the second carrier; forming circuit-forming grooves by removing the first circuit-forming pattern and the second circuit-forming pattern, and forming via-forming indentations connected with the circuit-forming grooves; and forming outer circuit patterns and outer vias by filling the circuit-forming grooves and the via-forming indentations with a conductive material.
    Type: Application
    Filed: March 18, 2008
    Publication date: January 15, 2009
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventor: Ryoichi Watanabe
  • Publication number: 20080254205
    Abstract: A method and composition for electrolessly depositing a layer of a metal alloy onto a surface of a metal substrate in manufacture of microelectronic devices. The composition comprises a source of metal deposition ions, a borane-based reducing agent, and a two-component stabilizer, wherein the first stabilizer component is a source of hypophosphite and the second stabilizer component is a molybdenum (VI) compound.
    Type: Application
    Filed: April 13, 2007
    Publication date: October 16, 2008
    Applicant: ENTHONE INC.
    Inventors: Nicolai Petrov, Charles Valverde, Qingyun Chen, Richard Hurtubise
  • Publication number: 20080251495
    Abstract: A method of forming printed circuit boards and packaging substrates for integrated circuits based on filling-vias plating and a semi-additive process, comprising the following steps: (1) providing a dielectric layer on a substrate; (2) providing blind vias on said dielectric layer; (3) providing a first seed layer after providing blind vias; (4) providing solid conductive vias by a filling-vias plating process after providing a first seed layer, and also providing a copper layer covering the first seed layer during the filling-vias plating process; (5) removing said first seed layer as well as the copper layer formed thereon, and retaining solid copper pillars in the conductive vias; (6) providing a second seed layer which is used to form wires by a semi-additive process; (7) providing a photo-sensitive thin film, and providing a plating resistant layer by image-transfer to expose a wire pattern; (8) thickening wires; (9) removing the photo-sensitive thin film; (10) removing the exposed second seed layer and
    Type: Application
    Filed: March 25, 2008
    Publication date: October 16, 2008
    Applicant: Shanghai Meadville Science & Technology Co., Ltd.
    Inventors: FanXiong Cheng, Peifeng Chen, Haitao Fu, Yonghong Luo
  • Patent number: 7416763
    Abstract: A process in which a base metal film is formed on the surface of a plastic film using a dry plating process, and a liquid containing an organic monomer is then brought in contact with the base metal film, thereby selectively forming a conductive organic polymer coating within any pinhole defects, and effectively filling the defects. A metal film is then formed on top of the base metal film using an electroplating process, thus forming a metal wet plating layer.
    Type: Grant
    Filed: June 16, 2004
    Date of Patent: August 26, 2008
    Assignee: Cookson Electronics Co.
    Inventors: Yuichi Kanda, Takashi Abe, Atsushi Tanaka, Keisuke Nishu
  • Publication number: 20080138629
    Abstract: There is provided a technology that can be applied as a substrate material to ordinary resin substrate materials and allows the adhesive strength between this substrate material and a plating metal layer to be increased; more specifically, there is provided an ordinary resin substrate material with an increased adhesive strength between the substrate material and a plating metal layer. The present invention relates to a resin substrate material such as an epoxy resin whose surface is swellable in a solution containing imidazolesilane and a palladium or other noble metal compound having a catalytic action in electroless plating and which has been surface-treated with the solution, and to an electronic component substrate material manufactured by performing electroless plating on this resin substrate material.
    Type: Application
    Filed: February 27, 2006
    Publication date: June 12, 2008
    Inventors: Toshifumi Kawamura, Toru Imori
  • Publication number: 20080138506
    Abstract: An electroless gold plating bath includes a water-soluble gold compound, a complexing agent, a formaldehyde metabisulfite adduct, and an amine compound represented by R1—NH—C2H4—NH—R2 or (CH2—NH—C2H4—NH—CH2)n—R4 (wherein R1 to R4 represent —OH, —CH3, —CH2OH, —C2H4OH, —CH2N(CH3)2, —CH2NH(CH2OH), —CH2NH(C2H4OH), —C2H4NH(CH2OH), —C2H4NH(C2H4OH), —CH2N(CH2OH)2, —CH2N(C2H4OH)2, —C2H4N(CH2OH)2 or —C2H4N(C2H4OH)2, and n is an integer of 1 to 4). A gold plated coating of a good appearance can be formed without causing a failure in appearance owing to the progress of intergranular corrosion in a nickel surface.
    Type: Application
    Filed: December 5, 2007
    Publication date: June 12, 2008
    Inventors: Masayuki Kiso, Yukinori Oda, Seigo Kurosaka, Tohru Kamitamari, Yoshikazu Saijo, Katsuhisa Tanabe