Including Control Feature Responsive To A Test Or Measurement Patents (Class 430/30)
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Patent number: 8042067Abstract: A pattern forming method of forming a desired pattern on a semiconductor substrate is disclosed, which comprises extracting a first pattern of a layer, extracting a second pattern of one or more layers overlapped with the layer, the second pattern being arranged close to or overlapped with the first pattern, calculating a distance between the first and second patterns on a semiconductor substrate in consideration of a predetermined process variation, determining whether or not the distance between the first and second patterns satisfy an allowable margin given for the distance between the first and second patterns, and correcting, if the distance does not satisfy the allowable margin, at least one of the first and second patterns to satisfy the allowable margin.Type: GrantFiled: July 1, 2008Date of Patent: October 18, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Ayako Nakano, Toshiya Kotani
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Patent number: 8039176Abstract: In the field of semiconductor production using shaped charged particle beam lithography, a method and system for fracturing or mask data preparation or proximity effect correction is disclosed, wherein a series of curvilinear character projection shots are determined for a charged particle beam writer system, such that the set of shots can form a continuous track, possibly of varying width, on a surface. A method for forming a continuous track on a surface using a series of curvilinear character projection shots is also disclosed. Methods for manufacturing a reticle and for manufacturing a substrate such as a silicon wafer by forming a continuous track on a surface using a series of curvilinear character projection shots is also disclosed.Type: GrantFiled: November 14, 2009Date of Patent: October 18, 2011Assignee: D2S, Inc.Inventors: Akira Fujimura, Michael Tucker
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Patent number: 8039181Abstract: By taking into consideration the combination of the substrate holders in various lithography tools used during the imaging to two subsequent device layers, enhanced alignment accuracy may be accomplished. Furthermore, restrictive tool dedications for critical lithography processes may be significantly relaxed by providing specific overlay correction data for each possible process flow, wherein, in some illustrative embodiments, a restriction of the number of possible process flows may be accomplished by implementing a rule for selecting a predefined substrate holder when starting the processing of an associated group of substrates.Type: GrantFiled: June 2, 2009Date of Patent: October 18, 2011Assignee: Advanced Micro Devices, Inc.Inventors: Rolf Seltmann, Jens Busch, Uwe Schulze
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Patent number: 8039177Abstract: A method of correcting a flare comprising: calculating a distribution of a flare value corresponding to pattern data on the pattern data as a flare map; calculating an occupancy of a pattern having a predetermined flare value on the pattern data as a flare value occupancy for each flare value, by using the flare map; determining a reference flare value to be a reference of the flare value based on the distribution of the flare value occupancy; and performing a pattern correction corresponding to the flare value with a pattern correction amount at the reference flare value as a reference.Type: GrantFiled: June 17, 2010Date of Patent: October 18, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Taiga Uno, Yukiyasu Arisawa, Hajime Aoyama
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Patent number: 8039179Abstract: Provided is a photolithography apparatus including a photomask. The photomask includes a pattern having a plurality, of features, in an example, dummy line features. The pattern includes a first region being in the form of a localized on-grid array and a second region where at least one of the features has an increased width. The apparatus may include a second photomask which may define an active region. The feature with an increased width may be adjacent, and outside, the defined active region.Type: GrantFiled: December 29, 2010Date of Patent: October 18, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Feng Shieh, Shinn-Sheng Yu, Anthony Yen, Shao-Ming Yu, Chang-Yun Chang, Jeff J. Xu, Clement Hsingjen Wann
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Patent number: 8039180Abstract: A method of forming a mask having optical proximity correction features, which includes the steps of obtaining a target pattern of features to be imaged, expanding—the width of the features to be imaged, modifying the mask to include assist features which are placed adjacent the edges of the features to be imaged, where the assist features have a length corresponding to the expanded width of the features to be imaged, and returning the features to be imaged from the expanded width to a width corresponding to the target pattern.Type: GrantFiled: February 22, 2011Date of Patent: October 18, 2011Assignee: ASML Masktools B.V.Inventors: Thomas Laidig, Kurt E. Wampler, Douglas Van Den Broeke, Jang Fung Chen
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Publication number: 20110248388Abstract: A wafer includes an active region and a kerf region surrounding at least a portion of the active region. The wafer also includes a target region having a rectangular shape with a width and a length greater than the width, the target region including one or more target patterns, at least one of the target patterns being formed by two sub-patterns disposed at opposing corners of a target rectangle disposable within the target region.Type: ApplicationFiled: April 9, 2010Publication date: October 13, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Christopher P. Ausschnitt, Allen H. Gabor, Nelson M. Felix
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Patent number: 8035824Abstract: A method is described for measuring a dimension on a substrate, wherein a target pattern is provided with a nominal characteristic dimension that repeats at a primary pitch of period P, and has a pre-determined variation orthogonal to the primary direction. The target pattern formed on the substrate is then illuminated so that at least one non-zero diffracted order is detected. The response of the non-zero diffracted order to variation in the printed characteristic dimension relative to nominal is used to determine the dimension of interest, such as critical dimension or overlay, on the substrate. An apparatus for performing the method of the present invention includes an illumination source, a detector for detecting a non-zero diffracted order, and means for positioning the source relative to the target so that one or more non-zero diffracted orders from the target are detected at the detector.Type: GrantFiled: October 28, 2009Date of Patent: October 11, 2011Assignee: International Business Machines CorporationInventor: Christopher Ausschnitt
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Publication number: 20110244380Abstract: According to one embodiment, an image forming apparatus includes: an image forming unit configured to form a toner image on an image bearing member according to printing information; a transfer unit configured to transfer an unfixed toner image formed by the image forming unit onto a printing sheet; a fixing unit configured to heat the unfixed toner image carried on the printing sheet and fix the unfixed toner image on the printing sheet; a temperature measuring unit configured to measure the temperature of the fixing unit; and a quick-print processing unit configured to cause, when printing is started, even if the temperature of the fixing unit measured by the temperature measuring unit does not reach ready temperature, the image forming unit to perform an image forming operation on the basis of low process speed for enabling the fixing in the fixing unit, which is lower than normal process speed corresponding to the ready temperature.Type: ApplicationFiled: April 4, 2011Publication date: October 6, 2011Applicants: Kabushiki Kaisha Toshiba, Toshiba Tec Kabushiki KaishaInventor: Eiji Shinohara
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Patent number: 8029953Abstract: A device manufacturing method includes a transfer of a pattern from a patterning device onto a substrate. The device manufacturing method further includes transferring a pattern of a main mark to a base layer for forming an alignment mark; depositing a pattern receiving layer on the base layer; in a first lithographic process, aligning, by using the main mark, a first mask that includes a first pattern and a local mark pattern, and transferring the first pattern and the local mark pattern to the pattern receiving layer; aligning, by using the local mark pattern, a second mask including a second pattern relative to the pattern receiving layer; and in a second lithographic process, transferring the second pattern to the pattern receiving layer; the first and second patterns being configured to form an assembled pattern.Type: GrantFiled: February 17, 2011Date of Patent: October 4, 2011Assignee: ASML Netherlands B.V.Inventors: Maurits Van Der Schaar, Richard Johannes Franciscus Van Haren
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Patent number: 8029947Abstract: Methods, systems, and tool sets involving reticles and photolithography processing. Several embodiments of the invention are directed toward obtaining qualitative data from within the pattern area of a reticle that is indicative of the physical characteristics of the pattern area. Additional embodiments of the invention are directed toward obtaining qualitative data indicative of the physical characteristics of the reticle remotely from a photolithography tool. These two aspects of the invention can be combined in further embodiments in which qualitative data is obtained from within the pattern area of a reticle in a tool that is located remotely from the photolithography tool. As a result, several embodiments of methods and systems in accordance with the invention provide data taken from within the pattern area to more accurately reflect the contour of the pattern area of the reticle without using the photolithography tool to obtain such measurements.Type: GrantFiled: September 1, 2005Date of Patent: October 4, 2011Assignee: Micron Technology, Inc.Inventor: Craig A. Hickman
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Patent number: 8029954Abstract: A method comprises determining an exposure condition by executing a process including computing an image formed on an image plane under the current exposure condition while changing the exposure condition, and evaluating a line width of the computed image, and exposing the substrate under the determined exposure condition, wherein the determining includes, computing a simplified evaluation value of the computed image, changing the exposure condition and executing the process in the changed exposure condition, after evaluating the computed image if the simplified evaluation value satisfies an allowable value, and changing the exposure condition and executing the process in the changed exposure condition without evaluating the computed image if the simplified evaluation value does not satisfy the allowable value.Type: GrantFiled: July 8, 2009Date of Patent: October 4, 2011Assignee: Canon Kabushiki KaishaInventors: Koji Mikami, Kouichirou Tsujita, Hiroyuki Ishii
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Patent number: 8029952Abstract: There is provided a method for fabricating a magnetic recording medium that provides high throughput, low manufacturing cost, and no degradation in accuracy in pattern size in fine pattern formation. A resist layer is formed on a substrate or cutting work layer. The surface of the substrate is divided into two or more areas using the center of rotation of the substrate as a reference point. An optical, contactless pattern transfer method is used to transfer a figure pattern contained in the divided area through a mask to the resist layer so as to form a latent image of the figure pattern. The pattern transfer is similarly carried out for the divided area. After the pattern transfer processes for all the divided areas are completed, the entire resist layer is developed to form a resist pattern. The resist pattern is used as a mask to cut the substrate or cutting work layer. As a result, there is provided the substrate or cut work layer onto which a fine pattern has been transferred.Type: GrantFiled: November 15, 2007Date of Patent: October 4, 2011Assignee: Hitachi, Ltd.Inventors: Yuko Tsuchiya, Chiseki Haginoya
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METHOD FOR EXAMINING A WAFER WITH REGARD TO A CONTAMINATION LIMIT AND EUV PROJECTION EXPOSURE SYSTEM
Publication number: 20110236809Abstract: A method for examining at least one wafer (13) with regard to a contamination limit, in which the contamination potential of the resist (13a) of the wafer (13), which resist (13a) outgasses contaminating substances, is examined with regard to a contamination limit before the wafer (13) is exposed in an EUV projection exposure system (1). The method preferably includes: arranging the wafer (13) and/or a test disc coated with the same resist (13a) as the resist (13a) of the wafer (13) in a vacuum chamber (19), evacuating the vacuum chamber (19), and measuring the contamination potential of the contaminating substances outgassed from the wafer (13) in the evacuated vacuum chamber (19), and also comparing the contamination potential of the wafer (13) with a contamination limit. An EUV projection exposure system (1) for carrying out the method is also disclosed.Type: ApplicationFiled: June 6, 2011Publication date: September 29, 2011Applicant: CARL ZEISS SMT GMBHInventors: Andreas DORSEL, Stefan SCHMIDT -
Patent number: 8026025Abstract: A method includes a preparation step of preparing a transparent substrate having a precision-polished main surface, a surface shape information obtaining step of obtaining, as surface shape information, height information at a plurality of measurement points on the main surface of the transparent substrate that contacts a mask stage of an exposure apparatus, a simulation step of obtaining, based on the surface shape information and shape information of the mask stage, height information at the plurality of measurement points by simulating the state where the transparent substrate is set in the exposure apparatus, a flatness calculation step of calculating, based on the height information obtained through the simulation, a flatness of the transparent substrate when it is set in the exposure apparatus, a judging step of judging whether or not the calculated flatness satisfies a specification, and a thin film forming step of forming a thin film as serving as a mask pattern, on the main surface of the transparentType: GrantFiled: October 14, 2010Date of Patent: September 27, 2011Assignee: Hoya CorporationInventor: Masaru Tanabe
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Patent number: 8027529Abstract: A system for improving substrate critical dimension uniformity is described. The system includes an exposing means for exposing a plurality of mask patterns on a first plurality of substrates at predetermined locations with common splits of focus ({Fj}) and exposure dose ({Ek}) for each of the first plurality of substrates to form a plurality of perturbed wafers. A measuring means is provided for measuring a critical dimension of the plurality of mask patterns at each of the predetermined locations for each of the plurality of perturbed wafers. An averaging means is provided for averaging the critical dimension measured at each of the predetermined locations over the plurality of perturbed wafers to form a perturbed critical dimension map. A second measuring means is provided for measuring a sidewall angle of the plurality of mask patterns at each of the predetermined locations for each of the plurality of perturbed wafers.Type: GrantFiled: April 23, 2010Date of Patent: September 27, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shinn-Sheng Yu, Chih-Ming Ke, Jacky Huang, Chun-Kuang Chen, Tsai-Sheng Gau
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Patent number: 8021801Abstract: In a method for fabricating a photomask in a semiconductor device, a phase shift layer, a first light blocking layer, an insulating (or intermediate) layer, and a second light blocking layer are deposited on a transparent substrate. A photoresist pattern selectively exposing a surface of the second light blocking layer is formed. A second light blocking pattern exposing a portion of the insulating layer is formed by etching the second light blocking layer using the photoresist pattern as a mask. A critical dimension (CD) of the second light blocking pattern is measured and the CD of the second light blocking pattern is adjusted. A first light blocking pattern and a phase shift pattern are formed by etching the insulating layer, the first light blocking layer, and the phase shift layer using the second light blocking pattern with the adjusted CD as a mask.Type: GrantFiled: December 5, 2007Date of Patent: September 20, 2011Assignee: Hynix Semiconductor Inc.Inventor: Jea-Young Jun
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Patent number: 8021809Abstract: In an embodiment, a device manufacturing method for transferring a pattern from a patterning device onto a substrate includes receiving a design layout information associated with a device, determining the pattern from the design layout information, providing the pattern to a patterning device, determining feed-forward requirement data from the design layout information, wherein the feed-forward requirement data includes at least first feed-forward requirement data related to a first location in the pattern and second feed-forward requirement data related to a second location in the pattern, determining a transfer condition from at least at least the first and the second feed-forward requirement data; and transferring a portion of the pattern from the patterning device onto the substrate based at least in part on the transfer condition.Type: GrantFiled: December 29, 2008Date of Patent: September 20, 2011Assignee: ASML Netherlands B.V.Inventor: Adrianus Cornelis Johannes Van Dijk
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Patent number: 8017286Abstract: In the field of semiconductor device production, a method for manufacturing a surface using two-dimensional dosage maps is disclosed. A set of charged particle beam shots for creating an image on the surface is determined by combining dosage maps for a plurality of shots into the dosage map for the surface. A similar method is disclosed for fracturing or mask data preparation of a reticle image. A method for creating glyphs is also disclosed, in which a two-dimensional dosage map of one or more shots is calculated, and the list of shots and the calculated dosage map are stored for later reference.Type: GrantFiled: August 12, 2009Date of Patent: September 13, 2011Assignee: D2S, Inc.Inventors: Akira Fujimura, Harold Robert Zable
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Patent number: 8017287Abstract: A development method according to an embodiment includes exposing a photosensitive film formed on a substrate at a predetermined exposure amount, carrying out a first development process that develops the exposed photosensitive film at a predetermined first development condition so as to leave the photosensitive film, obtaining a sensitivity information of an unexposed photosensitive film on the substrate from a film thickness reduction of the photosensitive film developed by the first development process and the predetermined exposure amount, predicting pattern dimensions of multiple types of patterns to be formed when a second development process is carried out following the first development process from the sensitivity information, and determining a first acceptable range of a development condition in the second development process, determining a second acceptable range of the development condition in the second development process from the first acceptable range and a variation amount of pattern dimensioType: GrantFiled: September 15, 2009Date of Patent: September 13, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Hideaki Sakurai, Masatoshi Terayama
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Patent number: 8017289Abstract: A method is disclosed in which a plurality of variable shaped beam (VSB) shots is used to form a desired pattern on a surface. In this method some shots within the plurality of shots overlap each other. Additionally, the union of any subset of the plurality of shots differ from the desired pattern. In some embodiments, dosages of the shots vary with respect to each other. In other embodiments, an optimization technique may be used to minimize shot count. In yet other embodiments, the plurality of shots may be optionally selected from one or more pre-computed VSB shots or groups of VSB shots. The method of the present disclosure may be used, for example, in the process of manufacturing an integrated circuit by optical lithography using a reticle, or in the process of manufacturing an integrated circuit using direct write.Type: GrantFiled: January 10, 2011Date of Patent: September 13, 2011Assignee: D2S, Inc.Inventors: Akira Fujimura, Lance Glasser
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Patent number: 8017288Abstract: A method for manufacturing a semiconductor device using a photomask and optical lithography is disclosed, wherein circular patterns on the semiconductor wafer are formed by using circular patterns on the photomask, which is manufactured using a charged particle beam writer. In one embodiment, circular patterns of varying sizes have been formed on the photomask using a single character projection (CP) character, by varying the charged particle beam dosage. A method for fracturing circular patterns is also disclosed, either using circular CP characters or using VSB shots wherein the union of the plurality of VSB shots is different than the set of desired patterns.Type: GrantFiled: August 12, 2009Date of Patent: September 13, 2011Assignee: D2S, Inc.Inventors: Akira Fujimura, Michael Tucker
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Publication number: 20110212389Abstract: A focus test reticle for measuring focus information includes an outer pattern. The outer pattern has a line pattern composed of a light shielding film extending in the Y direction, a phase shift portion provided on a side in the +X direction of the line pattern and formed to have a line width narrower than the line pattern, a transmitting portion provided on a side in the ?X direction of the line pattern and formed to have a line width narrower than the line pattern, a transmitting portion provided on a side in the +X direction of the phase shift portion, and a phase shift portion provided on a side in the ?X direction of the transmitting portion. Focus information of a projection optical system is measured at a high measuring reproducibility and a high measuring efficiency.Type: ApplicationFiled: November 5, 2010Publication date: September 1, 2011Applicant: NIKON CORPORATIONInventors: Shigeru HIRUKAWA, Shinjiro KONDO
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Publication number: 20110212394Abstract: The present invention provides an exposure apparatus including a projection optical system configured to project a reticle pattern onto a wafer, a selector configured to select a dummy wafer to be placed near an image plane of the projection optical system, from a plurality of dummy wafers having the same shape as that of the wafer and different reflectance with each other, a transfer unit configured to place the dummy wafer selected by the selector near the image plane of the projection optical system, and a controller configured to perform control such that dummy exposure is performed by irradiating the dummy wafer, which is placed near the image plane of the projection optical system by the transfer unit, with light via the projection optical system.Type: ApplicationFiled: May 6, 2011Publication date: September 1, 2011Applicant: CANON KABUSHIKI KAISHAInventor: Nobuhiko Yabu
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Patent number: 8007968Abstract: In the present invention, patterning for the first time is performed on a film to be worked above the front surface of a substrate, and the actual dimension of the pattern formed by the patterning for the first time is measured. Based on the dimension measurement result of the patterning or the first time, the condition of patterning for the second time is then set. In this event, the condition of the patterning for the second time is set so that a difference between the dimension of the patterning for the first time and its target dimension is equal to a difference between the dimension of the patterning for the second time and its target dimension. Thereafter, the patterning for the second time is performed under the set patterning condition.Type: GrantFiled: July 25, 2007Date of Patent: August 30, 2011Assignee: Tokyo Electron LimitedInventors: Yoshiaki Yamada, Tadayuki Yamaguchi, Yuuichi Yamamoto, Yasuhito Saiga, Kazuo Sawai
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Publication number: 20110207035Abstract: An exposure apparatus includes an exposure unit selectively performing exposure on a resist layer with a first laser beam, focused by a lens system, in a pattern including pits and lands arranged in a scanning direction; a detecting unit detecting a reflection of a second laser beam applied through the lens system to the resist layer selectively exposed to the first laser beam, the second laser beam being produced by changing a focal length of the lens system such that the resist layer is prevented from responding thereto; a calculating unit calculating, from a result of the detection, a displacement between center axes of signal waveforms representing beams reflected from first and second portions of the pattern having a smallest width and a larger width, respectively; a setting unit setting the focal length of the lens system to such a value that the displacement is maximal; and a control unit controlling the exposure unit to expose the resist layer to the first laser beam focused with the focal length setType: ApplicationFiled: February 16, 2011Publication date: August 25, 2011Applicants: Sony Corporation, Sony DADC CorporationInventors: Akiya Saito, Akitoshi Suzuki, Toru Aida, Shinobu Hayashi
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Publication number: 20110200923Abstract: A substrate treatment method including a first treatment process (S13 to S16) for exposing, heating, and developing a substrate on which a first resist is formed, thereby forming a first resist pattern, and a second treatment process (S17 to S20) for forming a second resist film on the substrate on which the first resist pattern is formed, exposing, heating, and developing the substrate on which the second resist film is formed, thereby forming a second resist pattern. Also, the substrate treatment method compensates a first treatment condition in a first treatment process (S22 to S25) based on a measured value of a line width of the second resist pattern and a second treatment condition in a second treatment process (S26 to S29) based on a measured value of a line width of the first resist pattern.Type: ApplicationFiled: February 8, 2011Publication date: August 18, 2011Applicant: TOKYO ELECTRON LIMITEDInventors: Takafumi NIWA, Hiroshi NAKAMURA, Hideharu KYOUDA
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Publication number: 20110200922Abstract: Embodiments of the invention related to lithographic apparatus and methods. A lithographic method comprises calculating a laser metric based on a spectrum of laser radiation emitted from a laser to a lithographic apparatus together with a representation of an aerial image of a pattern to be projected onto the substrate by the lithographic apparatus, and using the laser metric to modify operation of the laser or adjust the lithographic apparatus, and projecting the pattern onto the substrate.Type: ApplicationFiled: February 2, 2011Publication date: August 18, 2011Applicant: ASML Netherlands B.V.Inventors: Carsten Andreas Köhler, Hans Van Der Laan, Frank Staals, Laurentius Cornelius De Winter, Herman Philip Godfried
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Patent number: 8001495Abstract: A system and method is provided which predicts problematic areas for lithography in a circuit design, and more specifically, which uses modeling data from a modeling tool to accurately predict problematic lithographic areas. The method includes identifying surface heights of plurality of tiles of a modeled wafer, and mathematically mimicking a lithographic tool to determine best planes of focus for exposure for the plurality of tiles.Type: GrantFiled: April 17, 2008Date of Patent: August 16, 2011Assignee: International Business Machines CorporationInventors: Timothy A. Brunner, Stephen E. Greco, Bernhard R. Liegl, Hua Xiang
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Patent number: 7998643Abstract: Disclosed is a method of correcting an error in a phase difference in a phase shift mask, in which a phase shift pattern is formed on a light transmitting substrate, wherein the method includes: determining generation of an error in a phase difference by measuring a phase of a light transmitted through the light transmitting substrate and a phase of a light transmitted through the phase shift pattern; and correcting the error in the phase difference by coating a self-assembled monolayer on the light transmitting substrate when the error of the phase difference is generated.Type: GrantFiled: December 28, 2009Date of Patent: August 16, 2011Assignee: Hynix Semiconductor Inc.Inventor: Jong Woo Kim
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Patent number: 7999399Abstract: An overlay vernier key includes a semiconductor substrate on which a cell region and a scribe lane region are defined, and a plurality of vernier patterns which are formed in the scribe lane region of the semiconductor substrate and arranged in a polygonal shape. Each of the vernier patterns has a hollow polygonal shape.Type: GrantFiled: December 29, 2006Date of Patent: August 16, 2011Assignee: Hynix Semiconductor Inc.Inventors: Byeong Ho Cho, Sung Woo Ko
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Patent number: 7993814Abstract: A method for forming patterns using a single mask includes: disposing a photo mask having a defined pattern, and performing an exposure process by controlling the focal length of an exposure apparatus to a focusing position to form a pattern having the same shape as the photo mask on the wafer; and using the same photo mask, and performing the exposure process by controlling the focal length of the exposure apparatus to a defocusing position to form a reverse pattern having a reversed image with respect to the pattern on the wafer.Type: GrantFiled: June 29, 2007Date of Patent: August 9, 2011Assignee: Hynix Semiconductor Inc.Inventor: Hyun Jo Yang
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Publication number: 20110189600Abstract: The invention relates to processing imaged precursors such as lithographic printing plates. The invention relates specifically to adjusting a processing device for optimal processing performance using a plate recognition system that includes a senseing and authenication subsystem. The processor is automated to make adjustments according to the information provided.Type: ApplicationFiled: January 29, 2010Publication date: August 4, 2011Inventors: Lars Plumer, Pavel Korolik, Danny Koifman, Harald Baumann, Bernd Strehmel
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Publication number: 20110189602Abstract: The disclosed heating device is to perform a heating process on an exposed substrate formed with a resist film before a developing process, the device including a heating part to perform a heating process on the exposed substrate, the heating part including a plurality of two-dimensionally arranged heating elements; a seating part provided at an upper side of the heating part, on which the substrate is disposed; and a control part to correct a setting temperature of the heating part based on temperature correction values, and to control the heating part based on the corrected setting temperature, during the heating process on one substrate by the heating part, wherein the temperature correction values being previously obtained from measured critical dimensions of the resist pattern in another substrate formed with the resist pattern through the heating process by the heating part and then the developing process.Type: ApplicationFiled: February 1, 2011Publication date: August 4, 2011Applicant: TOKYO ELECTRON LIMITEDInventors: Masahide TADOKORO, Yoshihiro KONDO, Takashi SAITO
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Publication number: 20110189601Abstract: In one embodiment, a method of forming a resist pattern on a substrate is provided. Information of a template pattern formed on a template based on template pattern data is obtained. A resist coating distribution is set based on the information of the template pattern. A resist is formed on a substrate based on the resist coating distribution. The template is brought into contact with the resist formed on the substrate so that the resist is filled into the template pattern formed on the template. The filled resist is cured. The template is separated from the cured resist so that a resist pattern is formed on the substrate.Type: ApplicationFiled: September 10, 2010Publication date: August 4, 2011Inventor: Takeshi KOSHIBA
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Patent number: 7985514Abstract: In the field of semiconductor production using shaped charged particle beam lithography, a method and system for fracturing or mask data preparation or proximity effect correction is disclosed, wherein a shot determined for a shaped charged particle beam writer system comprises dragging the charged particle beam across a surface during the shot, so as to form a complex pattern in a single, extended shot. The dragging may be done with either variable shaped beam (VSB) or character projection (CP) shots. Methods for specifying in the shot data the path for the dragged shot are also disclosed. Other embodiments include using dragged shots with partial projection, varying the dragging velocity during a shot, and combining dragged shots with conventional shots. A method and system for creating glyphs which contain dragged shots is also disclosed.Type: GrantFiled: October 21, 2009Date of Patent: July 26, 2011Assignee: D2S, Inc.Inventors: Akira Fujimura, Harold Robert Zable, Michael Tucker
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Patent number: 7987436Abstract: A method of making a mask design having optical proximity correction features is provided. The method can include obtaining a target pattern comprising a plurality of target pattern features corresponding to a plurality of features to be imaged on a substrate. The method can also comprise generating a mask design comprising mask features corresponding to the plurality of features to be imaged on the substrate and controlling the aspect ratio of at least one of the features of the plurality of features to be imaged on the substrate by positioning a sub-resolution assist feature proximate to the corresponding mask feature.Type: GrantFiled: February 17, 2009Date of Patent: July 26, 2011Assignee: Texas Instruments IncorporatedInventors: Scott William Jessen, Mark Terry, Robert Soper
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Patent number: 7985517Abstract: A lithography simulation method for estimating an optical image to be formed on a substrate when a mask pattern is transferred onto the substrate includes dividing the mask pattern into first calculation areas having sizes determined by a range affected by OPC, the range being obtained correspondingly to an exposure wavelength, a numerical aperture and an illumination shape which are used in the transferring the mask pattern onto the substrate, dividing the each of the first calculation areas into second calculation areas, calculating first electromagnetic field distributions formed by illuminating the mask pattern with exposure light and corresponding to the second calculation areas, obtaining second electromagnetic field distributions corresponding to the first calculation areas by synthesizing the first electromagnetic field distributions for each of the first calculation areas, and calculating the optical image to be formed on the substrate by using the second electromagnetic field distributions.Type: GrantFiled: June 3, 2009Date of Patent: July 26, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Satoshi Tanaka, Akiko Mimotogi
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Patent number: 7985516Abstract: A processing temperature of thermal processing is corrected based on measurement of a first dimension of a resist pattern on a substrate from a previously obtained relation between a dimension of a resist pattern and a temperature of thermal processing, a second dimension of the resist pattern after thermal processing is performed at the corrected processing temperature is measured, a distribution within the substrate of the second dimension is classified into a linear component expressed by an approximated curved surface and a nonlinear component, a processing condition of exposure processing is corrected based on the linear component from a previously obtained relation between a dimension of a resist pattern and a processing condition of exposure processing, and thermal processing at the processing temperature corrected in a temperature correcting step and exposure processing under the processing condition corrected in an exposure condition correcting step are performed to form a predetermined pattern.Type: GrantFiled: April 20, 2009Date of Patent: July 26, 2011Assignee: Tokyo Electron LimitedInventors: Kunie Ogata, Masahide Tadokoro, Tsuyoshi Shibata, Shinichi Shinozuka
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Patent number: 7981575Abstract: A method for optical proximity correction (OPC) of a desired pattern for a substrate is disclosed in which a plurality of variable shaped beam (VSB) shots are determined which can form on a surface an OPC-corrected version of the desired substrate pattern. Shots within the plurality of VSB shots are allowed to overlap each other. Dosages of the shots may also be allowed to vary with respect to each other. The union of the plurality of shots may deviate from the OPC-corrected version of the desired pattern for the substrate. In some embodiments, optimization may be used to minimize shot count. In other embodiments, the plurality of shots may be optionally selected from one or more pre-computed VSB shots or groups of VSB shots, that is, glyphs. A method for creating glyphs is also disclosed, in which patterns that would result on a surface from one or a group of VSB shots are pre-calculated.Type: GrantFiled: May 27, 2009Date of Patent: July 19, 2011Assignee: DS2, Inc.Inventors: Akira Fujimura, Lance Glasser
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Patent number: 7977017Abstract: Methods of fabricating a photomask, methods of treating a chemically amplified resist-coated photomask blank, a photomask blank resulting from the methods, and systems for fabricating a photomask are provided. The method is useful for recovering the exposure sensitivity of a chemically amplified resist disposed on a photomask blank from a post-coat delay effect.Type: GrantFiled: November 2, 2010Date of Patent: July 12, 2011Assignee: Micron Technology, Inc.Inventor: Baorui Yang
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Patent number: 7977019Abstract: A semiconductor device manufacturing method, a semiconductor device manufacturing equipment and a computer readable medium storing a computer program provide for easily identifying a cause of a deviation of pattern dimensions from the objective dimension. A first storage section stores a relation between a PEB temperature and a photoresist dimension of a post-lithography. A second storage section stores a relation between a PEB temperature and a post-etching dimension. A primary correction section determines a first corrected PEB temperature for conforming the photoresist dimension of a post-lithography to the objective dimension, using the relation data stored in the first storage section. A secondary correction section determines the second corrected PEB temperature for conforming the post-etching dimension using the first corrected PEB temperature to the objective dimension, using the relation data stored in the second storage section.Type: GrantFiled: February 13, 2009Date of Patent: July 12, 2011Assignee: Renesas Electronics CorporationInventor: Takashi Murakami
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Patent number: 7977018Abstract: In the exposure data preparation method for charged particle beam exposure in which an exposure object is exposed while dose is adjusted for each pattern, the method including the steps of: classifying a pattern in terms of a target linewidth; setting a standard characteristic showing the relationship between a standard dose and a resultant linewidth of a resist pattern for a group of patterns having the target linewidth; and preparing exposure data by correcting a shape and dose so that a characteristic showing the relationship between dose of each pattern having the target linewidth and a resultant linewidth of a resist pattern follows the standard characteristic.Type: GrantFiled: December 11, 2008Date of Patent: July 12, 2011Assignee: Fujitsu Semiconductor LimitedInventors: Kozo Ogino, Yasuhide Machida
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Patent number: 7975244Abstract: A method is provided for designing a mask that includes the use of a pixel-based simulation of a lithographic process model, in which test structures are designed for determining numerical and discretization errors associated with the pixel grid as opposed to other model inaccuracies. The test structure has a plurality of rows of the same sequence of features, but each row is offset from other rows along an x-direction by a multiple of a minimum step size, such as used in modifying masks during optical proximity correction. The images for each row are simulated with a lithographic model that uses the selected pixel-grid size and the differences between row images are compared. If the differences between rows exceed or violate a predetermined criterion, the pixel grid size may be modified to minimize discretization and/or numerical errors due to the choice of pixel grid size.Type: GrantFiled: January 24, 2008Date of Patent: July 5, 2011Assignee: International Business Machines CorporationInventors: Maharaj Mukherjee, James A. Culp, Alan E. Rosenbluth
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Patent number: 7972755Abstract: There is disclosed a substrate processing method by a multi-patterning technique, which comprises a lithography process and an etching process, each of the processes is performed to one substrate at least twice. The substrate processing method is performed by using a substrate processing system comprising a plurality of process units for performing respective steps of the lithography process. When a second lithography process is performed to a substrate, process unit(s) for performing one or more steps of the second lithography process to be used in the second lithography process is automatically selected based on the process history of the first lithography process in such a way that the process unit(s) to be used in the second lithography process is (are) identical to the processed unit(s) used in the first lithography process.Type: GrantFiled: November 14, 2007Date of Patent: July 5, 2011Assignee: Tokyo Electron LimitedInventor: Yuichi Yamamoto
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Patent number: 7968258Abstract: A method for photolithography in semiconductor manufacturing includes providing one or more masks for a wafer; defining a reference focus plane of a first mask of the one or more masks; defining a reference focus plane of a second mask of the one or more masks; and determining the best focus for the second mask based on the best focus of the first mask and the Z direction difference of the first and second masks, using the reference focus planes of the first and second masks.Type: GrantFiled: May 16, 2005Date of Patent: June 28, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Yu Su, Yi-Ming Dai, Chi-Hung Liao, Chun-Hung Kung
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Patent number: 7970485Abstract: Systems for determining width/space limits for product mask layouts. A mask writer generates a first pattern on a test mask corresponding to a test mask layout. A lithography tool generates a second pattern on a wafer corresponding to a first pattern on a test mask by a lithography process using a preset exposure dose. A metrology tool measures widths of the first and second pattern. A controller determines a width/space limit for the product mask layout according to the width difference between the first and second pattern.Type: GrantFiled: May 20, 2009Date of Patent: June 28, 2011Assignee: Winbond Electronics Corp.Inventor: Li-Ming Wang
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Patent number: 7968260Abstract: The present invention has: a first step of measuring, as an initial condition of a substrate, any of a film thickness of a processing film on the substrate, a refractive index of the processing film, an absorption coefficient of the processing film, and a warpage amount of the substrate; a second step of estimating a dimension of a pattern of the processing film after predetermined processing from a previously obtained first relation between the initial condition and the dimension of the pattern of the processing film based on a measurement result of the initial condition; a third step of obtaining a correction value for a processing condition of the predetermined processing from a previously obtained second relation between the processing condition of the predetermined processing and the dimension of the pattern of the processing film based on an estimation result of the dimension of the pattern; a fourth step of correcting the processing condition of the predetermined processing based on the correction valuType: GrantFiled: February 11, 2009Date of Patent: June 28, 2011Assignee: Tokyo Electron LimitedInventors: Masahide Tadokoro, Kunie Ogata
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Patent number: 7968259Abstract: In a multi-project-chip semiconductor device, semiconductor elements fabricated on a wafer have a layout that corresponds to an exposure order of a pattern of the semiconductor elements and that is based on information indicating manufacture conditions and the number of shots and are arranged such that the semiconductor elements having the same manufacture condition are adjacent to each other in ascending or descending order of the number of shots.Type: GrantFiled: December 2, 2008Date of Patent: June 28, 2011Assignee: Fujitsu Semiconductor LimitedInventors: Hiromi Hoshino, Takashi Maruyama
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Publication number: 20110151361Abstract: According to the embodiment, an optical image intensity distribution to be formed in a resist arranged on a lower layer side of a diffraction pattern is calculated by performing a whole image exposure from an upper surface side of the diffraction pattern formed on a substrate. The optical image intensity distribution is calculated by using a multimode waveguide analysis model or a fractional Fourier transform with respect to the diffraction pattern.Type: ApplicationFiled: December 3, 2010Publication date: June 23, 2011Inventors: Masanori TAKAHASHI, Satoshi Tanaka