Including Control Feature Responsive To A Test Or Measurement Patents (Class 430/30)
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Patent number: 7966584Abstract: Disclosed is a method of producing a pattern for a semiconductor device, comprising extracting part of a pattern layout, perturbing a pattern included in the part of the pattern layout to generate a perturbation pattern, correcting the perturbation pattern, predicting a first pattern, to be formed on a wafer, from the corrected perturbation pattern, acquiring a first difference between the perturbation pattern and the first pattern, and storing information concerning the perturbation pattern including information concerning the first difference.Type: GrantFiled: April 8, 2009Date of Patent: June 21, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Suigen Kyoh, Toshiya Kotani, Soichi Inoue
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Patent number: 7966580Abstract: A process-model generation method according to an embodiment of the present invention comprises: forming a test pattern on a film to be processed by exposing a test mask having a mask pattern formed thereon; generating a plurality of process models having a different model parameter; performing a simulation of the mask pattern by using each of the process models to predict a plurality of model patterns; calculating a difference in dimension between the test pattern and each of the model patterns; extracting a model pattern in which the difference in dimension from the test pattern is within a scope of specification from the model patterns; and specifying the process model, which predicts the extracted model pattern, as the mask pattern.Type: GrantFiled: August 5, 2008Date of Patent: June 21, 2011Assignee: Kabushiki Kaisha ToshibaInventor: Shimon Maeda
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Publication number: 20110143271Abstract: A pattern generating method includes obtaining an on-substrate pattern by performing a process for forming the on-substrate pattern by simulation or experiment based on a design pattern of the on-substrate pattern formed by an imprint process using a template, employing the design pattern when a comparison result of the design pattern and obtained on-substrate pattern satisfies a predetermined condition, and correcting the design pattern to satisfy the predetermined condition when the comparison result does not satisfy the predetermined condition.Type: ApplicationFiled: June 24, 2010Publication date: June 16, 2011Inventors: Takeshi KOSHIBA, Hidefumi Mukai, Kazuhito Kobayashi, Takumi Ota
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Publication number: 20110143272Abstract: According to an embodiment, an image forming apparatus includes an image holding member, a plurality of image forming units, an image density detection unit, an image density comparison unit, a control unit, a developer residual amount acquisition unit, and an image stabilization kind determination unit. The plurality of image forming units include at least a developer of a first color and a developer of a second color and form a predetermined pattern image on the image holding member using the developers of the first and second colors. The developer residual amount acquisition unit acquires a residual amount of the developer of the second color.Type: ApplicationFiled: December 7, 2010Publication date: June 16, 2011Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA TEC KABUSHIKI KAISHAInventors: Shingo Urasawa, Hirotaka Fukuyama
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Patent number: 7960078Abstract: A method includes forming a resist film on an etching target layer disposed on a test substrate, and performing sequential light exposure with a predetermined test pattern on the resist film sequentially at a plurality of areas, while respectively using different combinations of a light exposure amount and a focus value, along with subsequent development, thereby forming resist patterns at the plurality of areas; then etching the etching target layer, removing the resist patterns, and measuring shapes of etched patterns at the plurality of areas by means of a scatterometory technique; and determining a management span of combinations of a light exposure amount and a focus value admissible to obtain an etched pattern with a predetermined shape, with reference to the light exposure amounts and focus values used in the sequential light exposure, the line widths of the resist patterns, and the line widths of the etched patterns.Type: GrantFiled: November 8, 2005Date of Patent: June 14, 2011Assignee: Tokyo Electron LimitedInventors: Kazuo Sawai, Akihiro Sonoda
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Patent number: 7955765Abstract: An adjustment method for adjusting an illumination condition in illuminating an original plate using an illumination optical system and projecting an image of a pattern formed on the original plate onto a substrate through a projection optical system includes measuring a polarization state of light that has passed through the illumination optical system, the original plate, and the projection optical system in a state where the original plate is located on an object plane of the projection optical system, and adjusting the polarization state based on the measured polarization state.Type: GrantFiled: July 22, 2008Date of Patent: June 7, 2011Assignee: Canon Kabushiki KaishaInventor: Ken-ichiro Shinoda
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Patent number: 7958463Abstract: A computer automated method for designing an integrated circuit includes placing a plurality of marks on each of contours of a plurality of patterns allocated in a chip area; dividing the marks into a plurality of groups so that the adjacent marks are merged in a same group; determining one of the groups as a candidate hot spot based on a total number of marks included in each of the groups; and modifying the corresponding pattern in the candidate hot spot.Type: GrantFiled: September 30, 2008Date of Patent: June 7, 2011Assignee: Kabushiki Kaisha ToshibaInventor: Atsuhiko Ikeuchi
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Patent number: 7955766Abstract: A software-controlled maskless optical lithography system uses fluorescence feedback to control an aspect of the lithography, such as light source dose, wavelength, or flashing instances or duration, spatial light modulator (SLM) pattern, an optics parameter, a beamsplitter control parameter, or movement or positioning of a stage carrying a target workpiece, such as a semiconductor wafer.Type: GrantFiled: December 30, 2009Date of Patent: June 7, 2011Assignee: The Trustees of Columbia University in the City of New YorkInventor: Ioannis Kymissis
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Method for examining a wafer with regard to a contamination limit and EUV projection exposure system
Patent number: 7955767Abstract: A method for examining at least one wafer (13) with regard to a contamination limit, in which the contamination potential of the resist (13a) of the wafer (13), which resist (13a) outgasses contaminating substances, is examined with regard to a contamination limit before the wafer (13) is exposed in an EUV projection exposure system (1). The method preferably includes: arranging the wafer (13) and/or a test disc coated with the same resist (13a) as the resist (13a) of the wafer (13) in a vacuum chamber (19), evacuating the vacuum chamber (19), and measuring the contamination potential of the contaminating substances outgassed from the wafer (13) in the evacuated vacuum chamber (19), and also comparing the contamination potential of the wafer (13) with a contamination limit. An EUV projection exposure system (1) for carrying out the method is also disclosed.Type: GrantFiled: January 20, 2010Date of Patent: June 7, 2011Assignee: CARL ZEISS SMT GmbHInventors: Andreas Dorsel, Stefan Schmidt -
Patent number: 7952696Abstract: An exposure measurement apparatus is configured by including a size measurer measuring respective sizes of at least a pair of transferred patterns having mutually different optimal focus positions out of a plurality of transferred patterns formed by being transferred onto a transfer object, a difference value calculator obtaining a difference value between the size of one transferred pattern and the size of the other transferred pattern, a focus variation amount calculator calculating a focus variation amount of the transfer object using the difference value, and an exposure variation amount calculator calculating an exposure error amount of a wafer.Type: GrantFiled: October 27, 2004Date of Patent: May 31, 2011Assignee: Fujitsu Semiconductor LimitedInventor: Tomohiko Yamamoto
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Patent number: 7954073Abstract: Methods and apparatus are disclosed that arrange mask patterns in response to the contribution of an assist feature to image intensity. In some methods of arranging mask patterns, a distribution of functions h(??x) is obtained which represents the contribution of an assist feature to image intensity on a main feature. Neighboring regions of the main feature are discretized into finite regions, and the distribution of the functions h(??x) is replaced with representative values h(x,?) of the discretized regions. A position of the assist feature is determined using polygonal regions having the same h(x,?). As described, the term x is the position of the main feature and the term ? is the position of the assist.Type: GrantFiled: June 30, 2008Date of Patent: May 31, 2011Assignee: Samsung Electronics Co., Ltd.Inventor: Dong-woon Park
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Publication number: 20110123913Abstract: An exposure apparatus includes: a first moving body, which comprises guide members that extend in a first direction, moves in a second direction, which is substantially orthogonal to the first direction; two second moving bodies, which are provided such that they are capable of moving in the first direction along the guide members, move in the second direction together with the guide members by the movement of the first moving body; a holding apparatus holds the object and is supported by the two second moving bodies such that it is capable of moving within a two dimensional plane that includes at least the first directions and the second directions; and a transport apparatus, which comprises a chuck member that can noncontactually hold the object from above, transports the object to and from the holding apparatus.Type: ApplicationFiled: November 17, 2010Publication date: May 26, 2011Applicant: NIKON CORPORATIONInventor: Hiromitsu YOSHIMOTO
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Patent number: 7948616Abstract: An image of an aperture pattern that includes an L/S pattern having a linewidth that exceeds the measurement resolution of a measurement device is generated in each of divided areas on a wafer via an optical system. A part of each of the divided areas on the wafer exposed via a projection optical system, and an image of the aperture pattern after removal of a part of the image of the L/S pattern is formed in each of the divided areas. An image of the pattern that is obtained by removing a part of the pattern is formed in each of the divided areas after the wafer is developed. Measurement is performed by a measurement device using the wafer as a sample, and the optical characteristics of the projection optical system (such as a best focus position, field of curvature, or astigmatism) are obtained.Type: GrantFiled: April 11, 2008Date of Patent: May 24, 2011Assignee: Nikon CorporationInventor: Kazuyuki Miyashita
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Patent number: 7947413Abstract: In a pattern evaluation method of determining whether a pattern formed on a photomask is acceptable, an aberration parameter of an image quality evaluation apparatus for determining a pattern image intensity in transferring a pattern formed on a photomask onto a wafer is acquired. An acceptance criterion value used in determining whether an abnormal pattern of the photomask including the effect of aberration of the image quality evaluation apparatus is acceptable is set through a lithographic simulation using the acquired aberration parameter. Then, using the image quality evaluation apparatus, an image intensity of the abnormal pattern of the photomask and an image intensity of a normal pattern corresponding to the abnormal pattern are obtained. It is determined whether the difference between the two acquired image intensities is within the set acceptance criterion value.Type: GrantFiled: October 8, 2008Date of Patent: May 24, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Keiko Morishita, Shingo Kanamitsu
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Patent number: 7943273Abstract: A photomask for integrated circuit production for development of integrated circuit components, where the integrated circuit production uses a radiation source that generates a source image, includes a substrate with one or more layers disposed thereon; a source separator element that separates the source image into one or more duplicate source images; one or more polarizing elements each corresponding to one of the one or more duplicate source images; and one or more sensors each corresponding to one of the one or more polarizing elements, the one or more sensors sensing one or more radiation characteristics of the radiation source.Type: GrantFiled: April 18, 2008Date of Patent: May 17, 2011Assignee: Photronics, Inc.Inventor: Christopher J. Progler
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Patent number: 7945871Abstract: An integrated verification and manufacturability tool provides more efficient verification of integrated device designs than verification using several different verification components. The integrated verification and manufacturability includes a hierarchical database to store shared design data accessed by multiple verification components (e.g., layout versus schematic, design rule check, optical process correction, phase shift mask assignment and OPC verification and machine language conversion). The hierarchical database includes representations of one or more additional, or intermediate layer structures that are created and used by the verification components for operations performed on the design being verified. Use of a single hierarchical database having shared data for access and use by multiple verification components streamlines the verification process, which provides an improved verification tool.Type: GrantFiled: June 24, 2008Date of Patent: May 17, 2011Inventors: Nicolas B. Cobb, Eugene Miloslavsky
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Patent number: 7941232Abstract: By repeatedly executing a predetermined measurement at set intervals, data on a predetermined performance (a best focus position) of a predetermined apparatus and data on variation factors of the performance are obtained (Steps 204 to 214). Based on the obtained data, multivariate analysis is performed and a model equation that is used to predict a variation amount of the performance and includes at least one of the variation factors as a variable is derived (Step 214). Therefore, after deriving the model equation, a variation amount of the performance can be predicted using the model equation by obtaining data on the variation factor that serves as the variable (Step 238). Accordingly, it becomes possible to maintain the performance described above with good accuracy in accordance with the prediction results and also optimize the implementation timing of maintenance and the like.Type: GrantFiled: September 15, 2006Date of Patent: May 10, 2011Assignee: Nikon CorporationInventors: Yuuki Ishii, Shinichi Okita
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Patent number: 7939246Abstract: A deposition energy distribution when a charged particle beam is made incident upon a resist film, is approximated by a sum of element distributions having Gaussian distributions. A pattern area density map partitioning the pattern layout plane into small regions, is defined for each element distribution. First and second sub-steps are repeated for each of the pattern area density maps. In the first sub-step, an area density of each small region is obtained. In the second sub-step, in accordance with an energy deposition rate, an exposure dose assigned to a pattern in a first small region, an area of the pattern and the area density of the first small region, the deposition energy to be given to the target small region is obtained and the corrected area density is calculated. A deposition energy at an evaluation point on a pattern layout plane is calculated from the corrected area densities.Type: GrantFiled: June 14, 2006Date of Patent: May 10, 2011Assignee: Fujitsu Semiconductor LimitedInventor: Kozo Ogino
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Patent number: 7938587Abstract: In the present invention, when dense and sparse resist patterns are formed above a substrate, respective resist pattern dimensions are measured, and a correction value for a first processing unit is calculated based on the dimension measurement result of the dense resist pattern and a correction value for a second processing unit is calculated based on the dimension measurement result of the sparse resist pattern. Based on these calculation results, processing conditions in the first processing unit and the second processing unit are changed, and thereafter processing in these processing units are implemented under these changed conditions.Type: GrantFiled: February 26, 2009Date of Patent: May 10, 2011Assignee: Tokyo Electron LimitedInventor: Takahisa Otsuka
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Publication number: 20110102757Abstract: A method is disclosed. A change in position of a substrate in a direction substantially parallel to a direction of propagation of a radiation beam that is, or is to be, projected on to that substrate is determined, which change in position would result in a lithographic error in the application of a pattern to that substrate using that radiation beam. The change in position of the substrate is used to control a property of the radiation beam when, or as, the radiation beam is projected onto the substrate in order to reduce the lithographic error.Type: ApplicationFiled: October 4, 2010Publication date: May 5, 2011Applicant: ASML Netherlands B. V.Inventors: Hans BUTLER, Remco Jochem Sebastiaan Groenendijk
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Patent number: 7935945Abstract: Using a beam current of an ion beam, and a dose amount to a substrate, and an initial value of a scan number of the substrate set to 1, a scan speed of the substrate is calculated. If the scan speed is within the range, the current scan number and the current scan speed are set as a practical scan number and a practical scan speed, respectively. If the scan speed is higher than the upper limit of the range, the calculation process is aborted. If the scan speed is lower than the lower limit of the range, the scan number is incremented by one to calculate a corrected scan number. A corrected scan speed is calculated by using the corrected scan number, etc. The above steps are repeated until the corrected scan speed is within the allowable scan speed range.Type: GrantFiled: February 11, 2009Date of Patent: May 3, 2011Assignee: Nissin Ion Equipment Co., Ltd.Inventor: Masayoshi Hino
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Patent number: 7935946Abstract: Using a beam current of an ion beam, a dose amount to a substrate, and a reference scan speed, a scan number of the substrate is calculated as an integer value in which digits after a decimal point are truncated. If the scan number is smaller than 2, the process is aborted. If the scan number is equal to or larger than 2, it is determined whether the scan number is even or odd. If the scan number is even, the current scan number is set as a practical scan number. If the scan number is odd, an even scan number which is smaller by 1 than the odd scan number is obtained, and the obtained even scan number is set as a practical scan number. A practical scan speed of the substrate is calculated by using the practical scan number, the beam current, and the dose amount.Type: GrantFiled: February 11, 2009Date of Patent: May 3, 2011Assignee: Nissin Ion Equipment Co., Ltd.Inventor: Masayoshi Hino
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Patent number: 7935546Abstract: A method, structure, system of aligning a substrate to a photomask. The method includes: directing incident light through a pattern of clear regions transparent to the incident light in an opaque-to-the-incident-light region of a photomask, through a lens and onto a photodiode formed in a substrate, the photodiodes electrically connected to a light emitting diode formed in the substrate, the light emitting diode emitting light of different wavelength than a wavelength of the incident lights; measuring an intensity of emitted light from light emitting diode; and adjusting alignment of the photomask to the substrate based on the measured intensity of emitted light.Type: GrantFiled: February 6, 2008Date of Patent: May 3, 2011Assignee: International Business Machines CorporationInventors: Axel Aguado Granados, Benjamin Aaron Fox, Nathaniel James Gibbs, Andrew Benson Maki, John Edward Sheets, II, Trevor Joseph Timpane
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Patent number: 7937676Abstract: In positioning assist features on a photomask pattern to improve the image quality of the main features, the method includes deriving an h-function in a first process which represents a contribution of an assist feature with respect to image intensity at a main feature. In a continuation of the method, the position of the assist features are determined in a second process using the h-function derived in the first step. The assist features are then formed on the mask at the positions indicated. Also included is a computer readable medium having instructions for performing the h-function calculations, and the mask apparatus itself with both main and assist features positioned according to the h-function.Type: GrantFiled: November 8, 2007Date of Patent: May 3, 2011Assignee: Samsung Electronics Co., Ltd.Inventor: Dong-Woon Park
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Patent number: 7935464Abstract: A system and a method for self-aligned dual patterning are described. The system includes a platform for supporting a plurality of process chambers. An etch process chamber coupled to the platform. An ultra-violet radiation photo-resist curing process chamber is also coupled to the platform.Type: GrantFiled: October 30, 2008Date of Patent: May 3, 2011Assignee: Applied Materials, Inc.Inventor: Christopher Siu Wing Ngai
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Patent number: 7933186Abstract: A method and apparatus for manufacturing an optical disk master and an optical disk, including measuring the reflectance of laser light at each of a plurality of radius positions by applying the laser light to an optical disk master-forming substrate provided with an inorganic resist layer, the laser light having a non-recording laser power smaller than a recording sensitivity of the inorganic resist layer, producing recording power control data indicating recording laser powers in accordance with the radius positions of the optical disk master-forming substrate by using the reflectances measured, forming an exposure pattern on the inorganic resist layer by applying the laser light to the optical disk master-forming substrate on the basis of the recording power control data while the recording power is varied in accordance with the radius positions, and developing the inorganic resist layer provided with the exposure pattern so as to prepare an uneven pattern.Type: GrantFiled: April 6, 2007Date of Patent: April 26, 2011Assignee: Sony CorporationInventor: Toshihiko Shirasagi
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Patent number: 7932004Abstract: A method for selecting a set of features for monitoring a lithography process using a reticle, by identifying a set of candidate features, defining control regions around the candidate features, performing substrate level analysis using the reticle with different settings for the lithography process, determining which of the candidate features are most changed by the different settings, ranking the candidate features according to how much they are changed, and selecting the test set of features from those candidate features that are most changed.Type: GrantFiled: September 24, 2009Date of Patent: April 26, 2011Assignee: KLA-Tencor CorporationInventors: Yalin Xiong, Carl E. Hess
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Patent number: 7933015Abstract: A mark for alignment and overlay, a mask having the same, and a method of using the same are provided. The mark includes a first mark pattern and a second mark pattern. The first mark pattern includes a first pattern and a second pattern, and the second mark pattern includes a third pattern and a fourth pattern. The first pattern includes a plurality of rectangular regions arranged in a first direction, and for each rectangular region, a sideline in a second direction is longer than a sideline in the first direction, wherein the first direction is perpendicular to the second direction. The second pattern is disposed on both sides of the first pattern in the second direction and includes a plurality of rectangular regions arranged in the second direction, and for each rectangular region, the sideline in the first direction is longer than a sideline in the second direction.Type: GrantFiled: February 22, 2008Date of Patent: April 26, 2011Assignee: Nanya Technology Corp.Inventors: Chui-Fu Chiu, Jung-Chih Kuo
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Patent number: 7927773Abstract: A memory medium stores a program for generating data on an original pattern used in an exposure apparatus forming an image of a target pattern on a substrate, the program comprising a determination step of determining a final assist pattern based on a light intensity distribution formed by a projection optical system when, of a main pattern and an assist pattern to accompany the main pattern which form the original pattern, only the assist pattern is inserted in an object plane of the projection optical system, and a combining step of combining the final assist pattern and the main pattern to generate data on the original pattern, wherein in the determination step, the final assist pattern is determined by repeating a process of calculating and evaluating the light intensity distribution, and a process of changing the assist pattern to be inserted in the object plane of the projection optical system.Type: GrantFiled: April 8, 2009Date of Patent: April 19, 2011Assignee: Canon Kabushiki KaishaInventor: Manabu Hakko
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Patent number: 7930656Abstract: The present disclosure is directed a method for preparing photomask patterns. The method comprises receiving drawn pattern data for a design database. The drawn pattern data describes first device features and second device features, the second device features being associated with design specifications for providing a desired connectivity of the first device features to the second device features. At least a first plurality of the first device features have drawn patterns that will not result in sufficient coverage to effect the desired connectivity. Photomask patterns are formed for the first device features, wherein the photomask patterns for the first plurality of the first device features will result in the desired coverage. Integrated circuit devices formed using the principles of the present disclosure are also taught.Type: GrantFiled: November 14, 2007Date of Patent: April 19, 2011Assignee: Texas Instruments IncorporatedInventors: Thomas J. Aton, Carl A. Vickery, Frank Scott Johnson, James Walter Blatchford, Benjamen Michael Rathsack, Benjamin McKee
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Publication number: 20110086298Abstract: The substrate holding device of the present invention includes a holding unit that adsorbs and holds the substrate, a measuring section that measures a physical quantity relating to a adsorption force of the holding unit with the substrate mounted on the holding unit; and a control section that carries out a first determination based on a first condition and a measurement result obtained by the measuring section and a second determination based on a second condition that is different from the first condition and a measurement result obtained by the measuring section to select one of at least three preset operations based on the result of first and second determinations to thereby execute processing depending on the selected operation.Type: ApplicationFiled: April 1, 2010Publication date: April 14, 2011Applicant: CANON KABUSHIKI KAISHAInventor: Masatoshi Endo
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Patent number: 7923182Abstract: The field of this disclosure is making three-dimensional topographic structures by means of graduated exposure in a photosensitive material, such as a photoresist, photosensitive polymide, or similar. Such patterns may be written either to be used directly as optical, mechanical, fluidic, etc. components, e.g. diffusors, non-reflecting surfaces, Fresnel lenses and Fresnel prisms, computer-generated holograms, lenslet arrays, etc, or to be used as masters for the fabrication of such components by replication. Replication can be done by molding, pressing, embossing, electroplating, etching, as known in the art. This disclosure includes descriptions of using passive absorbing components in thin resist, using high gamma thick resists with high resolution pattern generators, using multiple focal planes including at least one focal plane in the bottom half of the resist, and iterative simulation of patterning and adjustment of an exposure map.Type: GrantFiled: October 22, 2009Date of Patent: April 12, 2011Assignee: Micronic Laser Systems ABInventors: Torbjörn Sandström, Mikael Wahlsten, Mats Ekberg, Anders Svensson
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Patent number: 7919218Abstract: An aspect of the present invention includes a method for patterning a workpiece covered at least partly with a layer sensitive to electromagnetic radiation by simultaneously using a plurality of exposure beams. In an example embodiment it is determined if any of the beams have an actual position relative to a reference beam which differs from its intended position. An adjustment of the exposure dose for a wrongly positioned beam is performed if said beam is printed at en edge of a feature. Other aspects of the present invention are reflected in the detailed description, figures and claims.Type: GrantFiled: April 19, 2005Date of Patent: April 5, 2011Assignee: Micronic Laser Systems ABInventor: Fredrik Sjostrom
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Publication number: 20110076601Abstract: In a monitoring method of an exposure apparatus, a top critical dimension (TCD) and a bottom critical dimension (BCD) of the test pattern formed on a photo-sensitive material layer are measured. A dose deviation (?E) and a focus deviation (?F) are calculated by following equations: TCD+BCD=??E+(TCD0+BCD0) TCD?BCD=?1?F+?2?F3 Here, ?, ?1 and ?2 are constants, ?E=E?E0, ?F=F?F0, E represents a real exposure dose, F represents a real exposure focus, E0 represents a dose defined when a middle critical dimension of the test pattern is equal to a predetermined value, F0 represents a focus defined when TCD of the test pattern is equal to BCD thereof, and TCD0 and BCD0 are theoretical values in case of E0 and F0.Type: ApplicationFiled: September 29, 2009Publication date: March 31, 2011Applicant: UNITED MICROELECTRONICS CORP.Inventors: Da-Bai Jiang, Ching-Shu Lo
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Patent number: 7914958Abstract: A semiconductor device manufacturing method has forming a first resist pattern on the semiconductor substrate, and then, forming a first pattern on the semiconductor substrate by the use of the first resist pattern, and forming a second resist pattern on the semiconductor substrate by using an imprinter, and then, forming a second pattern on the semiconductor substrate by the use of the second resist pattern. The forming the first pattern, the first pattern smaller than a design pattern corresponding to the design data for forming a plurality of patterns on a semiconductor substrate being formed.Type: GrantFiled: June 4, 2009Date of Patent: March 29, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Ryoichi Inanami, Shinji Mikami, Hirofumi Inoue
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Patent number: 7916284Abstract: In a scatterometric method differential targets with different sensitivities to parameters of interest are printed in a calibration matrix and difference spectra obtained. principal component analysis is applied to the difference spectra to obtain a calibration function that is less sensitive to variations in the underlying structure than a calibration function obtained from spectra obtained from a single target.Type: GrantFiled: July 18, 2006Date of Patent: March 29, 2011Assignee: ASML Netherlands B.V.Inventors: Mircea Dusa, Arie Jeffrey Den Boef, Hugo Augustinus Joseph Cramer
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Patent number: 7917244Abstract: A method for reducing a critical dimension error of a substrate is provided. A first function is identified for correlating a critical dimension error with a first effect. A second function is identified for correlating a critical dimension error with a scan speed. An optimal scan speed for minimizing the critical dimension error is identified by substantially equating the first function and the second function. The substrate may be a mask or a wafer.Type: GrantFiled: March 14, 2007Date of Patent: March 29, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Ming Lin, Chai-Wei Chang
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Patent number: 7913196Abstract: A method of verifying a layout pattern comprises separately steps of obtaining a simulated pattern at a lower portion of a film by using a layout pattern as a mask to transfer the layout pattern to the film, and obtaining a simulated pattern at an upper portion of the film by using the layout pattern as a mask to transfer the layout pattern to the film. The layout pattern is verified according to the upper and lower simulated patterns.Type: GrantFiled: May 23, 2007Date of Patent: March 22, 2011Assignee: United Microelectronics Corp.Inventors: Te-Hung Wu, Chia-Wei Huang, Chuen Huei Yang, Sheng-Yuan Huang, Pei-Ru Tsai, Chih-Hao Wu
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Patent number: 7911612Abstract: An overlay target on a substrate is disclosed, the overlay target including a periodic array of structures wherein every nth structure is different from the rest of the structures. The periodic array is desirably made of two interlaced gratings, one of the gratings having a different pitch from the other grating in order to create an asymmetry in the array. This asymmetry can then be measured by measuring the diffraction spectra of radiation reflected from the overlay target. Variation in the asymmetry indicates the presence of an overlay error in layers on the substrate, where overlay targets are printed on subsequent layers.Type: GrantFiled: June 13, 2007Date of Patent: March 22, 2011Assignee: ASML Netherlands B.V.Inventors: Antoine Gaston Marie Kiers, Arie Jeffrey Den Boef, Maurits Van Der Schaar
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Publication number: 20110065027Abstract: In one embodiment, a flare correction method is disclosed. The method can acquire a flare point spread function. The method can calculate a pattern density distribution in a first region of the mask, the distance from the pattern being equal to or shorter than a predetermined value in the first region. The method can calculate pattern coverage in a second region of the mask, the distance from the pattern being longer than the predetermined value. The method can calculate a first flare distribution with respect to the pattern by performing convolution integration between the flare point spread function corresponding to the first region and the pattern density distribution. The method can calculate a flare value corresponding to the second region by multiplying a value of integral of the flare point spread function corresponding to the second region by the pattern coverage. The method can calculate a second flare distribution by adding the flare value to the first flare distribution.Type: ApplicationFiled: August 26, 2010Publication date: March 17, 2011Inventors: Ryoichi INANAMI, Suigen Kyoh
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Publication number: 20110065028Abstract: According to the embodiments, each of a main pattern of a mask to be transferred onto a substrate by using a lithography process, a first assist pattern that improves a resolution of an on-substrate pattern obtained by transferring the main pattern onto the substrate, and a second assist pattern that suppresses a transfer property of the first assist pattern onto the substrate is placed as a mask pattern.Type: ApplicationFiled: September 2, 2010Publication date: March 17, 2011Inventors: Katsuyoshi KODERA, Satoshi TANAKA, Toshiya KOTANI, Soichi INOUE
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Publication number: 20110065030Abstract: According to one embodiment, a mask pattern determining method includes a mask-pattern dimension variation amount of a first photomask is derived. Moreover, a correspondence relationship between a target dimension value of an on-substrate test pattern formed by using a second photomask and a dimension allowable variation amount of a mask pattern formed on the second photomask is derived. Then, it is determined whether pattern formation is possible with a pattern dimension that needs to be formed when performing the pattern formation on a substrate by using the first photomask based on the mask-pattern dimension variation amount and the correspondence relationship.Type: ApplicationFiled: September 13, 2010Publication date: March 17, 2011Inventors: Toshiya KOTANI, Fumiharu Nakajima, Ryota Aburada, Takafumi Taguchi, Hiromitsu Mashita, Michiya Takimoto, Chikaaki Kodama
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Patent number: 7908572Abstract: An optical proximity correction (OPC) based integrated circuit design system and method introduce a variable rule in which rules are specified in terms of multiple correction actions that yield acceptable results. This category of rules provides more degrees of freedom in actual application so that the rule-based OPC tool can intelligently select the proper valid rule that minimizes the OPC complexity or meets other objectives.Type: GrantFiled: September 8, 2005Date of Patent: March 15, 2011Assignee: Takumi Technology CorporationInventor: Youping Zhang
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Patent number: 7901853Abstract: A pattern prediction method according to an embodiment includes: predicting a second pattern shape from a first pattern shape by using a conversion function and a conversion difference residual error amount function, wherein; the conversion function makes the connection between the first pattern formed by a first step and the second pattern formed by a second step following the first step based on contour shapes of the first pattern and the second pattern, and the conversion difference residual error amount function makes the connection between a residual error amount between a predicted shape of the second pattern obtained from the conversion function and the second pattern shape obtained by actually using the second step, and factors other than the contour shapes of the first pattern and the second pattern.Type: GrantFiled: February 27, 2009Date of Patent: March 8, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Satoshi Tanaka, Masaki Satake
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Patent number: 7901945Abstract: A system and method for recognition of images may include the use of alignment markers. The image recognized may be a pattern from an array, a character, a number, a shape, and/or irregular shapes. The pattern may be formed by elements in an array such as an identification marking and/or a sensor array. More particularly, the system and method relate to discriminating between images by accounting for the orientation of the image. The size and/or location of alignment markers may provide information about the orientation of an image. Information about the orientation of an image may reduce false recognitions. The system and method of image recognition may be used with identification markings, biosensors, micro-fluidic arrays, and/or optical character recognition systems.Type: GrantFiled: July 16, 2008Date of Patent: March 8, 2011Assignee: Board of Regents the University of Texas SystemInventors: Jason E. Meiring, Timothy B. Michaelson, C. Grant Willson
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Patent number: 7901850Abstract: A method for fracturing or mask data preparation or proximity effect correction of a desired pattern to be formed on a reticle is disclosed in which a plurality of variable shaped beam (VSB) shots are determined which can form the desired pattern. Shots within the plurality of VSB shots are allowed to overlap each other. Dosages of the shots may also be allowed to vary with respect to each other. The union of the plurality of shots may deviate from the desired pattern. The plurality of shots may be determined such that a pattern on the surface calculated from the plurality of shots is within a predetermined tolerance of the desired pattern. In some embodiments, an optimization technique may be used to minimize shot count. In other embodiments, the plurality of shots may be optionally selected from one or more pre-computed VSB shots or groups of VSB shots.Type: GrantFiled: May 27, 2009Date of Patent: March 8, 2011Assignee: D2S, Inc.Inventors: Akira Fujimura, Lance Glasser
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Patent number: 7901852Abstract: A method for patterning a substrate is provided, which comprises (a) providing a substrate; (b) applying a first layer comprising a first photo resist to the substrate; (c) applying a second layer comprising a second photo resist over the first layer; (d) patterning the second layer; and (e) inspecting the patterned second layer with an inspection tool; wherein at least one of the first and second layers comprises a contrasting agent which increases the contrast between the first and second layers to the inspection tool.Type: GrantFiled: February 29, 2008Date of Patent: March 8, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Cesar M. Garza, Sungseo Cho
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Patent number: 7901845Abstract: A method for optical proximity correction of a design of a pattern on a surface is disclosed with the method comprising the steps of inputting desired patterns for the substrate and inputting a set of characters some of which are complex characters that may be used for forming the patterns on the surface. A method of creating glyphs is also disclosed.Type: GrantFiled: September 1, 2008Date of Patent: March 8, 2011Assignee: D2S, Inc.Inventors: Akira Fujimura, Lance Glasser, Takashi Mitsuhashi, Kazuyuki Hagiwara
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Patent number: 7901840Abstract: A method includes a preparation step of preparing a transparent substrate having a precision-polished main surface, a surface shape information obtaining step of obtaining, as surface shape information, height information at a plurality of measurement points on the main surface of the transparent substrate that contacts a mask stage of an exposure apparatus, a simulation step of obtaining, based on the surface shape information and shape information of the mask stage, height information at the plurality of measurement points by simulating the state where the transparent substrate is set in the exposure apparatus, a flatness calculation step of calculating, based on the height information obtained through the simulation, a flatness of the transparent substrate when it is set in the exposure apparatus, a judging step of judging whether or not the calculated flatness satisfies a specification, and a thin film forming step of forming a thin film as serving as a mask pattern, on the main surface of the transparentType: GrantFiled: February 27, 2006Date of Patent: March 8, 2011Assignee: Hoya CorporationInventor: Masaru Tanabe
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Patent number: 7902528Abstract: A method of particle beam lithography includes selecting at least two cell patterns from a stencil, correcting proximity effect by dose control and by pattern modification for the at least two cell patterns, and writing the at least cell two patterns by one shot of the particle beam after proximity effect correction (PEC).Type: GrantFiled: November 21, 2006Date of Patent: March 8, 2011Assignee: Cadence Design Systems, Inc.Inventors: Daisuke Hara, Katsuo Komuro, Takashi Mitsuhashi