Plural Exposure Steps Patents (Class 430/394)
  • Patent number: 12648458
    Abstract: An electrical device is provided that includes a wiring level including a plurality of metal lines, and an dielectric filling a space between adjacent metal lines in the plurality of metal lines of the wiring level. The dielectric comprises an epoxy composition having a filler of magnetic fillers. The dielectric has a permeability that reduces crosstalk noise between the adjacent metal lines in the plurality of metal lines of the wiring level.
    Type: Grant
    Filed: June 29, 2023
    Date of Patent: June 2, 2026
    Assignee: International Business Machines Corporation
    Inventor: Hiroyuki Mori
  • Patent number: 12645148
    Abstract: An EUV radiation source apparatus includes an EUV source vessel; a tin layer disposed in the EUV source vessel; a chamber disposed adjacent to the EUV source vessel; and a first filter disposed in the chamber, wherein the first filter includes a membrane and a mesh disposed on the membrane, and the membrane and the mesh are integrally formed. A method for generating EUV radiation includes: forming a first filter including a membrane and a mesh integrally formed with the membrane; disposing the first filter in a chamber adjacent to an EUV source vessel; and collecting fuel debris on the first filter in the chamber.
    Type: Grant
    Filed: August 25, 2023
    Date of Patent: June 2, 2026
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chien-Hsing Lu, Chih-Chiang Tu, Chih-Wei Wen, Hsin-Fu Tseng, Tzu Jeng Hsu
  • Patent number: 12619156
    Abstract: An extreme ultraviolet (EUV) light uniformity control apparatus includes a plurality of nano thin-films each having a band shape extending in a first direction that is a scanning direction of EUV exposure equipment and linearly arranged under a reticle of the EUV exposure equipment in a second direction that is perpendicular to the first direction. The apparatus further includes thin film mounts fixing the nano thin-films on both sides in the first direction, and a thin film control device connected to the thin film mounts and controlling the nano thin-films. EUV light from the EUV exposure equipment is projected onto a wafer that is an exposure target, after passing through the nano thin-films twice by being incident to and reflected from the reticle, and the EUV light projected on the wafer is uniformly adjusted by using the thin film control device.
    Type: Grant
    Filed: June 29, 2023
    Date of Patent: May 5, 2026
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eunhee Jeang, Jeonggil Kim
  • Patent number: 12601621
    Abstract: A method of manufacturing a dielectric barrier discharge (DBD) structure includes forming a patterned electrode layer around an outer perimeter of a substrate composed of a dielectric material. The patterned electrode layer includes multiple electrodes around the outer perimeter of the substrate and gaps between adjacent electrodes. The method further includes depositing a dielectric layer over at least a first region of the patterned electrode layer to form a DBD region of the DBD structure.
    Type: Grant
    Filed: June 29, 2022
    Date of Patent: April 14, 2026
    Assignee: Applied Materials, Inc.
    Inventors: David John Jorgensen, Jian Wu, Vladimir Nagorny, Hugo Rivera
  • Patent number: 12581869
    Abstract: One aspect provides semiconductor-superconductor hybrid device comprises a substrate, a first semiconductor component arranged on the substrate, a superconductor component arranged to be capable of energy level hybridisation with the first semiconductor component, and a second semiconductor component arranged as a gate electrode for gating the first semiconductor component. Another aspect provides a semiconductor-superconductor hybrid device, comprising: a substrate; a semiconductor component arranged on the substrate; a gate electrode for gating the semiconductor component; and a superconductor component capable of undergoing energy level hybridisation with the semiconductor component; wherein the gate electrode is arranged in a channel in the substrate. Also provided are methods of fabricating the semiconductor-superconductor hybrid devices.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: March 17, 2026
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Marina Quintero Pérez, David Johannes Van Woerkom, Vinay Kumar Chinni, Amrita Singh
  • Patent number: 12581933
    Abstract: Embodiments relate to an electronic circuit implemented using a first integrated circuit die, a second integrated circuit die, and an interposer connecting the first integrated circuit die to the second integrated circuit die. The first integrated circuit die implements a first electronic circuit. The first integrated circuit die includes a first set of contacts on a bottom surface, a buried power rail (BPR), and a plurality of through-silicon vias (TSV) for connecting the BPR to the first set of contacts. The interposer includes a second set of contacts and a power delivery network (PDN). Each contact of the second set of contact corresponds to a contact of the first set of contacts of the first integrated circuit die. The PDN is configured to route a power supply voltage to the second set of contacts.
    Type: Grant
    Filed: April 15, 2024
    Date of Patent: March 17, 2026
    Assignee: Synopsys, Inc.
    Inventors: Xi-Wei Lin, Victor Moroz
  • Patent number: 12578655
    Abstract: A method for controlling a lithographic apparatus configured to pattern an exposure field on a substrate including at least a sub-field, the method including: obtaining an initial spatial profile associated with a spatial variation of a performance parameter associated with a layer on the substrate across at least the sub-field of the exposure field; and decomposing the initial spatial profile into at least a first component spatial profile for controlling a lithographic apparatus at a first spatial scale and a second component spatial profile for controlling the lithographic apparatus at a second spatial scale associated with a size of the sub-field, wherein the decomposing includes co-optimizing the first and second component spatial profiles based on correcting the spatial variation of the performance parameter across the sub-field.
    Type: Grant
    Filed: May 12, 2023
    Date of Patent: March 17, 2026
    Assignee: ASML NETHERLANDS B.V.
    Inventors: Rowin Meijerink, Putra Saputra, Pieter Gerardus Jacobus Smorenberg, Theo Wilhelmus Maria Thijssen, Khalid Elbattay, Ma Su Su Hlaing, Paul Derwin, Bo Zhong, Masaya Komatsu
  • Patent number: 12558838
    Abstract: A 3D printing system includes a tank containing a liquid photopolymer resin. A textured surface is disposed in the tank. The textured surface is configured such that light passes through therethrough and into the liquid polymer resin. A layer of an inert material is disposed on the textured surface.
    Type: Grant
    Filed: November 23, 2022
    Date of Patent: February 24, 2026
    Assignees: NISSAN NORTH AMERICA, INC., NORTHWESTERN UNIVERSITY
    Inventors: Nanzhu Zhao, Evan Jones, Sandeep Patil, Cheng Sun
  • Patent number: 12535740
    Abstract: A method for lithographically patterning a photoresist is provided. The method includes receiving a wafer with the photoresist and exposing the photoresist using an extreme ultraviolet (EUV) radiation reflected by an EUV mask. The EUV mask includes a substrate, a reflective multilayer stack on the substrate, a capping layer on the reflective multilayer stack, a patterned absorber layer on the capping layer. The patterned absorber layer includes a matrix metal and an interstitial element occupying interstitial sites of the matrix metal, and a size ratio of the interstitial element to the matrix metal is from about 0.41 to about 0.59.
    Type: Grant
    Filed: April 8, 2022
    Date of Patent: January 27, 2026
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Jhih Lin, Pei-Cheng Hsu, Ta-Cheng Lien, Chia-Jen Chen, Hsin-Chang Lee
  • Patent number: 12528889
    Abstract: The present invention relates to a homogeneous liquid/fluid combination of photoinitiators with improved formulability, reactivity and surface curing performances, more particularly to novel combinations of acylphosphine oxides and ketocoumarins, optionally further combined with at least one co-initiator.
    Type: Grant
    Filed: October 9, 2020
    Date of Patent: January 20, 2026
    Assignee: IGM RESINS ITALIA S.R.L.
    Inventors: Angelo Casiraghi, Gabriele Norcini, Stephen Postle
  • Patent number: 12528309
    Abstract: Provided is a decorative sheet which combines an excellent touch with design attractiveness. The decorative sheet comprises a base layer, a protrusion layer partly disposed, and a first resin layer in this order, in which the first resin layer contains a matting agent and the layer of protrusions contains particles.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: January 20, 2026
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventors: Shohei Ishiguro, Yosuke Abe, Masahiro Yasuhara
  • Patent number: 12509603
    Abstract: A photo-curable ink jet ink set includes an undercoating photo-curable ink jet ink containing a (meth)acrylic acid ester having a vinyl ether group expressed by general formula (I), and an overcoating photo-curable ink jet ink. The undercoating photo-curable ink jet ink has a higher surface tension than the overcoating photo-curable ink jet ink.
    Type: Grant
    Filed: November 3, 2023
    Date of Patent: December 30, 2025
    Assignee: Seiko Epson Corporation
    Inventors: Keitaro Nakano, Jun Ito
  • Patent number: 12512407
    Abstract: Methods for fabricating interconnect arrangements of a metallization layer Mx by using stitching that is enabled by subtractive metallization are disclosed. An example method includes providing a metal layer and a collection layer over the metal layer. The method then includes forming openings for two sets of metal lines by performing a first lithographic process to provide, in the collection layer, first openings for a first set of lines, and then performing a second lithographic process to provide, in the collection layer, second openings for a second set of lines. The method further includes performing a third lithographic process to provide a further opening (a stitch opening) that overlaps with at least one of the first openings of a first track and at least one of the second openings of a second track, and, finally, transferring the pattern of the first, second, and stitch openings to the metal layer.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: December 30, 2025
    Assignee: Intel NDTM US LLC
    Inventors: Guillaume Bouche, Andy Chih-Hung Wei
  • Patent number: 12481219
    Abstract: An illumination optical system that irradiates a target object with light from a light source unit includes an integrator optical system, a condenser lens, and a bandpass filter. The integrator optical system is disposed on an optical path of the light emitted from the light source unit and uniformizes an illuminance distribution of the light with which the target object is to be irradiated. The condenser lens includes a plurality of lenses and irradiates the target object with the light emitted from the integrator optical system. The bandpass filter is disposed between any two of the plurality of lenses included in the condenser lens.
    Type: Grant
    Filed: November 27, 2023
    Date of Patent: November 25, 2025
    Assignee: Ushio Denki Kabushiki Kaisha
    Inventors: Osamu Osawa, Koichi Ito
  • Patent number: 12472685
    Abstract: A method and device of polymerization to form 3D objects is provided. The method and device incorporate an inert immiscible liquid between a liquid monomer and a light source such that the liquid monomer is polymerized when exposed to polymerization light from the light source at a liquid monomer-inert immiscible liquid interface. The liquid monomer is polymerized into a solid polymer that forms the 3D object.
    Type: Grant
    Filed: January 11, 2019
    Date of Patent: November 18, 2025
    Assignee: UNIVERSITY OF FLORIDA RESEARCH FOUNDATION, INCORPORATED
    Inventors: Toshikazu Nishida, Aftab A. Bhanvadia
  • Patent number: 12448677
    Abstract: A mask assembly and method for manufacturing of the same are provided. A mask assembly includes: a mask frame including a first mask opening and a second mask opening which are located side by side in a first direction and defined by a support bar; a first split mask overlapping the first mask opening; and a second split mask overlapping the second mask opening, and the first split mask and the second split mask are spaced apart from each other in a region overlapping the support bar.
    Type: Grant
    Filed: March 29, 2023
    Date of Patent: October 21, 2025
    Assignee: Samsung Display Co., Ltd.
    Inventors: Se Il Kim, Sang Min Yi, Eui Gyu Kim, Dae Won Baek
  • Patent number: 12444689
    Abstract: The present disclosure provides a semiconductor substrate, including a first dielectric layer with a first surface and a second surface, a first conductive via extending between the first surface and the second surface, a first patterned conductive layer on the first surface, and a second patterned conductive layer on the second surface. The first conductive via includes a bottom pattern on the first surface and a second patterned conductive layer on the second surface. The bottom pattern has at least two geometric centers corresponding to at least two geometric patterns, respectively, and a distance between one geometric center and an intersection of the two geometrical patterns is a geometric radius. A distance between the at least two geometric centers is greater than 1.4 times the geometric radius. A method for manufacturing the semiconductor substrate described herein and a semiconductor package structure having the semiconductor substrate are also provided.
    Type: Grant
    Filed: February 6, 2024
    Date of Patent: October 14, 2025
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Sheng-Ming Wang, Tien-Szu Chen, Wen-Chih Shen, Hsing-Wen Lee, Hsiang-Ming Feng
  • Patent number: 12430490
    Abstract: A method for generating a mask pattern to be employed in a patterning process. The method including obtaining (i) a first feature patch including a first polygon portion of an initial mask pattern, and (ii) a second feature patch including a second polygon portion of the initial mask pattern; adjusting the second polygon portion at a patch boundary between the first feature patch and the second feature patch such that a difference between the first polygon portion and the second polygon portion at the patch boundary is reduced; and combining the first polygon portion and the adjusted second polygon portion at the patch boundary to form the mask pattern.
    Type: Grant
    Filed: October 23, 2023
    Date of Patent: September 30, 2025
    Assignee: ASML NETHERLANDS B.V.
    Inventors: Quan Zhang, Yong-Ju Cho, Zhangnan Zhu, Boyang Huang, Been-Der Chen
  • Patent number: 12423498
    Abstract: A semiconductor structure includes first and second active regions extending in a first direction. The semiconductor structure further includes gate electrodes extending in a second direction perpendicular to the first direction. Each of the gate electrodes includes a first segment over at least one of the first active region or the second active region; a gate extension extending beyond each of the first active region and the second active region, wherein the gate extension has a uniform width in the first direction, and a conductive element, wherein a width of the conductive element in the first direction increases as a distance from the gate extension increases along an entirety of the conductive element in the second direction.
    Type: Grant
    Filed: July 28, 2023
    Date of Patent: September 23, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Jen Chen, Ling-Sung Wang, I-Shan Huang, Chan-yu Hung
  • Patent number: 12405536
    Abstract: The method for optimizing a light source in integrated circuit manufacturing, includes following steps: S1, providing an initial light source; S2, performing region segmentation according to light intensity distribution of the initial light source to obtain a plurality of sub light source regions; S3, providing at least two matching patterns and matching them with each sub light source region to obtain at least two matching results corresponding to each sub light source region; S4, performing calculating based on the at least two matching results and each sub light source region to obtain a best matching pattern corresponding to each sub light source region; and S5, generating a light source to be optimized based on the best matching pattern corresponding to each sub light source region.
    Type: Grant
    Filed: May 19, 2023
    Date of Patent: September 2, 2025
    Assignee: SHENZHEN JINGYUAN INFORMATION TECHNOLOGY CO., LTD
    Inventors: Ge Yan, Ming Ding
  • Patent number: 12357978
    Abstract: A composition, method, and article of manufacture are disclosed. The composition is a microcapsule that includes a transparent shell encapsulating a mixture comprising light upconversion molecules. The method is a method of forming a microcapsule, which includes obtaining light upconversion molecules, forming an emulsion of the light upconversion molecules and a shell formation solution, and encapsulating the light upconversion molecules in a transparent shell. The article of manufacture comprises the microcapsule.
    Type: Grant
    Filed: August 7, 2020
    Date of Patent: July 15, 2025
    Assignee: International Business Machines Corporation
    Inventors: Brandon M. Kobilka, Jason T. Wertz, Sarah K. Czaplewski-Campbell, Eric J. Campbell
  • Patent number: 12350880
    Abstract: Methods and apparatus comprising a dewetting phase and a polymerization liquid that are immiscible, and can be used for the formation of three-dimensional objects, wherein the method does not require a dead zone. Additionally, methods and apparatus that employ an optically transparent cooling apparatus to mitigate heat generated during the fabrication process, and the use of a mobile phase to provide a shearing interface to reduce interfacial adhesive forces.
    Type: Grant
    Filed: September 6, 2022
    Date of Patent: July 8, 2025
    Assignee: NORTHWESTERN UNIVERSITY
    Inventors: Chad A. Mirkin, David A. Walker, James L. Hedrick, III
  • Patent number: 12353122
    Abstract: A method for forming a photomask includes the following steps. A first target pattern is provided, wherein the first target pattern includes a first pattern area and a second pattern area. The first pattern area includes a block pattern. The second pattern area includes multiple stripe patterns. A first sidewall reset area is defined in the second pattern area. A retarget procedure is executed on the first target pattern to obtain a second target pattern. The photomask is formed based on the second target pattern.
    Type: Grant
    Filed: November 3, 2022
    Date of Patent: July 8, 2025
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventor: Chun-Liang Lin
  • Patent number: 12353120
    Abstract: A reflective mask includes a substrate, a lower reflective multilayer disposed over the substrate, an intermediate layer disposed over the lower reflective multilayer, an upper reflective multilayer disposed over the intermediate layer, a capping layer disposed over the upper reflective multilayer, and an absorber layer disposed in a trench formed in the upper reflective layers and over the intermediate layer. The intermediate layer includes a metal other than Cr, Ru, Si, Si compound and carbon.
    Type: Grant
    Filed: July 30, 2021
    Date of Patent: July 8, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Che Hsieh, Chi-Lun Lu, Ping-Hsun Lin, Fu-Sheng Chu, Ta-Cheng Lien, Hsin-Chang Lee
  • Patent number: 12349495
    Abstract: A semiconductor device includes a plurality of wirings each having a damascene structure on a semiconductor layer, wherein the plurality of wirings includes a first wiring and a second wiring adjacent to each other, wherein the first wiring includes, along a direction in which the first wiring extends, a first portion, a second portion, and a third portion located between the first portion and the second portion, and wherein a width of the third portion is larger than each of a width of the first portion and a width of the second portion.
    Type: Grant
    Filed: February 16, 2021
    Date of Patent: July 1, 2025
    Assignee: Canon Kabushiki Kaisha
    Inventors: Junya Tamaki, Takafumi Miki, Ryo Yoshida, Atsushi Kanome, Kosuke Asano, Takehiro Toyoda, Masaki Kurihara
  • Patent number: 12331394
    Abstract: A method of forming an inorganic film on a surface can include depositing a polymer at a layer on a surface, swelling the polymer with a solvent to produce a swollen polymer on the surface, infiltrating the swollen polymer with a precursor, removing the swollen polymer after infiltrating the swollen polymer with the precursor, and forming a porous inorganic film on the surface based on removing the swollen polymer.
    Type: Grant
    Filed: July 22, 2023
    Date of Patent: June 17, 2025
    Assignee: UNIVERSITY OF NORTH TEXAS
    Inventors: Diana Berman, Elena V. Shevchenko, Supratik Guha
  • Patent number: 12327726
    Abstract: A patterning method includes forming a multilayer photoresist stack on a substrate. The multilayer photoresist stack includes a first layer of a wet photoresist, deposited by spin-on deposition, over a second layer of a dry photoresist, deposited by vapor deposition. The multilayer photoresist stack is exposed to a first pattern of actinic radiation including relative, spatially-varying doses of actinic radiation and including high-dose regions, mid-dose regions and low-dose regions. The multilayer photoresist stack and the first pattern of actinic radiation are configured such that after the exposing the multilayer photoresist stack to the first pattern of actinic radiation, in the high-dose regions, developability of both the first layer and the second layer is changed; in the mid-dose regions, developability of the first layer is changed while developability of the second layer is unchanged; in the low-dose regions, developability of both the first layer and the second layer is unchanged.
    Type: Grant
    Filed: May 3, 2022
    Date of Patent: June 10, 2025
    Assignee: Tokyo Electron Limited
    Inventor: Anton J. Devilliers
  • Patent number: 12285915
    Abstract: A method of forming a part includes 3D printing a photopolymerizable resin and forming a preformed part and subsequently post-curing the preformed part with electron beams. The preformed part may be cured via UV curing. A section of the preformed part post-cured with electron beams may have a thickness of at least 1.0 centimeter, for example, at least 2.0 centimeters or at least 3.0 centimeters. An electron beam dosage to post-cure the preformed part may be between 10 kilogray (kGy) and 100 kGy. The preformed part may be 3D printed using stereolithography (SLA), digital light processing (DLP) or material jetting (MJ) and the photopolymerizable resin may include at least one of an acrylate functional polymer and a methacrylate functional polymer. In the alternative, or in addition to, the photopolymerizable resin may include at least one of a urethane, a polyester, and a polyether.
    Type: Grant
    Filed: July 9, 2021
    Date of Patent: April 29, 2025
    Assignee: Ford Global Technologies, LLC
    Inventors: Christopher Michael Seubert, Mark Edward Nichols, Ellen Cheng-chi Lee
  • Patent number: 12282261
    Abstract: Methods of fabricating an object via direct laser lithography are provided. In embodiments, such a method comprises illuminating, via an optical fiber having an end facet and a metalens directly on the end facet, a location within a photosensitive composition from which an object is to be fabricated with light, thereby inducing a multiphoton process within the photosensitive composition to generate a region of the object; and repeating the illuminating step one or more additional times at one or more additional locations to generate one or more additional regions of the object.
    Type: Grant
    Filed: November 1, 2021
    Date of Patent: April 22, 2025
    Assignee: Northwestern University
    Inventors: Sridhar Krishnaswamy, Heming Wei, Wisnu Hadibrata, Koray Aydin
  • Patent number: 12194531
    Abstract: This application describes kits, methods, and systems of three dimensional printing. In some examples, described herein are three-dimensional object printing kits comprising a metallic or a ceramic build material, a polymeric binder dispersed in an aqueous liquid vehicle, and a boundary fluid comprising thermally expandable particles.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: January 14, 2025
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: James P Shields
  • Patent number: 12154932
    Abstract: An electronic detection interface for testing micro photoelectric chips or micro semiconductor chips comprises a substrate structure and a plurality of detection units in array, responsive to the micro photoelectric chips or the micro semiconductor chips. The substrate structure includes a circuit film, which comprises a plurality of circuit units in array. The detection units are disposed on a surface of the substrate structure, and are corresponded to the circuit units in a respect manner. Each of the detection units includes at least one resilient conductive pillar, which is electrically connected to each of the circuit units through a conductive pad. Each of the resilient conductive pillars is a conductive photoresist.
    Type: Grant
    Filed: April 13, 2023
    Date of Patent: November 26, 2024
    Assignee: ULTRA DISPLAY TECHNOLOGY CORP.
    Inventor: Hsien-Te Chen
  • Patent number: 12147166
    Abstract: An apparatus for manufacturing semiconductors includes a power amplifier to power a laser, a catalyst disposed in the power amplifier, an inlet port, and an exhaust port. The inlet port introduces a mixing gas to an interior of the power amplifier during a cleaning operation so that the mixing gas contacts a surface of the catalyst having a build-up thereon. The mixing gas reacts with and removes the build-up by generating gaseous by-products. The exhaust port removes the gaseous by-products from the power amplifier.
    Type: Grant
    Filed: June 15, 2023
    Date of Patent: November 19, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Ping Yen, Yen-Shuo Su, Jui-Pin Wu, Chun-Lin Chang, Han-Lung Chang, Heng-Hsin Liu
  • Patent number: 12137747
    Abstract: An electrically operated smoking device configured to receive a smoking article is provided, including: a housing defining a cavity configured to at least partially receive the smoking article; and an image sensor configured to detect indicia on the smoking article, the image sensor being disposed on a periphery of the cavity and including a light source, an image detector, and a plurality of microlenses held in a support structure, the plurality of microlenses being configured to provide a mosaic of inverted images on the image detector. A smoking system is also provided.
    Type: Grant
    Filed: October 8, 2021
    Date of Patent: November 12, 2024
    Assignee: Philip Morris Products S.A.
    Inventors: Christiane Gimkiewicz, Rolf Eckert, Edoardo Franzi, David Hasler, Ross Stanley
  • Patent number: 12134227
    Abstract: A method of forming a three-dimensional object includes: providing a carrier and an optically transparent member having a build surface, the carrier and the build surface defining a build region therebetween; filling the build region with a polymerizable liquid, irradiating the build region with light through the optically transparent member to form a solid polymer from the polymerizable liquid, and advancing said carrier away from said build surface to form said three-dimensional object from said solid polymer. The irradiating step includes projecting focused light at the build region, and the advancing step is carried out at a rate that is dependent on an average light intensity of the focused light.
    Type: Grant
    Filed: July 8, 2022
    Date of Patent: November 5, 2024
    Assignee: CARBON, INC.
    Inventors: Joseph M. DeSimone, Alexander Ermoshkin, Edward T. Samulski, Jason P. Rolland
  • Patent number: 12111572
    Abstract: A method of imprinting a pattern on a substrate is provided. The method includes forming a first pattern on a plurality of masters using a method other than imprinting, the first pattern including a plurality of patterned features of varying sizes; measuring the patterned features at a plurality of locations on each of the masters; selecting a first master of the plurality of masters based on the measurements of the patterned features on each of the masters; using the first master to form a second pattern on an imprint template; and imprinting the first pattern on a first device with the imprint template.
    Type: Grant
    Filed: June 12, 2023
    Date of Patent: October 8, 2024
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Hao Tang, Kang Luo, Erica Chen, Yongan Xu
  • Patent number: 12070818
    Abstract: The present invention relates to an information storage medium and a method for long-term storage of information comprising the steps of: providing a ceramic substrate; coating the ceramic substrate with a layer of a second material different from the material of the ceramic substrate, the layer having a thickness no greater than 10 ?m; tempering the coated ceramic substrate to form a writable plate or disc; encoding information on the writable plate or disc by using a laser and/or a focused particle beam to manipulate localized areas of the writable plate or disc.
    Type: Grant
    Filed: April 19, 2021
    Date of Patent: August 27, 2024
    Assignee: Ceramic Data Solutions GmbH
    Inventors: Martin Kunze, Christian Pflaum
  • Patent number: 12053920
    Abstract: An apparatus dispenses a raw material in liquid form into a manufacturing zone. The raw material is, by computer-controlled, point-by-point targeted light irradiation, heated and solidified by the region of incidence of a light beam relative to the manufacturing zone being altered in a continuous and/or in a step-by-step manner. The light beam is emitted from the light beam source, or from an optical unit influencing the light of the light beam source, with a substantially ring-shaped light intensity profile. The ring-shaped light intensity profile is formed by a ring-shaped region in which the light intensity initially increases in the direction toward the center of the ring from the outer diameter and then drops off again toward the inner diameter of the ring, with the light intensity being equal to zero in the interior region of the ring.
    Type: Grant
    Filed: November 23, 2018
    Date of Patent: August 6, 2024
    Assignee: MEDIZINISCHE HOCHSCHULE HANNOVER
    Inventors: Jan Stieghorst, Theodor Doll
  • Patent number: 12055849
    Abstract: A method for correcting a semiconductor mask pattern includes steps as follows: A pattern to be corrected in the semiconductor mask pattern is divided into a plurality of sub-blocks that are symmetrical to and coincide with each other. Then, an optical proximity correction (OPC) step is performed on one of the plurality of sub-blocks to obtain a modified template. At least one copy template is generated according to the modified template corresponding to the other ones of the plurality of sub-blocks. The modified template and the at least one copy template are spliced to form a correcting pattern to replace the original pattern to be corrected.
    Type: Grant
    Filed: June 30, 2021
    Date of Patent: August 6, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Sheng-Lun Tseng, Yen-Ting Pan, Chih-Wei Hsu
  • Patent number: 12044965
    Abstract: A method for producing a component without tabs during etching. The method includes: applying a wafer tape to the plated side of the substrate; depositing a resist layer on a metal layer on a metal side of the substrate that is opposite of the plated side; exposing the resist layer to UV light; developing the resist layer; and etching the metal layer.
    Type: Grant
    Filed: February 9, 2021
    Date of Patent: July 23, 2024
    Assignee: Hutchinson Technology Incorporated
    Inventors: Clark T. Olsen, Jeffery G. Ribar
  • Patent number: 11999098
    Abstract: The present invention relates to a method for additive manufacturing of a 3D-structured form and to a device for additive manufacturing of a 3D-structured form.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: June 4, 2024
    Assignee: Karlsruher Institut für Technologie
    Inventors: Vincent Hahn, Patrick Müller, Eva Blasco, Martin Wegener
  • Patent number: 11988868
    Abstract: A mask material is deposited on a substrate or growth template. The substrate or growth template is compatible with crystalline growth of a crystalline optical material. Patterned portions of the mask material are removed to expose one or more regions of the substrate or growth template. The one or more regions have target shapes of one or more optical components. The crystalline optical material is selectively grown in the one or more regions to form the one or more optical components.
    Type: Grant
    Filed: January 27, 2021
    Date of Patent: May 21, 2024
    Assignee: XEROX CORPORATION
    Inventor: Thomas Wunderer
  • Patent number: 11982935
    Abstract: A reflective mask blank for EUV lithography includes a substrate and, formed on or above the substrate in the following order, a reflective layer for reflecting EUV light, a protective layer for the reflective layer, an absorption layer for absorbing EUV light, and a hard mask layer. The protective layer contains ruthenium (Ru), the absorption layer contains tantalum (Ta), the hard mask layer contains chromium (Cr) and at least one of nitrogen (N) and oxygen (O), and the hard mask layer has a film density of from 3.00 g/cm3 to 5.40 g/cm3.
    Type: Grant
    Filed: November 17, 2021
    Date of Patent: May 14, 2024
    Assignee: AGC INC.
    Inventors: Hirotomo Kawahara, Hiroshi Hanekawa, Toshiyuki Uno, Masafumi Akita
  • Patent number: 11984384
    Abstract: Embodiments relate to an electronic circuit implemented using a first integrated circuit die, a second integrated circuit die, and an interposer connecting the first integrated circuit die to the second integrated circuit die. The first integrated circuit die implements a first electronic circuit. The first integrated circuit die includes a first set of contacts on a bottom surface, a buried power rail (BPR), and a plurality of through-silicon vias (TSV) for connecting the BPR to the first set of contacts. The interposer includes a second set of contacts and a power delivery network (PDN). Each contact of the second set of contact corresponds to a contact of the first set of contacts of the first integrated circuit die. The PDN is configured to route a power supply voltage to the second set of contacts.
    Type: Grant
    Filed: September 9, 2021
    Date of Patent: May 14, 2024
    Assignee: Synopsys, Inc.
    Inventors: Xi-Wei Lin, Victor Moroz
  • Patent number: 11972953
    Abstract: A semiconductor structure and a manufacturing method thereof are provided. The method includes: providing a substrate; forming, on the substrate, a first mask layer having a plurality of strip-shaped first patterns arranged in parallel; forming, on the first mask layer, a second mask layer having a plurality of strip-shaped second patterns arranged in parallel; forming, on the second mask layer, a third mask layer having a plurality of strip-shaped third patterns arranged in parallel, the second patterns overlap with the third patterns, and the second patterns and the third patterns are configured to sever the first patterns at predetermined positions; and performing layer-by-layer etching, using the first mask layer, the second mask layer, and the third mask layer as masks to transfer the first patterns, the second patterns, and the third patterns to the substrate to form an array of discrete active areas.
    Type: Grant
    Filed: August 7, 2021
    Date of Patent: April 30, 2024
    Assignee: Changxin Memory Technologies, Inc.
    Inventor: Zhen Zhou
  • Patent number: 11955421
    Abstract: An integrated circuit includes a plurality of transistors and an interlevel dielectric layer formed over the transistors. The interlevel dielectric layer includes a first region and a second region with a higher dielectric constant than the first region. The difference in dielectric constant is produced by curing the first region shielding the second region from the curing. Metal signal lines are formed in the first region. Metal-on-metal capacitors are formed in the second region.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: April 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Anhao Cheng
  • Patent number: 11957038
    Abstract: A mask includes a body unit through which a deposition opening is defined, and a protrusion unit through which a pattern opening is defined and which protrudes from a corner of the body unit, where a thickness of the body unit is greater than a thickness of the protrusion unit.
    Type: Grant
    Filed: April 30, 2021
    Date of Patent: April 9, 2024
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Areum Lee, Jeongkuk Kim, Hwi Kim, Seungyong Song, Kyu Hwan Hwang
  • Patent number: 11940725
    Abstract: A blankmask for EUV lithography includes a substrate, a reflective layer, a capping layer, and a phase shift layer. The phase shift layer is made of a material containing ruthenium (Ru) and chromium (Cr), and a total content of ruthenium (Ru) and chromium (Cr) is 50 to 100 at %. The phase shift layer may further contain boron (B) or nitrogen (N). The phase shift layer of the present invention has a high relative reflectance (relative reflectance with respect to a reflectance of the reflective layer under the phase shift layer) with respect to a tantalum (Ta)-based phase shift layer and has a phase shift amount of 170 to 230°. It is possible to obtain excellent resolution when finally manufacturing a pattern of 7 nm or less by using a photomask manufactured using such a blankmask.
    Type: Grant
    Filed: December 6, 2021
    Date of Patent: March 26, 2024
    Assignee: S&S Tech Co., Ltd.
    Inventors: Cheol Shin, Yong-Dae Kim, Jong-Hwa Lee, Chul-Kyu Yang, Min-Kwang Park, Mi-Kyung Woo
  • Patent number: 11941221
    Abstract: A touch sensor includes a sensing part in which a plurality of sensing cells is arranged and connected and a wiring part connected to the sensing part and formed outside the sensing part. The wiring part includes a first divisional wiring part having a plurality of first divisional wires having a connecting protrusion with a width larger than that of the wiring at one end thereof and a second divisional wiring part having a plurality of second divisional wires having one end thereof with a width smaller than that of the connecting protrusion and coupled to and overlapped with the connecting protrusion. The first divisional wiring part and the second divisional wiring part are formed by divisional exposure.
    Type: Grant
    Filed: August 4, 2021
    Date of Patent: March 26, 2024
    Assignee: DONGWOO FINE-CHEM CO., LTD.
    Inventors: Dongjin Son, Junha Kim
  • Patent number: 11934095
    Abstract: A method of managing a critical dimension error includes (i) defining, in a photomask, N openings having a width, where N is a natural number, (ii) using graphs for each of the N openings, each of the graphs being obtained by setting locations through an opening of the N openings as a first axis and an intensity of transmitting light as a second axis, obtaining ILSi proportional to an inclination of a tangent to a graph of the graphs at a location corresponding to an edge of an opening and Ii which is an intensity of transmitting light at the location, where i is a natural number from 1 to N, (iii) obtaining, with respect to each of the N openings, a real width CDi of the openings, and (iv) when I a ? v ? e = 1 N ? ? i = 1 N ? I i , CD a ? v ? e = 1 N ? ? i = 1 N ? CD i ? ? and ? ? ILS a ? v ? e = 1 N ? ? i = 1 N ? ILS i , obtaining AIMEEFi which is an aerial image mask error enhancement factor with respect to each of the N openings accordi
    Type: Grant
    Filed: July 19, 2021
    Date of Patent: March 19, 2024
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jaehyuk Chang, Taejoon Kim, Hyunkyu Sun, Sikyung Lim
  • Patent number: 11928296
    Abstract: A display device may include a display panel, an input sensing unit, and an alignment structure. The display panel may include a sealing member. The input sensing unit may be disposed on the display panel. The input sensing unit may include first-type sensor electrodes directly contacting a face of a first insulator of the display device, a first-type connector electrically connecting the first-type sensor electrodes, second-type sensor electrodes directly contacting the face of the first insulator of the display device, and a second-type connector electrically connecting the second-type sensor electrodes. The alignment structure may overlap the sealing member and may include a transparent member that directly contacts the face of the first insulator of the display device.
    Type: Grant
    Filed: October 31, 2022
    Date of Patent: March 12, 2024
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jong Seon Park, Hwan Hee Jeong