Plural Exposure Steps Patents (Class 430/394)
  • Patent number: 9746774
    Abstract: A method for mitigating shot noise in extreme ultraviolet (EUV) lithography and patterning of photo-sensitized chemically-amplified resist (PS-CAR) is described. The method includes a first EUV patterned exposure to generate a photosensitizer and a second flood exposure at a wavelength different than the wavelength of the first EUV patterned exposure, to generate acid in regions exposed during the first EUV patterned exposure, wherein the photosensitizer acts to amplify acid generation and improve contrast. The resist may be exposed to heat, liquid solvent, solvent atmosphere, or a vacuum to mitigate the effects of EUV shot noise on photosensitizer concentration which may accrue during the first EUV patterned exposure.
    Type: Grant
    Filed: February 23, 2015
    Date of Patent: August 29, 2017
    Assignee: Tokyo Electron Limited
    Inventors: Michael A. Carcasi, Mark H. Somervell
  • Patent number: 9698070
    Abstract: In various embodiments, an arrangement is provided. The arrangement may include a plurality of chips; a chip carrier carrying the plurality of chips, the chip carrier including a chip carrier notch; and encapsulation material encapsulating the chip carrier and filling the chip carrier notch; wherein the outer circumference of the encapsulation material is free from a recess.
    Type: Grant
    Filed: April 11, 2013
    Date of Patent: July 4, 2017
    Assignee: Infineon Technologies AG
    Inventors: Michael Ledutke, Edward Fuergut
  • Patent number: 9465287
    Abstract: Methods of forming a pattern in a semiconductor device structure include deprotecting an outer portion of a first photosensitive resist material, forming a second photosensitive resist material, exposing portions of the first and second photosensitive resist materials to radiation, and removing the deprotected outer portion of the first photosensitive resist material and the exposed portions of the first and second photosensitive resist materials. Additional methods include forming a first resist material over a substrate to include a first portion and a relatively thicker second portion, deprotecting substantially the entire first portion and an outer portion of the second portion while leaving an inner portion of the second portion protected, and forming a second resist material over the substrate. A portion of the second resist material is exposed to radiation, and deprotected and exposed portions of the first and second resist materials are removed.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: October 11, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Scott L. Light, Yuan He, Michael A. Many, Michael Hyatt
  • Patent number: 9406499
    Abstract: A semiconductor structure includes a wafer including a first surface and a periphery, a plurality of protrusions protruded from the first surface and a plurality of recesses spaced from each other by the plurality of protrusions, and each of the plurality of recesses is extended from the periphery of the wafer and is elongated across the first surface of the wafer.
    Type: Grant
    Filed: February 12, 2014
    Date of Patent: August 2, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chen-Chun Chen, Chiu-Jung Chen, Fu-Tsun Tsai, Shiu-Ko Jangjian, Chi-Cherng Jeng, Hsin-Chi Chen
  • Patent number: 9354510
    Abstract: An extreme ultraviolet (EUV) mask can be used in lithography, such as is used in the fabrication of a semiconductor wafer. The EUV mask includes a low thermal expansion material (LTEM) substrate and a reflective multilayer (ML) disposed thereon. A capping layer is disposed on the reflective ML and a patterned absorption layer disposed on the capping layer. The pattern includes an antireflection (ARC) type pattern.
    Type: Grant
    Filed: April 4, 2014
    Date of Patent: May 31, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Fang Yu, Ting-Hao Hsu, Sheng-Chi Chin
  • Patent number: 9310698
    Abstract: A lithographic exposure process is performed on a substrate using a scanner. The scanner comprises several subsystems. There are errors in the overlay arising from the subsystems during the exposure. The overlay errors are measured using a scatterometer to obtain overlay measurements. Modeling is performed to separately determine from the overlay measurements different subsets of estimated model parameters, for example field distortion model parameters, scan/step direction model parameters and position/deformation model parameters. Each subset is related to overlay errors arising from a corresponding specific subsystem of the lithographic apparatus. Finally, the exposure is controlled in the scanner by controlling a specific subsystem of the scanner using its corresponding subset of estimated model parameters. This results in a product wafer being exposed with a well controlled overlay.
    Type: Grant
    Filed: January 24, 2011
    Date of Patent: April 12, 2016
    Assignee: ASML Netherlands B.V.
    Inventors: Boris Menchtchikov, Alexander Viktorovych Padiy
  • Patent number: 9278504
    Abstract: The present invention relates to a decorative film to be attached to an outside surface of a home appliance and a method for manufacturing the same, and more particularly, to a decorative film to be attached to an outside surface of a home appliance which is to be attached to an outside of a home appliance, such as a refrigerator, an air conditioner or a washing machine, replacing stainless steel panel etched to form a pattern to have metal feeling; and a method for manufacturing the same. The decorative film to be attached to an outside surface of a home appliance comprises a base layer, a pattern layer on a back side of the base layer, the pattern layer having a micro pattern, a metal layer on a back side of the pattern layer, and a protective layer of synthetic resin attached to a back side of the metal layer for protecting the metal layer.
    Type: Grant
    Filed: August 17, 2010
    Date of Patent: March 8, 2016
    Assignee: LG ELECTRONICS INC.
    Inventors: Hyun Woo Jun, Hyun Gi Jung, Min Ju Son
  • Patent number: 9235119
    Abstract: A method that forms a film of photoresist composition on a substrate and exposes a first and second region of the film to radiation through a first and second mask having a first and second image pattern, respectively. The photoresist composition includes a polymer comprising at least one acid labile group, a photosensitive acid generator capable of generating a first amount of acid upon exposure to a first dose of radiation and of generating a second amount of acid upon exposure to a second dose of radiation, and a photosensitive base generator capable of generating a first amount of base upon exposure to the first dose of radiation and of generating a second amount of base upon exposure to the second dose of radiation. The photosensitive acid generator includes (trifluoro-methylsulfonyloxy)-bicyclo[2.2.1]hept-5-ene-2,3-dicarboximide (MDT), N-hydroxy-naphthalimide dodecane sulfonate (DDSN), or a combination thereof. The photosensitive base generator includes a quaternary ammonium salt.
    Type: Grant
    Filed: August 12, 2014
    Date of Patent: January 12, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Kuang-Jung Chen, Wu-Song Huang, Ranee Wai-Ling Kwong, Sen Liu, Pushkara R. Varanasi
  • Patent number: 9217927
    Abstract: Provided is a method for fabricating a microstructure. The method includes disposing an X-ray mask on photosensitive material and exposing the photosensitive material by radiating X-rays to the photosensitive material, etching the exposed photosensitive material, forming a mold having a micro-pattern by filing the etched photosensitive material with metal, forming a mold module by combining a plurality of molds, and forming a microstructure using the mold module.
    Type: Grant
    Filed: November 2, 2009
    Date of Patent: December 22, 2015
    Assignee: POSTECH ACADEMY-INDUSTRY FOUNDATION
    Inventors: Bong-Kee Lee, Dong Sung Kim, Tai-Hun Kwon, Young Ok Lee
  • Patent number: 9122176
    Abstract: A method for fabricating a semiconductor device, includes dividing a pattern region of a desired pattern that is to be formed on a semiconductor substrate into a plurality of sub-regions; calculating combination condition including a shape of illumination light for transferring and a mask pattern obtained by correcting a partial pattern in the sub-region of the desired pattern formed on a mask used during transferring for each of the plurality of sub-regions, to make a dimension error of the partial pattern of each of the plurality of sub-regions smaller when transferred to the semiconductor substrate; and forming the desired pattern by making multiple exposures on the semiconductor substrate in such a way that the partial patterns of the sub-regions divided are sequentially transferred by transferring a pattern to the semiconductor substrate using the combination conditions calculated for each of the sub-regions.
    Type: Grant
    Filed: March 27, 2012
    Date of Patent: September 1, 2015
    Assignee: NuFlare Technology, Inc.
    Inventor: Takayuki Abe
  • Patent number: 9104833
    Abstract: A mask set for double exposure process and method of using said mask set. The mask set is provided with a first mask pattern having a first base and a plurality of first teeth and protruding portions, and a second mask pattern having a second base and a plurality of second teeth, wherein the second base may at least partially overlap the first base such that each of the protruding portions at least partially overlaps one of the second teeth.
    Type: Grant
    Filed: May 26, 2014
    Date of Patent: August 11, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Fang Kuo, Ming-Jui Chen, Ting-Cheng Tseng, Cheng-Te Wang
  • Patent number: 9017904
    Abstract: A method of providing a photolithography pattern can be provided by identifying at least one weak feature from among a plurality of features included in a photolithography pattern based on a feature parameter that is compared to a predetermined identification threshold value for the feature parameter. A first region of the weak feature can be classified as a first dosage region and a second region of the weak feature can be classified as a second dosage region. Related methods and apparatus are also disclosed.
    Type: Grant
    Filed: July 25, 2013
    Date of Patent: April 28, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin Choi, Heung-Suk Oh, Sin-jeung Park, Rae-won Yi
  • Patent number: 9005875
    Abstract: A method of fabricating a substrate including coating a first resist onto a hardmask, exposing regions of the first resist to electromagnetic radiation at a dose of 10.0 mJ/cm2 or greater and removing a portion of said the and forming guiding features. The method also includes etching the hardmask to form isolating features in the hardmask, applying a second resist within the isolating features forming regions of the second resist in the hardmask, and exposing regions of the second resist to electromagnetic radiation having a dose of less than 10.0 mJ/cm2 and forming elements.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: April 14, 2015
    Assignee: Intel Corporation
    Inventors: Robert L. Bristol, Paul A. Nyhus, Charles H. Wallace
  • Patent number: 9005854
    Abstract: A conductive pattern is formed using a reactive polymer comprising pendant tertiary alkyl ester groups, a compound that provides an acid upon exposure to radiation, and a crosslinking agent. A polymeric layer is patternwise exposed to form first exposed regions with a polymer comprising carboxylic acid groups that are contacted with electroless seed metal ions, and then contacted with a halide to form corresponding electroless seed metal halide. Another exposure converts electroless seed metal halide to electroless seed metal nuclei and forms second exposed regions. A reducing agent is used to develop the electroless seed metal nuclei in the second exposed regions, or to develop the electroless seed metal halide in the first exposed regions. Fixing is used to remove any remaining electroless seed metal halide. The electroless seed metal nuclei are then electrolessly plated in various exposed regions.
    Type: Grant
    Filed: November 5, 2013
    Date of Patent: April 14, 2015
    Assignee: Eastman Kodak Company
    Inventors: Mark Edward Irving, Thomas B. Brust
  • Patent number: 8993217
    Abstract: Innovative techniques are disclosed for fabricating microelectronic devices using an alternating phase shift mask. Some embodiments of the invention encompass a double exposure technique that utilize high resolution line patterning such that two opaque lines intersect at an angle. After development, substantially circular images may be formed. In certain embodiments, high resolution disk imaging as small as 60 nm is possible.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: March 31, 2015
    Assignee: Western Digital (Fremont), LLC
    Inventors: Ling Wang, Dujiang Wan, Miao Wang, Hai Sun
  • Patent number: 8993224
    Abstract: One illustrative method disclosed herein involves identifying an overall target pattern comprised of at least one hole-type feature, decomposing the overall target pattern into at least a first sub-target pattern and a second sub-target pattern, wherein the first sub-target pattern and the second sub-target pattern each comprise at least one common hole-type feature, generating a first set of mask data information corresponding to the first sub-target pattern, and generating a second set of mask data information corresponding to the second sub-target pattern.
    Type: Grant
    Filed: May 23, 2014
    Date of Patent: March 31, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Yuyang Sun, Norman S. Chen, Jian Liu
  • Patent number: 8986554
    Abstract: A method of forming patterns includes forming a photoresist film on a substrate. The photoresist film is exposed with a first dose of light to form a first area and a second area in the photoresist film. A first hole and a second hole are formed by removing the first area and the second area with a first developer. The photoresist film is re-exposed with a second dose of the light to form a third area in the photoresist film between the first hole and the second hole. A third hole is formed between the first hole and the second hole by removing the third area with a second developer.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: March 24, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eun-sung Kim, Kyoung-seon Kim, Jae-woo Nam, Chul-ho Shin, Shi-young Yi
  • Patent number: 8980540
    Abstract: A solid-state image sensor is manufactured through a plurality of photolithography processes. The plurality of photolithography processes includes at least one first lithography process including a dividing exposure step of exposing a substrate using a plurality of photomasks, and at least one second lithography process including a non-dividing exposure step of exposing the substrate using one photomask. The at least one first lithography process includes a process for forming a resist pattern to define active regions on the substrate, and a process for forming a resist pattern to define charge accumulation region.
    Type: Grant
    Filed: February 21, 2013
    Date of Patent: March 17, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventor: Hideomi Kumano
  • Patent number: 8974683
    Abstract: A method of reducing roughness in an opening in a surface of a resist material disposed on a substrate, comprises generating a plasma having a plasma sheath and ions therein. The method also includes modifying a shape of a boundary defined between the plasma and the plasma sheath with a plasma sheath modifier so that a portion of the boundary facing the resist material is not parallel to a plane defined by the surface of the substrate. The method also includes providing a first exposure of ions while the substrate is in a first position, the first exposure comprising ions accelerated across the boundary having the modified shape toward the resist material over an angular range with respect to the surface of the substrate.
    Type: Grant
    Filed: September 9, 2011
    Date of Patent: March 10, 2015
    Inventors: Ludovic Godet, Patrick M. Martin, Joseph C. Olson, Andrew J. Hornak
  • Patent number: 8956791
    Abstract: According to one embodiment, an exposure tolerance estimation method is disclosed. The method can include setting a plurality of regions along a first surface of a substrate. The method can form a plurality of patterns for estimation by performing exposure on each of the regions using at least three levels of exposure condition using an exposure mask. The method can measure dimensions of the patterns for estimation and find relationships between the exposure condition and the dimensions. The method can select a first region from the regions. In the first region, a first dimension of a first pattern for estimation formed by exposure using a first exposure condition of an intermediate level out of the at least three levels falls within a previously set range. In addition, the method can calculate an exposure tolerance from a relationship between the first exposure condition and the first dimension.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: February 17, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Osamu Yamane, Kazuyuki Masukawa, Yasunobu Kai
  • Patent number: 8945797
    Abstract: A mask, a pattern disposing method thereof and an exposing method thereof are provided. A plurality of geometric patterns are arranged on the mask along a plurality of columns. The arrangement of the patterns arranged along odd columns is similar to that of the patterns arranged along even columns. Two odd columns or two even columns are selected to be a first edge column and a second edge column respectively. At each corresponding position of the first edge column and the second edge column, only one of the first edge column and the second edge column is selected to be disposed one geometric pattern.
    Type: Grant
    Filed: January 16, 2013
    Date of Patent: February 3, 2015
    Assignee: Macronix International Co., Ltd.
    Inventors: Shih-Rung Wu, Shao-Wei Hsieh
  • Patent number: 8945800
    Abstract: In a multiple patterning techniques, where two or more exposures are used to form a single layer of a device, the splitting of features in a single layer between the multiple exposures is carried out additionally with reference to features of another associated layer and the splitting of that layer into two or more sets of features for separate exposure. The multiple exposure process can be a process involving repeated litho-etch steps desirably, the alignment scheme utilized during exposure of the split layers is optimized with reference to the splitting approach.
    Type: Grant
    Filed: August 12, 2013
    Date of Patent: February 3, 2015
    Assignee: ASML Netherlands B.V.
    Inventors: Tsann-Bim Chiou, Mircea Dusa, Alek Chi-Heng Chen
  • Patent number: 8945811
    Abstract: A system and method for forming encoded microparticles is described. One embodiment includes an encoded microparticle, the microparticle comprising a plurality of segments aligned along an axis, wherein the plurality of segments define a code for the microparticle; and an outer cuboid encapsulating the plurality of segments, wherein the plurality of segments are detectable through the outer cuboid.
    Type: Grant
    Filed: February 6, 2013
    Date of Patent: February 3, 2015
    Assignee: Affymetrix, Inc.
    Inventor: Randall J. True
  • Patent number: 8932785
    Abstract: An EUV mask set and method of manufacturing is disclosed. In one embodiment, a set of EUV mask blanks is inspected to obtain information about defects in each of the EUV mask blanks. From the obtained information, a set of complementary functional portions is determined, wherein each functional portion is assigned to one of the EUV mask blanks and does not contain any of the defects. The functional portions of the EUV mask blanks of the EUV mask blank set complement one another to form a virtual image area corresponding in size to image areas of the EUV mask blanks. A predefined mask pattern is provided on the EUV mask blanks. Information identifying position and shape of the functional portions is used to control an illumination process for imaging the predefined mask pattern onto a target.
    Type: Grant
    Filed: October 16, 2012
    Date of Patent: January 13, 2015
    Assignee: Advanced Mask Technology Center GmbH & Co. KG
    Inventor: Clemens Utzny
  • Patent number: 8927200
    Abstract: A double patterning method includes providing a first resist film on a substrate using a first photoresist composition. The first resist film is exposed. The exposed first resist film is developed using a first developer to form a first resist pattern. A second resist film is provided in at least space areas of the first resist pattern using a second photoresist composition. The second resist film is exposed. The exposed second resist film is developed using a second developer that includes an organic solvent to form a second resist pattern. The first resist pattern is insoluble or scarcely soluble in the second developer.
    Type: Grant
    Filed: October 22, 2013
    Date of Patent: January 6, 2015
    Assignee: JSR Corporation
    Inventors: Kanako Meya, Takeo Shioya, Motoyuki Shima
  • Patent number: 8927198
    Abstract: A two-dimensional dense array of contact holes can be printed on a negative photoresist employing a combination of a quadrupole illumination lens and a lithographic mask including a criss-cross pattern of opaque lines. The openings in the quadrupole illumination lens are aligned along the perpendicular directions of the opaque lines. Discrete contact holes can be printed on a negative photoresist employing a combination of a quadrupole illumination lens and a lithographic mask including a criss-cross pattern of opaque subresolution assist features and discrete opaque cross patterns. Alternately, a two-dimensional array of contact holes can be printed on a negative photoresist employing a quadrupole illumination lens and a checkerboard pattern of openings. The openings in the quadrupole illumination lens are in diagonal directions.
    Type: Grant
    Filed: January 15, 2013
    Date of Patent: January 6, 2015
    Assignee: International Business Machines Corporation
    Inventors: Martin Burkhardt, Yongan Xu
  • Patent number: 8911920
    Abstract: A method for fabricating integrated circuits includes fabricating an EUV mask by providing a photomask having a border region. A photoresist is formed over the photomask and has a border region overlying the border region of the photomask. The method exposes an inner portion and an outer portion of the photoresist border region. The method removes the inner portion and the outer portion to expose the border region of the photomask. The border region of the photomask is etched using the photoresist as a mask to form the EUV mask with a non-reflective border. The photoresist is removed from the EUV mask. The method includes forming another photoresist over a partially-fabricated integrated circuit layer and patterning the photoresist by exposure to EUV light reflected from the EUV mask to expose portions of the partially-fabricated integrated circuit layer. Portions of the partially-fabricated integrated circuit layer and the photoresist are removed.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: December 16, 2014
    Assignee: GlobalFoundries, Inc.
    Inventors: Sudharshanan Raghunathan, Pawitter Mangat, Hui Peng Koh
  • Patent number: 8900776
    Abstract: An embodiment of the disclosed technology provides a mask plate for photolithography process comprising a first pattern region, a second pattern region having a different exposure level from that of the first pattern region, and a redundant pattern provided between the first pattern region and the second pattern region, wherein the redundant pattern is configured for forming a redundant photoresist pattern so as to prevent developer diffusion at different concentrations across the photoresist redundant pattern.
    Type: Grant
    Filed: January 11, 2012
    Date of Patent: December 2, 2014
    Assignee: Boe Technology Group Co., Ltd.
    Inventors: Guanbao Hui, Seungjin Choi, Feng Zhang, Jianshe Xue
  • Patent number: 8895211
    Abstract: A mask is disclosed which includes a plurality of first phase shift regions disposed on a first side of the mask, and a plurality of second phase shift regions disposed on a second side of the mask. The first phase shift regions and second phase shift regions may be alternating phase shift regions in which phase shift of the first phase shift regions is out of phase, for instance by 180 degrees, from phase shift of the second phase shift regions. A method for forming the mask, and a semiconductor device fabrication method using the mask is also disclosed.
    Type: Grant
    Filed: December 11, 2012
    Date of Patent: November 25, 2014
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventors: Guoxiang Ning, Chunyu Wong, Paul Ackmann, Sarasvathi Thangaraju
  • Patent number: 8889337
    Abstract: Such a film forming method is provided that can prevent peeling of surface films including a resist film from a substrate during immersion exposure. The film forming method includes the steps of forming surface films including a resist film and a protective film covering the resist film over a surface of a wafer, and forming an edge cap film by supplying an edge cap film material to at least a boundary portion including a periphery of the wafer and peripheries of the surface films such as the protective film.
    Type: Grant
    Filed: November 2, 2007
    Date of Patent: November 18, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Hitoshi Kosugi, Taro Yamamoto, Yoshiaki Yamada, Yasuhito Saiga
  • Patent number: 8883393
    Abstract: The invention relates to an imaging element and a method of using the imaging element to form a recording element. The imaging element includes a composition sensitive to actinic radiation at a first wavelength and a photoluminescent tag that is responsive to radiation at a second wavelength different from the first wavelength. The photoluminescent tag can be used to authenticate the identity of the element, provide information about the element, and/or to establish one or more conditions in a device used to prepare the recording element from the imaging element.
    Type: Grant
    Filed: December 9, 2009
    Date of Patent: November 11, 2014
    Assignee: E I du Pont de Nemours and Company
    Inventor: Anandkumar R. Kannurpatti
  • Patent number: 8877433
    Abstract: Provided is a method of manufacturing a liquid injection head, the method including: forming, on a substrate, a negative photosensitive resin layer having a first surface on a side opposite to the substrate and a second surface on the substrate side; carrying out first exposure of the negative photosensitive resin layer; carrying out second exposure of the negative photosensitive resin layer; and forming the ejection orifice by carrying out development after the first exposure and the second exposure in which each of the first surface and the second surface has a portion in which a part of the unexposed portion in the first exposure and a part of the unexposed portion in the second exposure overlap and a portion in which a part of the unexposed portion in the first exposure and a part of the unexposed portion in the second exposure do not overlap.
    Type: Grant
    Filed: April 5, 2013
    Date of Patent: November 4, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventors: Tetsushi Ishikawa, Tamaki Sato
  • Patent number: 8877431
    Abstract: A process for producing a liquid ejection head by providing, in one chip, a liquid ejection head having a portion for ejection in which an ejection orifice array is arranged and a side portion having no ejection orifice array, these portions being provided with a member of a photosensitive material, arranging the chip on a common substrate in such a chip array that these two portions are alternately arranged, and separating each chip from the substrate, the process including the steps of relatively moving a reticle of an aligner along the chip array for a photosensitive material on the substrate to expose each chip, and developing the material to obtain the member. A first reticle for forming the portion for ejection and a second reticle for forming only the side portion are used. The exposure includes a first and a second exposure treatment respectively by the first and second reticles.
    Type: Grant
    Filed: January 2, 2014
    Date of Patent: November 4, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takuma Kodoi, Chiaki Muraoka, Keiji Tomizawa
  • Patent number: 8871428
    Abstract: New photoresist compositions are provided that are useful for immersion lithography. Preferred photoresist compositions of the invention comprises two or more distinct materials that can be substantially non-mixable with a resin component of the resist. Particularly preferred photoresists of the invention can exhibit reduced leaching of resist materials into an immersion fluid contacting the resist layer during immersion lithography processing.
    Type: Grant
    Filed: September 3, 2012
    Date of Patent: October 28, 2014
    Assignee: Rohm and Haas Electronics Materials LLC
    Inventors: Deyan Wang, Cheng-Bai Xu, George G. Barclay
  • Patent number: 8865377
    Abstract: A method and system for fracturing or mask data preparation is disclosed in which the central core portion of a diagonal pattern is fractured using overlapping variable shaped beam (VSB) shots, and an outer portion of the diagonal pattern is fractured using non-overlapping VSB shots. A transition region is interposed between the central core and outer pattern portions, and transition region shots are generated so as to produce in the transferred pattern a smooth transition in pattern characteristics such as line edge roughness or period of waviness, from the central core portion of the pattern to the outer portion of the pattern. Methods for forming a semiconductor device layout pattern on a reticle or substrate are also disclosed.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: October 21, 2014
    Assignee: D2S, Inc.
    Inventors: Etienne Jacques, Jin Choi, Kazuyuki Hagiwara
  • Patent number: 8859195
    Abstract: A method of lithographically patterning a substrate that has photoresist having removal areas and non-removal areas includes first exposing at least the non-removal areas to radiation effective to increase outer surface roughness of the photoresist in the non-removal areas at least post-develop but ineffective to change photoresist solubility in a developer for the photoresist to be cleared from the non-removal areas upon develop with the developer. Second exposing of radiation to the removal areas is conducted to be effective to change photoresist solubility in the developer for the photoresist to be cleared from the removal areas upon develop with the developer. The photoresist is developed with the developer effective to clear photoresist from the removal areas and to leave photoresist in the non-removal areas that has outer surface roughness in the non-removal areas which is greater than that before the first exposing. Other implementations and embodiments are contemplated.
    Type: Grant
    Filed: October 24, 2012
    Date of Patent: October 14, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Yoshiki Hishiro, Scott Sills, Hiroyuki Mori, Troy Gugel, Paul D. Shirley, Lijing Gou, Adam Olson
  • Patent number: 8852830
    Abstract: A photomask for exposing a region on a substrate, with a mask pattern, including a first line pattern, a second line pattern, a first connection pattern for a peripheral portion of the region and a second connection pattern for the peripheral portion, wherein the first connection pattern is wider than the first line pattern and the second connection pattern is wider than the second line pattern, a distance from a virtual line between the first line pattern and the second line pattern to a center line of the first connection pattern is larger than a distance from the virtual line to a center line of the first line pattern and a distance from the virtual line to a center line of the second connection pattern is larger than a distance from the virtual line to a center line of the second line pattern.
    Type: Grant
    Filed: February 19, 2013
    Date of Patent: October 7, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventors: Satoshi Hirayama, Atsushi Kanome
  • Patent number: 8835082
    Abstract: The present disclosure provides a method for electron-beam (e-beam) lithography patterning. The method includes forming a resist layer on a substrate; performing a first e-beam exposure process to the resist layer according to a first pattern; performing a second e-beam exposure process to the resist layer according to a second pattern, wherein the second patterned is overlapped to the first pattern on the resist layer; and developing the resist layer.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: September 16, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Pei-Shiang Chen, Hung-Chun Wang, Jeng-Horng Chen
  • Patent number: 8835100
    Abstract: A method of manufacturing using a double patterning method is provided. The double patterning method uses a first developer and a second developer that are different. For example, the first developer may be a positive tone developer for a positive photoresist while the second developer may be a negative tone developer for the positive photoresist. Photoresists having a photoactive compound are also provided that may be useful in double patterning methods.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: September 16, 2014
    Assignee: Macronix International Co., Ltd.
    Inventor: Chin Cheng Yang
  • Patent number: 8835083
    Abstract: A manufacturing method of a photomask by which a resist pattern corresponding to a pattern with designed values can be formed, a method for optical proximity correction, and a manufacturing method of a semiconductor device are provided. Proximity design features that are close to each other and estimated to violate a mask rule check are extracted. In the proximity design features, correction prohibited regions where optical proximity correction is not carried out are set based on the distance between the features obtained from the extracted proximity design features and the resolution of an exposure device. Optical proximity correction is carried out on the proximity design features with the correction prohibited regions excluded to obtain corrected proximity patterns. A predetermined mask material is patterned by carrying out electron beam lithography based on the corrected proximity pattern data.
    Type: Grant
    Filed: October 2, 2013
    Date of Patent: September 16, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Ayumi Minamide, Akemi Moniwa, Akira Imai
  • Patent number: 8828650
    Abstract: A method for making a retarder includes: (a) forming a photocurable layer on a substrate, the photocurable layer including at least one photocurable prepolymer that has a plurality of reactive functional groups and a functional group equivalent weight ranging from 70 to 700 g/mol; (b) covering partially the photocurable layer using a patterned mask; (c) exposing the photocurable layer through the patterned mask; (d) removing the patterned mask; (e) exposing the photocurable layer to cure second regions of the photocurable layer so as to form a microstructure; (f) forming an alignment layer on the microstructure; (g) forming a liquid crystal layer on the alignment layer; and (h) curing the liquid crystal layer.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: September 9, 2014
    Assignee: Far Eastern New Century Corporation
    Inventors: Da-Ren Chiou, Wei-Che Hung, Chiu-Fang Chen, Yu-June Wu
  • Patent number: 8828632
    Abstract: A method for fabricating a semiconductor device is disclosed. An exemplary method includes receiving an integrated circuit (IC) layout design including a target pattern on a grid. The method further includes receiving a multiple-grid structure. The multiple-grid structure includes a number of exposure grid segments offset one from the other by an offset amount in a first direction. The method further includes performing a multiple-grid exposure to expose the target pattern on a substrate and thereby form a circuit feature pattern on the substrate. Performing the multiple-grid exposure includes scanning the substrate with the multiple-grid structure in a second direction such that a sub-pixel shift of the exposed target pattern occurs in the first direction, and using a delta time (?t) such that a sub-pixel shift of the exposed target pattern occurs in the second direction.
    Type: Grant
    Filed: September 4, 2013
    Date of Patent: September 9, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Chuan Wang, Shy-Jay Lin, Pei-Yi Liu, Jaw-Jung Shin, Burn Jeng Lin
  • Patent number: 8822139
    Abstract: A method for providing an ordered polymer layer at a surface of a substrate includes depositing a self-assemblable polymer layer directly onto a primer layer on a substrate to provide an interface between the self-assemblable polymer layer and the primer layer, and treating the self-assemblable polymer layer to provide self-assembly into an ordered polymer layer, such as a block copolymer, having first and second domain types at the interface. The primer layer is adapted to improve its chemical affinity to each domain type at the interface, in response to the presence of the respective domain type in the self-assembled polymer at the interface during the self-assembly of the self-assemblable polymer layer into the ordered polymer layer. This may lead to reduction in defect levels and/or improved persistence length for the ordered polymer layer. The method may be useful for forming resist layers for use in device lithography.
    Type: Grant
    Filed: January 19, 2011
    Date of Patent: September 2, 2014
    Assignee: ASML Netherlands B.V.
    Inventors: Emiel Peeters, Sander Frederik Wuister, Roelof Koole
  • Patent number: 8822107
    Abstract: The present disclosure provide one embodiment of a method of a lithography process for reducing a critical dimension (CD) by a factor n wherein n<1. The method includes providing a pattern generator having a first pixel area S1 to generate a data grid having a second pixel area S2 that is equal to n2*S1, wherein the pattern generator includes a multi-segment structure having multiple grid segments, wherein the grid segments includes a first set of grid segments and a second set of grid segments, each of the first set of grid segments being configured to have an offset in a first direction; and scanning the pattern generator in a second direction perpendicular to the first direction during the lithography process such that each of the second set of grid segments is controlled to have a time delay.
    Type: Grant
    Filed: January 30, 2013
    Date of Patent: September 2, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Chuan Wang, Shy-Jay Lin, Pei-Yi Liu, Jaw-Jung Shin, Burn Jeng Lin
  • Patent number: 8822106
    Abstract: The present disclosure provides an embodiment of a method, for a lithography process for reducing a critical dimension (CD) by a factor n wherein n<1. The method includes providing a pattern generator having a first pixel size S1 to generate an alternating data grid having a second pixel size S2 that is <S1, wherein the pattern generator includes multiple grid segments configured to offset from each other in a first direction; and scanning the pattern generator in a second direction perpendicular to the first direction during the lithography process such that each subsequent segment of the grid segments is controlled to have a time delay relative to a preceding segment of the grid segments.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: September 2, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Chuan Wang, Shy-Jay Lin, Pei-Yi Liu, Jaw-Jung Shin, Burn Jeng Lin
  • Patent number: 8815498
    Abstract: The present invention provides a method of forming tight-pitched patterns. First, a target pattern is provided, wherein the target pattern comprises a plurality of first stripe patterns, and each of the first stripe patterns has a first width and a first length. Then, a photomask comprising a plurality of second stripe patterns corresponding to the first stripe patterns is provided, and each of the second stripe patterns has a second width and a second length. Then, a first exposure process with the photomask is provided in an exposure system, wherein the first exposure process uses a first light source that can resolve the second width of each of the second stripe patterns. Lastly, a second exposure process with the photo-mask is provided in the exposure system, wherein the second exposure process uses a second light source that cannot resolve the second width of each of the second stripe patterns.
    Type: Grant
    Filed: August 22, 2012
    Date of Patent: August 26, 2014
    Assignee: Nanya Technology Corp.
    Inventor: Chun-Wei Wu
  • Patent number: 8815490
    Abstract: The radiation-sensitive resin composition includes a first polymer, a second polymer and a radiation sensitive acid generator. The first polymer includes a repeating unit represented by formula (1). The second polymer includes an acid labile group and is dissociated by an action of acid so that alkali solubility is given by dissociation of said acid labile group. R1 represents a hydrogen atom, a methyl group or a trifluoromethyl group. R2 represents a single bond or a divalent linear, branched or cyclic, saturated or unsaturated hydrocarbon group having 1-20 carbon atoms. X represents a fluorine atom-substituted methylene group or a linear or branched fluoroalkylene group having 2-20 carbon atoms. R3 represents a hydrogen atom or a monovalent organic group.
    Type: Grant
    Filed: December 2, 2011
    Date of Patent: August 26, 2014
    Assignee: JSR Corporation
    Inventors: Yasuhiko Matsuda, Tomohisa Fujisawa, Yukari Hama, Takanori Kawakami
  • Patent number: 8815473
    Abstract: Techniques for reducing the number of shots required by a radiation beam writing tool to write a pattern, such as fractured layout design, onto a substrate. One or more apertures are employed by a radiation beam writing tool to write a desired pattern onto a substrate using L-shaped images, T-shaped images, or some combination of both. By reducing the number of shots required to write a pattern onto a substrate, various implementations of the invention may reduce the write time and/or write complexity of the write process.
    Type: Grant
    Filed: October 12, 2010
    Date of Patent: August 26, 2014
    Inventors: Emile Y. Sahouria, Steffen F. Schulze
  • Patent number: 8802358
    Abstract: A method of forming an alignment film is provided. A photosensitive polymer material is provided, wherein the photosensitive polymer material defines a first pixel area and a second pixel area respectively defining a first sub-pixel area and the second sub-pixel area. In a first exposure, the photosensitive polymer material is irradiate by a first exposure light and a second exposure light to form a first alignment portion and a second alignment portion with different alignment directions in the first sub-pixel of the first pixel area and the second sub-pixel of the second pixel area respectively. In a second exposure, the photosensitive polymer material is irradiated with the first exposure light and the second exposure light to form a third alignment portion and a fourth alignment portion with different alignment directions in the first sub-pixel of the second pixel area and the second sub-pixel of the first pixel area respectively.
    Type: Grant
    Filed: November 6, 2012
    Date of Patent: August 12, 2014
    Assignees: Innocom Technology (Shenzhen) Co., Ltd., Innolux Corporation
    Inventors: Yao-Jen Ou, Han-Lang Lee, Chien-Chih Wang, Hung-I Tseng
  • Patent number: 8802360
    Abstract: In one example, a reticle disclosed herein includes a body having a center, an arrangement of a plurality of exposure patterns, wherein a center of the arrangement is offset from the center of the body, and at least one open feature defined on or through the body of the reticle. In another example, a method is disclosed that includes forming a layer of photoresist above a plurality of functional die and a plurality of incomplete die, exposing the photoresist material positioned above at least one of the functional die and/or at least one of the incomplete die, performing an incomplete die exposure processes via an open feature of the reticle to expose substantially all of the photoresist material positioned above the plurality of incomplete die, and developing the photoresist to remove the portions of the photoresist material positioned above the incomplete die.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: August 12, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Martin Mazur, Henke Dietmar, Hans-Juergen Thees