Radiation Mask Patents (Class 430/5)
  • Patent number: 10733354
    Abstract: Disclosed are embodiments of a system, method and computer program product for wafer-level design including chip and frame design. The embodiments employ three-dimensional (3D) emulation to preliminarily verify in-kerf optical macros included in a frame design layout. Specifically, 3D images of a given in-kerf optical macro at different process steps are generated by a 3D emulator and a determination is made as to whether or not that macro will be formed as predicted. If not, the plan for the macro is altered using an iterative design process. Once the in-kerf optical macros within the frame design layout have been preliminarily verified, wafer-level design layout verification, including chip and frame design layout verification, is performed. Once the wafer-level design layout has been verified, wafer-level design layout validation, including chip and frame design layout validation, is performed. Optionally, an emulation library can store results of 3D emulation processes for future use.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: August 4, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hojin Kim, Dongyue Yang, Dong-Ick Lee, Yue Zhou, Jae Ho Joung, Gregory Costrini, El Mehdi Bazizi, Dongsuk Park
  • Patent number: 10725454
    Abstract: Techniques for modifying a mask fabrication process based the identification of an abnormality in a pattern of a fabricated lithography mask are disclosed including comparing a fabricated lithography mask to a lithography mask design where the fabricated lithography mask is fabricated based at least in part on the lithography mask design using a mask fabrication process. An abnormality in a pattern of the fabricated lithography mask relative to a corresponding one of the plurality of patterns in the lithography mask design is identified based at least in part on the comparison of the fabricated lithography mask to the lithography mask design. A calibrated mask model is generated based at least in part on the identified abnormality in the pattern of the fabricated lithography mask and the mask fabrication process is modified based at least in part on the calibrated mask model.
    Type: Grant
    Filed: November 12, 2018
    Date of Patent: July 28, 2020
    Assignee: International Business Machines Corporation
    Inventors: Ravi K. Bonam, Nicole Saulnier, Michael Crouse, Derren N. Dunn
  • Patent number: 10719011
    Abstract: A method including: determining first error information based on a first measurement and/or simulation result pertaining to a first patterning device in a patterning system; determining second error information based on a second measurement and/or simulation result pertaining to a second patterning device in the patterning system; determining a difference between the first error information and the second error information; and creating modification information for the first patterning device and/or the second patterning device based on the difference between the first error information and the second error information, wherein the difference between the first error information and the second error information is reduced to within a certain range after the first patterning device and/or the second patterning device is modified according to the modification information.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: July 21, 2020
    Assignee: ASML Netherlands B.V.
    Inventors: Peter Ten Berge, Daan Maurits Slotboom, Richard Johannes Franciscus Van Haren, Peter Hanzen Wardenier
  • Patent number: 10719009
    Abstract: A photo mask includes a transparent substrate, a transflective member, and a light shielding member. The transparent substrate has a transflective region including a first region, a second region located in opposing lateral portions of the first region, and an edge region located adjacent to the first and second regions, and a light shielding region surrounding the transflective region. The transflective member is disposed in the first, second and edge regions under the transparent substrate, and has a different light transmittance in each of the first, second and edge regions. The light shielding member is disposed in the light shielding region under the transparent substrate, and defines an opening which exposes the transflective region. The light shielding member includes a long side extending in a first direction parallel to an upper surface of the transparent substrate and a short side extending in a second direction.
    Type: Grant
    Filed: November 8, 2018
    Date of Patent: July 21, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jun Chun, Junhong Park, Gwangmin Cha, Hoon Kang, Jeongmin Park
  • Patent number: 10719018
    Abstract: Embodiments described provide dynamic imaging systems that compensates for pattern defects resulting from distortion caused by warpage of the substrate. The methods and apparatus described are useful to create compensated exposure patterns. The dynamic imaging system includes an inspection system configured to provide 3D profile measurements and die shift measurements of the first substrate to the interface configured to provide compensated pattern data to the digital lithography system configured to receive the compensated pattern data from the interface and expose the photoresist with a compensated pattern.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: July 21, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Ching-Chang Chen, Chien-Hua Lai, Wei-Chung Chen, Shih-Hao Kuo, Hsiu-Jen Wang
  • Patent number: 10720419
    Abstract: A layout modification method for fabricating a semiconductor device is provided. Uniformity of critical dimensions of a first portion and a second portion in a patterned layer is calculated by using a layout for an exposure manufacturing process to produce the semiconductor device. The second portion is adjacent to the first portion, and a width of the second portion equals a penumbra size of the exposure manufacturing process. The penumbra size is utilized to indicate which area of the patterned layer is affected by light leakage exposure from another exposure manufacturing process. Non-uniformity between the first and second portions of the patterned layer is compensated according to the uniformity of critical dimensions to generate a modified layout.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: July 21, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hung-Wen Cho, Fu-Jye Liang, Chun-Kuang Chen, Chih-Tsung Shih, Li-Jui Chen, Po-Chung Cheng, Chin-Hsiang Lin
  • Patent number: 10719008
    Abstract: A phase-shift mask for extreme ultraviolet (EUV) lithography may be provided. The phase-shift mask may include a substrate, a reflection layer on the substrate, and phase-shift patterns including at least one metal nitride on the reflection layer. The at least one metal nitride may include at least one of TaN, TiN, ZrN, HfN, CrN, VN, NbN, MoN, WN, AlN, GaN, ScN, and YN.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: July 21, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hwanseok Seo, SeongSue Kim, Taehoon Lee, Roman Chalykh
  • Patent number: 10712651
    Abstract: A reticle used for collecting information for image-error compensation is provided. The reticle includes a first black border structure and a second black border structure formed over a substrate. The first and second black borders are concentric with a center of the substrate. The reticle further includes a first image structure and a second image structure formed over the substrate. The first and second image structures each has patterns representing features to be patterned on a semiconductor wafer. In a direction away from the center of the substrate, the second image structure, the second black border structure, the first image structure and the first black border structure are arranged in order.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: July 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hung-Wen Cho, Fu-Jye Liang, Chun-Kuang Chen, Chih-Tsung Shih, Li-Jui Chen, Po-Chung Cheng, Chin-Hsiang Lin
  • Patent number: 10712658
    Abstract: There is provided a method for procuring an agglutinant structure or in particular an agglutinant layer, from an agglutinant material, which is laid on an end face of a pellicle frame for gluing the pellicle to a photomask, wherein the agglutinant material is processed into the agglutinant layer passing through one more stages wherein the material is under a helium gas atmosphere; the invention is also about a manufacturing method of a pellicle wherein the agglutinant layer is procured in the above described manner.
    Type: Grant
    Filed: January 24, 2018
    Date of Patent: July 14, 2020
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Yuichi Hamada, Yu Yanase
  • Patent number: 10712657
    Abstract: A method for manufacturing a membrane assembly for EUV lithography, the method including: providing a stack having a planar substrate and at least one membrane layer, wherein the planar substrate includes an inner region and a border region around the inner region; and selectively removing the inner region of the planar substrate. The membrane assembly includes: a membrane formed from the at least one membrane layer; and a border holding the membrane, the border formed from the border region of the planar substrate. The stack is provided with a mechanical protection material configured to mechanically protect the border region during the selectively removing the inner region of the planar substrate.
    Type: Grant
    Filed: July 4, 2016
    Date of Patent: July 14, 2020
    Assignee: ASML Netherlands B.V.
    Inventors: Johan Hendrik Klootwijk, Wilhelmus Theodorus Anthonius Johannes Van Den Einden
  • Patent number: 10712653
    Abstract: A method to improve a lithographic process for imaging a portion of a design layout onto a substrate using a lithographic projection apparatus and for transferring the imaged portion of the design layout to the substrate by an etching process, which method includes: determining a value of at least one evaluation point of the lithographic process for each of a plurality of variations of the etching process; computing a multi-variable cost function of a plurality of design variables that are characteristics of the lithographic process, wherein the multi-variable cost function is a function of deviation from the determined values of the at least one evaluation point; and reconfiguring the characteristics of the lithographic process by adjusting the design variables until a termination condition is satisfied. This method may reduce the need of repeated adjustment to the lithographic process when the etching process varies.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: July 14, 2020
    Assignee: ASML Netherlands B.V.
    Inventor: Xiaofeng Liu
  • Patent number: 10712652
    Abstract: A mask blank having a resist layer, which enables charge-up to be suppressed during electron beam irradiation. The mask blank having a resist layer includes a substrate having a thin film, a resist layer formed on a surface of the thin film, and a conductive layer formed on the resist layer. The conductive layer includes a first metal layer containing aluminum as a main component thereof and a second metal layer made of a metal other than aluminum. The first metal layer is formed on the resist layer side of the second metal layer.
    Type: Grant
    Filed: November 7, 2016
    Date of Patent: July 14, 2020
    Assignee: HOYA CORPORATION
    Inventors: Takahiro Hiromatsu, Hiroaki Shishido, Seishi Shibayama
  • Patent number: 10712654
    Abstract: A photomask blank has on a transparent substrate, an optional first film, a second film, a third film, and a fourth film. The first and third films are formed of silicon-containing materials which are resistant to chlorine base dry etching and removable by fluorine base dry etching. The second and fourth films are formed of chromium-containing materials which are resistant to fluorine base dry etching and removable by chlorine base dry etching. An etching clear time of the fourth film is longer than an etching clear time of the second film, on chlorine base dry etching.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: July 14, 2020
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Souichi Fukaya, Yukio Inazuki
  • Patent number: 10712655
    Abstract: This mask blank is provided with a light blocking film on a light transmitting substrate. The light blocking film has an optical density of 2.5 or more with respect to ArF excimer laser exposure light, and has a structure that comprises three or more multilayer structures, each of which is composed of a high nitride layer and a low nitride layer. The high nitride layer and the low nitride layer are formed from a material that is composed of silicon and nitrogen or a material that contains one or more elements selected from among semimetal elements and non-metal elements in addition to silicon and nitrogen. The high nitride layer has a nitrogen content of 50 atom % or more, and has a thickness of 10 nm or more. The low nitride layer has a nitrogen content of less than 50 atom %, and has a thickness that is not less than twice the thickness of the high nitride layer.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: July 14, 2020
    Assignee: HOYA CORPORATION
    Inventors: Hiroaki Shishido, Yasutaka Horigome
  • Patent number: 10712656
    Abstract: A method for manufacturing a membrane assembly for EUV lithography, the method comprising: providing a stack comprising a planar substrate and at least one membrane layer, wherein the planar substrate comprises an inner region and a border region around the inner region; positioning the stack on a support such that the inner region of the planar substrate is exposed; and selectively removing the inner region of the planar substrate using a non-liquid etchant, such that the membrane assembly comprises: a membrane formed from the at least one membrane layer; and a border holding the membrane, the border formed from the border region of the planar substrate.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: July 14, 2020
    Assignee: ASML Netherlands B.V.
    Inventors: Zomer Silvester Houweling, Eric Willem Felix Casimiri, Tamara Druzhinina, Paul Janssen, Michael Alfred Josephus Kuijken, Martinus Hendrikus Antonius Leenders, Sicco Oosterhoff, Mária Péter, Willem Joan Van Der Zande, Pieter-Jan Van Zwol, Beatrijs Louise Marie-Joseph Katrien Verbrugge, Johannes Petrus Martinus Bernardus Vermeulen, David Ferdinand Vles, Willem-Pieter Voorthuijzen
  • Patent number: 10698312
    Abstract: A membrane transmissive to EUV radiation, which may be used as a pellicle or spectral filter in a lithographic apparatus. The membrane has one or more high doped regions wherein the membrane is doped with a dopant concentration greater than 1017 cm?3, and one or more regions with low (or no) doping. The membrane may have a main substrate having low doping and one or more additional layers, wherein the high doped regions are within some or all of the additional layers.
    Type: Grant
    Filed: January 14, 2019
    Date of Patent: June 30, 2020
    Assignee: ASML Netherlands B.V.
    Inventors: Pieter-Jan Van Zwol, Vadim Yevgenyevich Banine, Jozef Petrus Henricus Benschop, Florian Didier Albin Dhalluin, Mária Péter, Luigi Scaccabarozzi, Willem Joan Van Der Zande
  • Patent number: 10695976
    Abstract: A multiple light source correction apparatus and a method of use thereof are disclosed. The multiple light source correction apparatus (10) comprises a transparent thin plate (1) having a first correction pattern (12), a second correction pattern (13) and at least one third correction pattern (14). The first correction pattern (12) includes a first straight line (121) having first and second end points (1211, 1212). The second correction pattern (13) includes a second straight line (131) and two U-shaped frames (132). The second straight line (131) includes third and fourth end points (1311, 1312). The two U-shaped frame (132) is installed at externals of the third and fourth end points (1311, 1312) respectively. The third correction pattern (14) includes a third straight line (141) having fifth and sixth end points (1411, 1412). The first, second and third straight lines (121, 131, 141) are arranged parallel to each other.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: June 30, 2020
    Assignees: XYZPRINTING, INC., KINPO ELECTRONICS, INC.
    Inventors: Tsung-Hua Kuo, Ming-Hsiung Ding, Chung-Yen Gir
  • Patent number: 10698311
    Abstract: A reflection-type exposure mask includes a light reflector provided in a pattern on a substrate. The light reflector has a multilayer structure including first-type layers and second-type layers that are alternately stacked. The second-type layers have a refractive index higher at an extreme ultraviolet wavelength than a refractive index of the first-type layer at the extreme ultraviolet wavelength. A light transmitting medium is on a side surface of the light reflector.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: June 30, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takeshi Yamane, Kosuke Takai
  • Patent number: 10691017
    Abstract: Pellicle-mask systems for advanced lithography, such as extreme ultraviolet lithography, are disclosed herein. An exemplary pellicle-mask system includes a mask having an integrated circuit (IC) pattern, a pellicle membrane, and a pellicle frame. The pellicle frame has a first surface attached to the pellicle membrane and a second surface opposite the first surface attached to the mask, such that the IC pattern of the mask is positioned within an enclosed space defined by the mask, the pellicle membrane, and the pellicle frame. A void is defined between the pellicle frame and the mask, where the void is defined by a portion of the second surface of the pellicle membrane not attached to the mask. The void is not in communication with the enclosed space and is not in communication with an exterior space of the pellicle-mask system.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: June 23, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Ching Lee, Ching-Fang Yu, Chun-Hung Lin, Ting-Hao Hsu, Ching-Hsiang Chang, Sheng-Chi Chin
  • Patent number: 10684545
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a material layer over a substrate and forming a assist layer over the material layer. The assist layer includes a polymer backbone, an acid labile group (ALG) bonded to the polymer backbone, and a floating group bonded to the polymer backbone. The floating group includes carbon fluoride (CxFy). The method also includes forming a resist layer over the assist layer and patterning the resist layer.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: June 16, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: An-Ren Zi, Ching-Yu Chang, Chin-Hsiang Lin
  • Patent number: 10685833
    Abstract: Example embodiments relate to selective deposition of metal-organic frameworks. One embodiment includes a method of forming a low-k dielectric film selectively on exposed dielectric locations in a substrate. The method includes selectively depositing a metal-containing film, using an area-selective deposition process, on the exposed dielectric locations using one or more deposition cycles. The method also includes providing, at least once, a vapor of at least one organic ligand to the deposited metal-containing film resulting in a gas-phase chemical reaction thereby obtaining a metal-organic framework which is the low-k dielectric film. The low-k dielectric film has gaps on locations where no metal-containing film was deposited.
    Type: Grant
    Filed: November 14, 2018
    Date of Patent: June 16, 2020
    Assignees: IMEC VZW, Katholieke Universiteit Leuven, KU LEUVEN R&D
    Inventors: Mikhail Krishtab, Silvia Armini, Ivo Stassen, Rob Ameloot
  • Patent number: 10678128
    Abstract: This application relates to a photo-mask and a method for manufacturing an active switch array substrate of the photo-mask. The photo-mask includes a transparent region, a light shielding region, and a semi-transparent region disposed between the transparent region and the light shielding region. A transmittance of the photo-mask is adjusted according to a doping amount and a distribution density of a low reflective material, so as to enable a transmittance of the semi-transparent region to be less than a transmittance of the transparent region and to be greater than a transmittance of the light shielding region.
    Type: Grant
    Filed: May 17, 2017
    Date of Patent: June 9, 2020
    Assignees: HKC CORPORATION LIMITED, CHONGQING HKC OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Yu-Jen Chen
  • Patent number: 10678126
    Abstract: A mask for semiconductor manufacturing includes a mask substrate, a shifter layer over the mask substrate, a stop layer over and in contact with the shifter layer, and an absorber layer over the stop layer. The shifter layer includes each material of a set of materials, the materials being combined in a first proportion in the shifter layer. The stop layer includes each material of the set of materials, the materials being combined in a second proportion in the stop layer that is different from the first proportion.
    Type: Grant
    Filed: April 18, 2018
    Date of Patent: June 9, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Chiang Tu, Chun-Lang Chen, Boming Hsu, Tran-Hui Shen
  • Patent number: 10672611
    Abstract: A method for manufacturing a semiconductor device includes forming one or more memory device layers over a contact structure. In the method, a plurality of hardmask layers are deposited on the one or more memory device layers in a stacked configuration. Alternating hardmask layers of the stacked configuration are different from each other in at least one respect. The method further includes patterning the plurality of hardmask layers and the one or more memory device layers into a pillar over the contact structure.
    Type: Grant
    Filed: October 19, 2018
    Date of Patent: June 2, 2020
    Assignee: International Business Machines Corporation
    Inventors: Michael Rizzolo, Ashim Dutta, Oscar van der Straten, Chih-Chao Yang
  • Patent number: 10670924
    Abstract: In an alignment regulating layer, a plurality of regulation regions is defined in plan view perpendicular to the surface of the alignment regulating layer, and the plurality of regulation regions includes at least one first regulation region, at least one second regulation region, and a third regulation region fitted between the first regulation region and the second regulation region. The alignment regulating direction in the first regulation region is a first regulating direction, and the alignment regulating direction in the second regulation region is a second regulating direction that is different from the first regulating direction. In the third regulation region, the alignment regulating direction continuously changes from the first regulating direction to the second regulating direction from a portion contacting the first regulation region toward a portion contacting the second regulation region.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: June 2, 2020
    Assignee: TOPPAN PRINTING CO., LTD.
    Inventor: Masami Inokuchi
  • Patent number: 10670955
    Abstract: A method of correcting a critical dimension (CD) variation in extreme ultraviolet (EUV) photolithography includes mapping the CD variation of a wafer exposure field formed by a photolithography system that includes an EUV photolithography photomask. Parameters of a treatment to produce a change in reflectance at a working wavelength of EUV radiation in a region of a reflective multilayer of the photomask are determined, the change in reflectance being calculated to correct the mapped CD variation. A treatment beam is directed to the region. The region is treated with the beam in accordance with the determined parameters.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: June 2, 2020
    Assignee: CARL ZEISS SMT GMBH
    Inventors: Sergey Oshemkov, Vladimir Kruglyakov, Frederik Blumrich, Yuval Perets
  • Patent number: 10670956
    Abstract: Some embodiments pertain to a photomask for mask patterning. The photomask includes a phase shift layer overlying a transparent layer, a first shielding layer overlying the phase shift layer, and a second shielding layer overlying the first shielding layer. The first shielding layer has a first optical density, and the second shielding layer has a second optical density. The second optical density is less than the first optical density.
    Type: Grant
    Filed: October 8, 2018
    Date of Patent: June 2, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Chiang Tu, Chun-Lang Chen
  • Patent number: 10670958
    Abstract: A method of forming a layout pattern is disclosed. First, an array comprising a plurality of main features is provided wherein the main features are arranged into a plurality of rows along a first direction and are parallel and staggered along a second direction. Assistant features are inserted into each row of the main features. A shortest distance d1 between the main features in row n to the main features in row n+1 and a shortest distance d2 between the main feature in row n?1 to the main feature in row n+1 are obtained. The assistance features inserted in row n of the main features are then adjusted according to the difference between the distances d1 and d2. After that, the main features and the assistant features are output to a photo mask.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: June 2, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Ying-Chiao Wang, Yu-Cheng Tung, Li-Wei Feng, Chien-Ting Ho
  • Patent number: 10670957
    Abstract: During reactive sputtering using a silicon-containing target, an inert gas, and a nitrogen-containing reactive gas, a hysteresis curve is drawn by sweeping the flow rate of the reactive gas, and plotting the sputtering voltage or current during the sweep versus the flow rate of the reactive gas. In the step of sputtering in a region corresponding to a range from more than the lower limit of reactive gas flow rate providing the hysteresis to less than the upper limit, the target power, the inert gas flow rate and/or the reactive gas flow rate is increased or decreased continuously or stepwise. The halftone phase shift film including a layer containing transition metal, silicon and nitrogen is improved in in-plane uniformity of optical properties.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: June 2, 2020
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Takuro Kosaka, Yukio Inazuki, Hideo Kaneko
  • Patent number: 10671793
    Abstract: The present embodiments relate to providing an overlap view of external and internal components of all instance circuit cells related to a master circuit cell in a same layout view. A layout of a circuit having a plurality of instance circuit cells of a master circuit cell is provided. Further, a graphical user interface including a user selectable option for an overlay view is provided. In addition, responsive to the selection of the overlay view, the plurality of instance circuit cells of the master circuit cell is determined. In addition, a plurality of sets of circuit elements, each set of circuit elements including external circuit elements that overlap with a corresponding instance circuit cell of the plurality of instance circuit cells is determined. Further, the plurality of sets of circuit elements overlaid on the master circuit cell is displayed on the layout view.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: June 2, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventors: Devendra Deshpande, Gerard Tarroux, Chun-Wen Chiang, Sheng-Wei Lin, Vandana Gupta
  • Patent number: 10663853
    Abstract: An extreme ultraviolet (EUV) mask includes: a substrate having a first region and a second region; a reflective layer on the substrate; an absorbing layer on the reflective layer; and a first recess in the absorbing layer and in part of the reflective layer on the first region. Preferably, a bottom surface of the first recess exposes a top surface of the reflective layer.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: May 26, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: En-Chiuan Liou, Yu-Cheng Tung
  • Patent number: 10663855
    Abstract: The present disclosure relates to a photoetching parameter adjustment method, apparatus and mask plate, in the field of photoetching technology. The method comprises: forming a photoresist pattern on a first substrate by a photoetching process, wherein the photoresist pattern comprises a photoetching detection pattern; judging whether photoetching parameters of the photoetching process need to be adjusted or not in accordance with the photoetching detection pattern; and adjusting the photoetching parameters when the photoetching parameters need to be adjusted. The present disclosure solves the problem that the reliability of the photoetching parameters is low and improves the reliability of the photoetching parameters. The present disclosure is used for adjusting photoetching parameters.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: May 26, 2020
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Wusheng Li, Zhanfeng Cao
  • Patent number: 10663856
    Abstract: An optical mask for use in a photolithography process, a method for fabricating the optical mask, and a method for fabricating an array of patterns on a substrate using the optical mask, wherein the optical mask includes an array of microstructures disposed on a mask substrate, and wherein the array of microstructures is arranged to transform a uniform optical exposure passing therethrough to an array of optical exposure patterns.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: May 26, 2020
    Assignee: City University of Hong Kong
    Inventors: Johnny Chung Yin Ho, Ming Fang, Lei Shu
  • Patent number: 10656516
    Abstract: A photomask blank including a transparent substrate, and at least one film (A) containing chromium and free of silicon and at least one film (B) containing silicon, and oxygen or oxygen and nitrogen, and free of a transition metal that are contacted to each other In the blank, when an intension of secondary ions is measured along a thickness direction of the films by a time-of-flight secondary ion mass spectrometry (TOF-SIMS), an intension of secondary ions derived from Cr2O5 is lower than an intension of secondary ions derived from Cr, at a position located at the interface or its vicinity of the film (A) and film (B) and having a maximum intensity of secondary ions derived from SiCrO5.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: May 19, 2020
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Takuro Kosaka, Yukio Inazuki
  • Patent number: 10657213
    Abstract: Methods for reticle enhancement technology (RET) include representing a target wafer pattern or a predicted wafer pattern as a smooth function captured as a function sample array, which is an array of function values. A continuous tone mask (CTM) is provided, where the CTM is used to produce the predicted wafer pattern. Methods for RET also include inputting a target wafer pattern, where the target wafer pattern spans an entire design area. The entire design area is divided into a plurality of tiles, each tile having a halo region surrounding the tile. A proposed mask for the entire design area is iterated until the proposed mask meets criteria towards producing the target wafer pattern. Each iteration includes calculating a predicted wafer pattern for a subset of the plurality of tiles; and updating the proposed mask for that tile; where all tiles in the subset are calculated before the next iteration.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: May 19, 2020
    Assignee: D2S, Inc.
    Inventor: P. Jeffrey Ungar
  • Patent number: 10649326
    Abstract: There is provided a pellicle frame and a pellicle using the frame, which has a hollow space inside a corner portion of the frame and optionally one or more hollow spaces in a straight portion (bar) of the frame, and also a hollow space in a corner portion of the frame may communicate with a neighboring hollow space in a straight portion of the frame.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: May 12, 2020
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventor: Akinori Nishimura
  • Patent number: 10642148
    Abstract: The present disclosure provides an embodiment of a reflective mask that includes a substrate; a reflective multilayer disposed on the substrate; an anti-oxidation barrier layer disposed on the reflective multilayer and the anti-oxidation barrier layer is in amorphous structure with an average interatomic distance less than an oxygen diameter; and an absorber layer disposed on the anti-oxidation barrier layer and patterned according to an integrated circuit layout.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: May 5, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Hao Yu, Chi-Lun Lu, Chih-Tsung Shih, Ching-Wei Shen, Jeng-Horng Chen
  • Patent number: 10642149
    Abstract: A reflective mask blank capable of obtaining high contrast at the edges of a phase shift film pattern. Provided is a reflective mask blank comprising a multilayer reflective film and a phase shift film that shifts the phase of EUV light formed in that order on a substrate, wherein root mean square roughness (Rms), obtained by measuring a 1 ?m×1 ?m region on the surface of the phase shift film with an atomic force microscope, is not more than 0.50 nm, and power spectrum density at a spatial frequency of 10 to 100 ?m?1 is not more than 17 nm4.
    Type: Grant
    Filed: July 5, 2019
    Date of Patent: May 5, 2020
    Assignee: HOYA CORPORATION
    Inventors: Kazuhiro Hamamoto, Yohei Ikebe
  • Patent number: 10643845
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to cut margin structures and methods of manufacture. The method includes: forming a plurality of patterned hardmask stacks containing at least a semiconductor layer and a capping layer; removing a portion of a first patterned hardmask stack and a margin of an adjacent hardmask stack of the plurality of the patterned hardmask stacks; and selectively growing material on the margin of the adjacent hardmask stack.
    Type: Grant
    Filed: January 2, 2018
    Date of Patent: May 5, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Xunyuan Zhang, Ruilong Xie, Yi Qi
  • Patent number: 10642150
    Abstract: The present invention relates to a photomask and a method for manufacturing a column spacer for a color filter using the same, and according to one aspect of the present invention, a photomask is provided, which comprises a central region having a first transmittance, a first perimeter region surrounding the central region and having a second transmittance lower than the first transmittance, and a second perimeter region surrounding the first perimeter region and having the first transmittance.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: May 5, 2020
    Assignee: LG CHEM, LTD.
    Inventors: Dae Han Seo, Dong Chang Choi, Kwang Han Park, Sang Choll Han, Jae Jin Kim, Eun Joo Choi, Min Soo Song
  • Patent number: 10634990
    Abstract: The present invention provides a halftone mask comprising an assist pattern and a manufacturing method of the halftone mask, which uses an ArF excimer laser as an exposing source, is used for a projection exposure by an off axis illumination, does not resolve the as pattern while keeping the focal depth magnification effect as the assist pattern, and may form a transferred image having high contrast of a main pattern.
    Type: Grant
    Filed: July 11, 2019
    Date of Patent: April 28, 2020
    Assignee: DAI NIPPON PRINTING CO., LTD.
    Inventors: Takaharu Nagai, Hiroshi Mohri, Yasutaka Morikawa, Katsuya Hayano
  • Patent number: 10627722
    Abstract: Provided is a process including: obtaining a layout specifying, at least in part, a pattern to be transferred to a substrate via a patterning process and an etch process; and modifying, with one or more processors, the layout to include an etch-assist feature that is larger than a resolution limit of the patterning process and smaller than a resolution limit of the etch process, the etch-assist feature being configured to reduce a bias of the patterning process or the etch process, to reduce an etch induced shift of a feature in the layout due to the etch process, or to expand a process window of another patterning process.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: April 21, 2020
    Assignee: ASML NETHERLANDS B.V.
    Inventors: Wim Tjibbo Tel, Thomas I. Wallow
  • Patent number: 10629855
    Abstract: A display device including a substrate in which at least one hole area is disposed. The substrate includes an active area. The display device also includes a thin film encapsulation (TFE) layer disposed on the substrate. A pixel including a plurality of sub-pixels is disposed on the active area. A plurality of first and second pixel groups each include the sub-pixels. The first and second pixel groups are disposed along a plurality of first and second lines of the active area, respectively. The first and second lines are alternated in the active area. A first deposition portion forming the common layer or the common electrode is disposed in the first pixel groups disposed along the first lines of the active area. A second deposition portion forming the common layer or the common electrode is disposed in the second pixel groups disposed along the second lines of the active area.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: April 21, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Euigyu Kim, Dahee Jeong
  • Patent number: 10627729
    Abstract: A first substrate (2002) has a calibration pattern applied to a first plurality of fields (2004) by a lithographic apparatus. Further substrates (2006, 2010) have calibration patterns applied to further pluralities of fields (2008, 2012). The different pluralities of fields have different sizes and/or shapes and/or positions. Calibration measurements are performed on the patterned substrates (2002, 2006, 2010) and used to obtain corrections for use in controlling the apparatus when applying product patterns to subsequent substrates. Measurement data representing the performance of the apparatus on fields of two or more different dimensions (2004, 2008, 2012) is gathered together in a database (2013) and used to synthesize the information needed to calibrate the apparatus for a new size. Calibration data is also obtained for different scan and step directions.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: April 21, 2020
    Assignee: ASML Netherlands B.V.
    Inventors: Emil Peter Schmitt-Weaver, Jens Stäcker, Koenraad Remi André Maria Schreel, Roy Werkman
  • Patent number: 10627971
    Abstract: The problem addressed lies in providing a conductive film, a touch panel and a display device which make it possible to suppress a deterioration in the quality of images observed on the display device. In a power spectrum obtained by means of a two-dimensional Fourier transform of each of an electrode wire pattern formed from electrode wires which bend irregularly and a reference pattern formed by regular bent lines, a value obtained by dividing, at predetermined frequency widths, the cumulative value of spectral intensity of each frequency width by the frequency width is a spectral density, and a first evaluation value, which is a common logarithm of a value obtained by dividing the cumulative value of the spectral density in a defined frequency region of the electrode wire pattern by the cumulative value of the spectral density in a defined frequency region of the reference pattern, is 3.6 or less.
    Type: Grant
    Filed: October 19, 2018
    Date of Patent: April 21, 2020
    Assignee: VTS-Touchsensor Co., Ltd.
    Inventors: Yumi Takizawa, Tomohiro Nakagome
  • Patent number: 10620530
    Abstract: Examples of a multiple-mask multiple-exposure lithographic technique and suitable masks are provided herein. In some examples, a photomask includes a die area and a stitching region disposed adjacent to the die area and along a boundary of the photomask. The stitching region includes a mask feature for forming an integrated circuit feature and an alignment mark for in-chip overlay measurement.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: April 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Peter Yu, Chih-Tung Hsu, Kevin Wang, Chih-Chia Hu, Roger Chen
  • Patent number: 10620527
    Abstract: Disclosed is a mask blank substrate for use in lithography, wherein a main surface of the substrate satisfies a relational equation of (BA70?BA30)/(BD70?BD30)?350(%/nm), and has a maximum height (Rmax)?1.2 nm in a relation between a bearing area (%) and a bearing depth (nm) obtained by measuring, with an atomic force microscope, an area of 1 ?m×1 ?m in the main surface on the side of the substrate where a transfer pattern is formed, wherein BA30 is defined as a bearing area of 30%, BA70 is defined as a bearing area of 70%, and BD70 and BD30 are defined to respectively represent bearing depths for the bearing area of 30% and the bearing area of 70%.
    Type: Grant
    Filed: August 9, 2019
    Date of Patent: April 14, 2020
    Assignee: HOYA CORPORATION
    Inventors: Kazuhiro Hamamoto, Toshihiko Orihara, Hirofumi Kozakai, Youichi Usui, Tsutomu Shoki, Junichi Horikawa
  • Patent number: 10620526
    Abstract: A mask, a manufacturing method thereof, and a patterning method employing the mask. In the mask, a plurality of masks can be combined into one mask. The pattern area (01) of the mask is provided with a first pattern section (10) and a second pattern section (20) which are not overlapped with each other; light of a first wavelength can run through the first pattern section (10) but light of a second wavelength cannot run through the first pattern section; the light of the second wavelength can run thorough the second pattern section (20) but the light of the first wavelength cannot run through the second pattern section; and the light of the first wavelength and the light of the second wavelength can run through the non-pattern area, or any of the light of the first wavelength and the light of the second wavelength cannot run through the non-pattern area. The mask is obtained by combining a plurality of masks.
    Type: Grant
    Filed: July 8, 2016
    Date of Patent: April 14, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Zhichao Zhang, Tsung Chieh Kuo, Zheng Liu, Shoukun Wang
  • Patent number: 10606166
    Abstract: A substrate with an electrically conductive film for fabricating a reflective mask is obtained that is capable of preventing positional shift of the reflective mask during pattern transfer. Provided is a substrate with an electrically conductive film used in lithography, the substrate with an electrically conductive film having an electrically conductive film formed on one of the main surfaces of a mask blank substrate, and a coefficient of static friction of the surface of the electrically conductive film is not less than 0.25.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: March 31, 2020
    Assignee: HOYA CORPORATION
    Inventors: Takumi Kobayashi, Kazuhiro Hamamoto, Tatsuo Asakawa, Tsutomu Shoki
  • Patent number: 10606168
    Abstract: Embodiments of the present disclosure relate to a mask, a masking exposure method, a mask system and a pattern control device. The mask according to embodiments of the present disclosure includes a pattern control layer and a light conversion layer. The pattern control layer includes a plurality of light-transmission units and a control circuit connected to each of the light-transmission units. The control circuit is configured to control conversion of each of the light-transmission units between in a light-transmission state and in a light-tight state, such that different mask patterns are formed. The light conversion layer is provided on a light-outgoing directional side or a light-incoming directional side of the pattern control layer and is configured to convert incoming light into parallel light so as to emit the parallel light.
    Type: Grant
    Filed: May 6, 2016
    Date of Patent: March 31, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Wei Wang, Zhongyuan Sun