Radiation Mask Patents (Class 430/5)
  • Patent number: 9817309
    Abstract: Provided are photomasks, methods of fabricating the photomasks, and methods of fabricating a semiconductor device by using the photomasks, in which a critical dimension (CD) of a pattern of a specific region of the photomask is corrected to improve the distribution of CDs of the pattern formed on a wafer. The photomasks may include a substrate and a light-blocking pattern formed on the substrate that includes an absorber layer and an anti-reflection coating (ARC) layer. The light-blocking pattern may include at least one of a first corrected area in which a top surface of the absorber layer is exposed, and a second corrected area in which a correction layer is formed on the ARC layer.
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: November 14, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung-hwan Lee, Byung-gook Kim, Sang-hyeon Lee
  • Patent number: 9810978
    Abstract: A EUV mask comprises a low thermal expansion material (LTEM) substrate, a reflective multi-layer (ML) over the LTEM substrate, and a patterned absorber layer over the reflective ML. The reflective ML includes a defect. The EUV mask further comprises a mark associated with the defect. The mark is one of: a deposit over the patterned absorber layer at a distance offset from the defect, and a cavity into the patterned absorber layer in an area over the defect.
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: November 7, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsun-Chuan Shih, Yuan-Chih Chu
  • Patent number: 9811619
    Abstract: A specialized low drop-out voltage regulator (LDO) computer system stores a generalized base model of an LDO. The base model includes values representing a circuit topology and a set of analog behavior blocks associated with the generalized LDO. Values of a set of operational parameters associated with a specific model of LDO are input to the specialized LDO computer system from a data sheet associated with the specific model of LDO. The specialized LDO computer system transforms the set of operational parameters into a computer model of the specific LDO. The LDO-specific computer model is output as a netlist or as a set of instantiation control values to control external hardware such as an integrated circuit die tooling system or a computer graphical display system.
    Type: Grant
    Filed: September 13, 2014
    Date of Patent: November 7, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Robert Nichols Atwell, Britt Eric Brooks
  • Patent number: 9806109
    Abstract: The present disclosure provides a half tone mask plate used to manufacture an active layer pattern as well as a source electrode pattern, a drain electrode pattern and a data line pattern located on the active layer pattern included in the array substrate. A surface of the array substrate includes a first region corresponding to the source electrode pattern, the drain electrode pattern and the data line pattern, a second region corresponding to a region of the active layer pattern located between the source electrode pattern and the drain electrode pattern, as well as a third region in addition to the first region and the second region; the half tone mask plate includes a semi-transparent region corresponding to the second region and a partial region of the third region.
    Type: Grant
    Filed: September 19, 2014
    Date of Patent: October 31, 2017
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Tiansheng Li, Zhenyu Xie
  • Patent number: 9804339
    Abstract: An optical connector for coupling to a counter-connector mechanically and optically, a portion of an optical transmission line transmitting an optical signal being disposed in the optical connector, includes: a first outer case through which the optical transmission line is inserted and that covers an incidence end or an emitting end of an optical signal through the optical transmission line; a cover plate that is permeable to an optical signal and seals a tip end side coupled to the counter-connector in the first outer case; and a coating film made of amorphous carbon that is disposed on a surface on the tip end side of the cover plate.
    Type: Grant
    Filed: June 5, 2015
    Date of Patent: October 31, 2017
    Assignee: Sony Olympus Medical Solutions Inc.
    Inventor: Morinao Fukuoka
  • Patent number: 9804492
    Abstract: A method for forming multi-layer film on substrate, which includes steps (1) forming under layer film on substrate by applying under layer film material containing resin having repeating unit represented by the general formula (1) or (2) in which fluorene structure is contained, and curing the same by heat treatment, (2) forming metal oxide film on the under layer film by applying metal oxide film material selected from titanium oxide film material, zirconium oxide film material, and hafnium oxide film material, (3) forming hydrocarbon film on metal oxide film by applying hydrocarbon film material, and (4) forming silicon oxide film on the hydrocarbon film by applying silicon oxide film material. There can be provided a method for forming multi-layer film that can reduce reflectance, and useful for a patterning process with high dimensional accuracy of dry etching.
    Type: Grant
    Filed: September 17, 2015
    Date of Patent: October 31, 2017
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Jun Hatakeyama, Tsutomu Ogihara
  • Patent number: 9805154
    Abstract: The present disclosure provides one embodiment of an IC method that includes receiving an IC design layout including a first main feature and inserting a first plurality of scattering bars in the IC design layout to form a first circular pattern of scattering bars around the first main feature. The first main feature is positioned at a center portion of the first circular pattern of scattering bars.
    Type: Grant
    Filed: May 15, 2015
    Date of Patent: October 31, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Irene Ho, Ai-Jen Hung, Hung-Chang Hsieh, Kuei-Liang Lu, Ya Hui Chang
  • Patent number: 9798230
    Abstract: A photomask blank includes a chromium-based material film as a hard mask film containing at least one selected from the group consisting of nitrogen, oxygen, carbon and hydrogen, wherein a ratio (A/B) of etching rates per unit film thickness is in a range from 0.7 to 0.9, and the chromium-based material film has a tensile stress or compressive stress corresponding to an amount of warp of up to 70 nm. The present invention provides a photomask blank having a thin film of chromium-based material which is enhanced in etch resistance and lowered in film stress. This enables high-accuracy patterning of a chromium-based material film.
    Type: Grant
    Filed: September 11, 2015
    Date of Patent: October 24, 2017
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Souichi Fukaya, Kouhei Sasamoto
  • Patent number: 9798225
    Abstract: A method of characterizing a lithographic mask type uses a mask having thereon test pattern units of linear features at different orientations. The mask is exposed, rotated by angle, exposed again, rotated by a further angle, exposed, etc. The printed features are measured to determine one or more characteristics of the mask. The method can be used to model shadowing effects of a EUV mask with a thick absorber illuminated at an angle.
    Type: Grant
    Filed: October 14, 2014
    Date of Patent: October 24, 2017
    Assignee: ASML NETHERLANDS B.V.
    Inventors: Eelco Van Setten, Natalia Viktorovna Davydova, Eleni Psara, Anton Bernhard Van Oosten
  • Patent number: 9798229
    Abstract: A method for designing a photomask blank comprising a transparent substrate and an optical film thereon is provided. The photomask blank is processed into a transmissive photomask having a pattern of optical film such that the film pattern may be transferred when exposure light is transmitted by the photomask. The optical film is selected using a specific reflectance, which is equal to the reflectance divided by the film thickness, as an index.
    Type: Grant
    Filed: July 16, 2015
    Date of Patent: October 24, 2017
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Kouhei Sasamoto, Hideo Kaneko, Yukio Inazuki, Souichi Fukaya
  • Patent number: 9798242
    Abstract: In a resist pattern forming process, a rinse solution comprising (A) a heat/acid-decomposable polymer and (B) an organic solvent is effective. The pattern forming process using the rinse solution is successful in forming fine feature size patterns while minimizing the occurrence of pattern collapse.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: October 24, 2017
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Jun Hatakeyama, Daisuke Kori, Tsutomu Ogihara
  • Patent number: 9798244
    Abstract: Methods, apparatus, and system for minimizing defectivity in top-coat-free immersion photolithography are provided. Embodiments include forming a photomask by defining a first pattern including a main functional pattern in the photomask; and defining a second pattern including a sub-resolution fill pattern in the photomask in areas between or and/or within structures of the first pattern, the fill pattern having a pitch or range of pitches smaller than a minimum resolved pitch of the lithographic exposure and/or at least a part of the sub-resolution structures of the sub-resolution fill pattern not substantially modifying an imaging of any structure of the main functional pattern in the lithographic exposure.
    Type: Grant
    Filed: November 17, 2015
    Date of Patent: October 24, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Arthur Hotzel, Philipp Jaschinsky, Remi Riviere, Wolfram Grundke
  • Patent number: 9791786
    Abstract: Embodiments disclosed herein relate to an exposure pattern alteration software application which manipulates exposure polygons having lines with angles substantially close to angles of symmetry of a hex close pack arrangement, which suffer from long jogs. Long jogs present themselves as high edge placement error regions. As such, the exposure pattern alteration software application provides for line wave reduction by serrating polygon edges at affected angles to reduce edge placement errors during maskless lithography patterning in a manufacturing process.
    Type: Grant
    Filed: June 21, 2016
    Date of Patent: October 17, 2017
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Joseph R. Johnson, Christopher Dennis Bencher, Thomas L. Laidig
  • Patent number: 9779953
    Abstract: Methods and apparatus for plasma-enhanced substrate processing are provided herein. In some embodiments, an apparatus for processing a substrate includes: a process chamber having an internal processing volume disposed beneath a dielectric lid of the process chamber; a substrate support disposed in the process chamber; two or more concentric inductive coils disposed above the dielectric lid to inductively couple RF energy into the processing volume above the substrate support; and an electromagnetic dipole disposed proximate a top surface of the dielectric lid between two adjacent concentric inductive coils of the two or more concentric inductive coils.
    Type: Grant
    Filed: September 19, 2014
    Date of Patent: October 3, 2017
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Joseph F. Aubuchon, Tza-Jing Gung, Samer Banna
  • Patent number: 9772566
    Abstract: According to one embodiment, there is provided a mask alignment mark disposed on a photomask irradiated by an illumination optical system with illumination light from a direction inclined with respect to an optical axis and used to form a latent image on a substrate through a projection optical system. The mask alignment mark including a plurality of patterns arranged in a predetermined direction at a pitch of substantially P=?/{2×(1??)×(LNA)}, where ? is a ratio of a numerical aperture INA of illumination light incident on the photomask from the illumination optical system to a numerical aperture LNA of an object side of the projection optical system (INA)/(LNA), and ? is a wavelength of light.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: September 26, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Nobuhiro Komine, Kazuo Tawarayama
  • Patent number: 9772551
    Abstract: The defect size of a photomask blank is evaluated. An inspection-target photomask blank is irradiated with inspection light and reflected light of the region of the inspection-target photomask blank irradiated with the inspection light is collected through an objective lens of an inspection optical system as a magnified image of the region. Then, an intensity change part in the light intensity distribution profile of the magnified image is identified. Next, a difference in the light intensity of the intensity change part is obtained and the width of the intensity change part is obtained as the apparent width of the defect. Then, the width of the defect is calculated on the basis of a predetermined conversion expression showing the relationship among the difference in the light intensity, the apparent width of the defect, and the actual width of the defect, and the width of the defect is estimated.
    Type: Grant
    Filed: October 23, 2015
    Date of Patent: September 26, 2017
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Tsuneo Terasawa, Takahiro Kishita, Daisuke Iwai, Hiroshi Fukuda, Atsushi Yokohata
  • Patent number: 9766546
    Abstract: The method comprises the steps of applying a layer of a negative photoresist on a bottom layer, providing the layer of the negative photoresist with a pattern arranged in a border zone of the resist structure to be produced, irradiating a surface area of the layer of the negative photoresist according to the resist structure to be produced, and removing the layer of the negative photoresist outside the irradiated surface area. The pattern is produced in such a manner that it comprises a dimension that is smaller than a minimal resolution of the irradiation. The pattern may especially be designed as a sub-resolution assist feature.
    Type: Grant
    Filed: July 25, 2014
    Date of Patent: September 19, 2017
    Assignee: AMS AG
    Inventors: Gerhard Eilmsteiner, Raimund Hoffmann
  • Patent number: 9759997
    Abstract: The present disclosure provides an apparatus for a semiconductor lithography process in accordance with some embodiments. The apparatus includes a pellicle membrane with a thermal conductive surface; a porous pellicle frame; and a thermal conductive adhesive layer that secures the pellicle membrane to the porous pellicle frame. The porous pellicle frame includes a plurality of pore channels continuously extending from an exterior surface of the porous pellicle frame to an interior surface of the porous pellicle frame.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: September 12, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Amö Chen, Yun-Yue Lin, Ta-Cheng Lien, Hsin-Chang Lee, Chih-Cheng Lin, Jeng-Horng Chen
  • Patent number: 9754071
    Abstract: Various embodiments include approaches for analyzing integrated circuit (IC) designs. In some cases, an approach includes: defining extraction parameters for the design of the IC for each of a set of failure modes; testing the design of the IC for a failure mode in the set of failure modes; identifying a defined extraction parameter from the design of the IC for at least one of the set of failure modes; correlating the identified defined extracted parameter and each of the at least one failure mode for the design of the IC; and creating a normalized parameter equation representing the correlation of the identified defined extraction parameter with the at least one failure mode for the design of the IC in numerical form.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: September 5, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Haraprasad Nanjundappa, Basanth Jagannathan, Laura S. Chadwick, Dureseti Chidambarrao, Christopher V. Baiocco
  • Patent number: 9753365
    Abstract: The present disclosure provides a mask plate, belongs to the field of display technology, and can maintain a uniform exposing interval, so that the exposure pattern has a uniform deformation amount and pattern size. A mask plate comprises opaque regions and transparent regions, and spacers of the same height are arranged in the opaque regions. Another mask plate comprises active regions and dummy regions, and spacers of the same height are arranged in the dummy regions. The present disclosure can be applied in a process for fabricating a color film substrate.
    Type: Grant
    Filed: March 10, 2015
    Date of Patent: September 5, 2017
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Bing Lu
  • Patent number: 9754068
    Abstract: A method includes providing a layout of a portion of a photomask. The layout includes a plurality of target features having a shape in accordance with a corresponding one of a target shape. For each of the target shapes, a local map specifying a respective value of a local sub-resolution assist feature (SRAF) usefulness for each of a plurality of positions relative to the target shape is provided. For each of the target features, an assignment of a part of the values of the local SRAF usefulness of the local map for the target shape corresponding to a target feature to a position relative to the portion of the photomask is provided. A global map specifying a global SRAF usefulness for each of the positions relative to the portion of the photomask is provided on the basis of the assignment of the values of the local SRAF usefulness.
    Type: Grant
    Filed: April 13, 2015
    Date of Patent: September 5, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Andrey Lutich
  • Patent number: 9753366
    Abstract: The invention relates to a method for determining at least one unknown laser beam parameter of a laser beam used for correcting errors of a transparent material including inducing a first persistent modification in the material by an interaction with the laser beam having a first set of laser beam parameters, measuring the induced first persistent modification of the material, calculating a second persistent modification in the material using a model describing persistent modifications in the material with a second set of laser beam parameters, wherein the first set of laser beam parameters comprises the second set of laser beam parameters and the at least one unknown laser beam parameter, setting up a target functional including the first persistent modification and the second persistent modification, and determining the at least one unknown laser beam parameter by minimizing the target functional.
    Type: Grant
    Filed: October 4, 2011
    Date of Patent: September 5, 2017
    Assignee: Carl Zeiss SMS Ltd.
    Inventor: Vladimir Dmitriev
  • Patent number: 9746764
    Abstract: A mask blank, including: a thin film for forming a transfer pattern; a resist underlying film made of a resist underlying composition and provided on the thin film; a resist film made of a chemically amplified resist and provided on the resist underlying film; and a mixture film provided so as to be interposed between the resist underlying film and the resist film, wherein the resist underlying film is configured so that a molecular weight is reduced from the thin film side to the resist film side in a thickness direction, and has a low molecular weight region in which the molecular weight is low on the resist film side surface, and the mixture film is formed by mixing a component of the low molecular weight region and a component of the chemically amplified resist.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: August 29, 2017
    Assignees: HOYA CORPORATION, NISSAN CHEMICAL INDUSTRIES, LTD.
    Inventors: Takahiro Hiromatsu, Masahiro Hashimoto, Yasushi Sakaida, Ryuta Mizuochi, Rikimaru Sakamoto, Masaki Nagai
  • Patent number: 9746780
    Abstract: A maskless exposure device includes an exposure head including a digital micro-mirror device and an exposure source, the digital micro-mirror device being configured to reflect a source beam outputted from the exposure source to a substrate and a system controller configured to control the digital micro-mirror device by using a graphic data system file. The graphic data system file includes data regarding patterns to be formed on the substrate. A pattern extending in a direction parallel to a scan direction of the exposure head includes a first pattern portion having a first width that is greater than a target width and a second pattern portion alternately disposed with the first pattern portion and having a second width that is less than the target width.
    Type: Grant
    Filed: June 19, 2015
    Date of Patent: August 29, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventors: Hyun-Seok Kim, Sang-Hyun Yun, Hi-Kuk Lee, Jae-Hyuk Chang, Sang-Hyun Lee, Jung-In Park, Jung-Chul Heo, Kab-Jong Seo, Ki-Beom Lee, Jun-Ho Sim
  • Patent number: 9747401
    Abstract: A method for modifying an integrated circuit layout design includes providing an initial multiple-patterned circuit layout design comprising a first pattern exposure and a second pattern exposure; modifying the initial multiple-patterned circuit layout design by providing a subresolution assist feature to the first pattern exposure; determining whether the presence of any overlapping areas between the subresolution assist feature of the first pattern exposure and the second pattern exposure; and further modifying the initial multiple-patterned circuit layout design by: maintaining the size of any portion of the subresolution assist feature in the overlapping areas; and shrinking the size of any portion of the subresolution assist feature that is not in the overlapping areas.
    Type: Grant
    Filed: March 23, 2016
    Date of Patent: August 29, 2017
    Assignee: GLOBALFOUNDRIES, INC.
    Inventor: Ayman Hamouda
  • Patent number: 9748148
    Abstract: Embodiments of the disclosure provide apparatus and methods for localized stress modulation for overlay and edge placement error (EPE) using electron or ion implantation. In one embodiment, a process for correcting overlay error on a substrate generally includes performing a measurement process in a metrology tool on a substrate to obtain a substrate distortion or an overlay error map, determining doping parameters to correct overlay error or substrate distortion based on the overlay error map, and providing a doping recipe to a doping apparatus based on the doping parameters determined to correct substrate distortion or overlay error. Embodiments may also provide performing a doping treatment process on the substrate using the determined doping repair recipe, for example, by comparing the overlay error map or substrate distortion with a database library stored in a computing system.
    Type: Grant
    Filed: June 10, 2015
    Date of Patent: August 29, 2017
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Ellie Y. Yieh, Huixiong Dai, Srinivas D. Nemani, Ludovic Godet, Christopher Dennis Bencher
  • Patent number: 9746763
    Abstract: Provided is a phase shift mask including a substrate, a phase shift layer, and a shielding layer. The phase shift layer is located on the substrate. A pattern of the phase shift layer includes a main pattern and sub-resolution assist features (SRAFs). The SRAFs are disposed around the main pattern. The phase shift layer has a transmission, and the transmission is larger than 6%. The shielding layer at least covers the SRAFs of the phase shift layer.
    Type: Grant
    Filed: August 4, 2015
    Date of Patent: August 29, 2017
    Assignee: Winbond Electronics Corp.
    Inventor: Kao-Tun Chen
  • Patent number: 9741564
    Abstract: In a method of forming a mark pattern according to the embodiments, a film to be processed on a substrate is coated with a photosensitive film, and the photosensitive film is irradiated with exposure light via a mask. On the mask, a first circuit pattern having a first transmittance and a mark having a second transmittance and used to measure a superposition between films are arranged. By irradiating with the exposure light, a second circuit pattern having a first film thickness and a mark pattern having a second film thickness thinner than the first film thickness are formed on the substrate.
    Type: Grant
    Filed: July 30, 2015
    Date of Patent: August 22, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yuji Setta, Taketo Kuriyama, Nobuhiro Komine
  • Patent number: 9740093
    Abstract: A pellicle is proposed in which a mask-bonding agglutinant layer, that bonds the pellicle to a photomask, is divided into segments, and the vacancies thus created between these segments are entirely occupied by segments of a non-resilient body layer, and these alternately arranged segments are flush with each other.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: August 22, 2017
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventor: Kazutoshi Sekihara
  • Patent number: 9741828
    Abstract: The present invention discloses a mask, a manufacturing method thereof and a manufacturing method of a thin film transistor. The mask includes: a first substrate and phase shift patterns formed above the first substrate, wherein an opening area is formed between the adjacent phase shift patterns and a halftone pattern is formed at positions corresponding to the phase shift patterns and the opening area. In the present invention, when an active layer pattern, a source and a drain are formed through one patterning process by using the mask, the design of narrow channel of the thin film transistor can be realized. As the width of the channel region of the thin film transistor becomes narrow, the volume of the thin film transistor can be effectively reduced, and the super-miniaturization of the thin film transistor can be achieved.
    Type: Grant
    Filed: December 11, 2014
    Date of Patent: August 22, 2017
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Rui Xu
  • Patent number: 9739722
    Abstract: A process for inspecting an EUV mask blank capable of distinguishing phase defects and amplitude defects and capable of detecting small amplitude defects, a process for producing an EUV mask blank using the inspection process, and an EUV mask blank obtainable by such a process. A process for inspecting a reflective mask blank for EUV lithography having a multilayer reflective film and an absorber layer. The process includes a first step of detecting in-plane defects in the multilayer reflective film by applying EUV light to the surface of the multilayer reflective film, a second step of detecting in-plane defects from the absorber layer by applying light having a wavelength of from 150 to 600 nm to the surface of the absorber layer, and a step of distinguishing phase defects and amplitude defects in the reflective mask blank by comparison between the first and second in-plane defect data.
    Type: Grant
    Filed: October 8, 2015
    Date of Patent: August 22, 2017
    Assignee: Asahi Glass Company, Limited
    Inventors: Hiroshi Nakanishi, Junichi Kageyama, Yoshiaki Ikuta
  • Patent number: 9733562
    Abstract: An apparatus comprises a low EUV reflectivity (LEUVR) mask. The LEUVR mask includes a low thermal expansion material (LTEM) layer; a reflective multilayer (ML) over the LTEM layer; and a patterned absorption layer over the reflective ML. The reflective ML has less than 2% EUV reflectivity.
    Type: Grant
    Filed: October 26, 2015
    Date of Patent: August 15, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-Cheng Lu, Jeng-Horng Chen, Shinn-Sheng Yu, Anthony Yen
  • Patent number: 9733569
    Abstract: A mask includes a transparent substrate and a light blocking pattern. The light blocking pattern includes a light blocking part and a diffraction pattern. The light blocking part is disposed on the transparent substrate and is configured to block light. The diffraction pattern includes a plurality of protrusion parts and is configured to diffract the light. The plurality of protrusion parts protrudes from a side of the blocking part and is separated from each other.
    Type: Grant
    Filed: April 27, 2015
    Date of Patent: August 15, 2017
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Yong Son, Min Kang, Bong-Yeon Kim, Hyun-Joo Lee, Jin-Ho Ju
  • Patent number: 9735023
    Abstract: Disclosed herein is a composition comprising a first block copolymer that comprises a first block and a second block; where the first block has a higher surface energy than the second block; a second block copolymer that comprises a first block and a second block; where the first block of the first block copolymer is chemically the same as or similar to the first block of the second block copolymer and the second block of the first block copolymer is chemically the same as or similar to the second block of the second block copolymer; where the weight percent based on total solids of the first block of the second block copolymer is greater than that of the first block of the first block copolymer; where the first block copolymer phase separates into a first morphology of cylindrical or lamellar domains when disposed singly on a substrate.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: August 15, 2017
    Assignees: DOW GLOBAL TECHNOLOGIES LLC, ROHM AND HAAS ELECTRONIC MATERIALS LLC
    Inventors: Jieqian Zhang, Phillip D. Hustad, Peter Trefonas, III, Mingqi Li, Valeriy V. Ginzburg, Jeffrey D. Weinhold
  • Patent number: 9735011
    Abstract: A method is provided for fabricating a metal interconnect structure. The method includes forming a reticle having a metal line pattern region and at least a scattering bar by an optical proximity correction process; and providing a semiconductor substrate having a first dielectric layer and at least one conductive via. The method also includes aligning the reticle with the semiconductor substrate with the conductive via to align the scattering bar next to the conductive via; and forming metal line patterns on the first dielectric layer and a top surface of the conductive via to completely cover the conducive via.
    Type: Grant
    Filed: May 27, 2015
    Date of Patent: August 15, 2017
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Baojun Zhao
  • Patent number: 9734572
    Abstract: The present disclosure provides a method including providing a first image and a second image. The first image is of a substrate having a defect and the second image is of a reference substrate. A difference between the first image and the second image is determined. A simulation model is used to generate a simulation curve corresponding to the difference and the substrate dispositioned based on the simulation curve. In another embodiment, the scan of a substrate is used to generate a statistical process control chart.
    Type: Grant
    Filed: February 2, 2015
    Date of Patent: August 15, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yao-Wei Tien, Chi-Hung Liao, Ming-Yi Lee
  • Patent number: 9726972
    Abstract: A mask blank wherein damage to a light semitransmissive film due to dry etching for removing a light shielding film is inhibited. Mask blank 100 has a light semitransmissive film 2 and light shielding film 4 laminated on a main surface of a transparent substrate 1. Film 2 can be dry etched with a fluorine-based gas. Film 4 has laminated lower layer 41 and upper layer 42. Lower layer 41 contained tantalum and id substantially free from hafnium, zirconium, and oxygen. Upper layer 42 contains tantalum and one or more of hafnium and zirconium and is substantially free from oxygen excluding the surface layer of the upper layer 42. Between the light semitransmissive film 2 and lower layer 41 is an etching stopper film 3 having etch selectivity with respect to the lower layer 41 in dry etching with an etching gas containing the chlorine-based gas and no oxygen gas.
    Type: Grant
    Filed: August 15, 2014
    Date of Patent: August 8, 2017
    Assignee: HOYA CORPORATION
    Inventors: Hiroaki Shishido, Ryo Ohkubo, Osamu Nozawa
  • Patent number: 9720316
    Abstract: A mask blank for EUV lithography (EUVL) excellent in in-plane uniformity of the peak reflectivity of light in the EUV wavelength region and in in-plane uniformity of the center wavelength of reflected light in the EUV wavelength region, at the surface of a multilayer reflective film, and a process for its production, as well as a substrate with reflective layer for EUVL to be used for the production of such a mask blank for EUVL, and a process for its production. A substrate with reflective layer for EUVL having a reflective layer for reflecting EUV light formed on a substrate, where the reflective layer is a multilayer reflective film having a low refractive index layer and a high refractive index layer alternately stacked plural times.
    Type: Grant
    Filed: October 14, 2015
    Date of Patent: August 1, 2017
    Assignee: Asahi Glass Company, Limited
    Inventor: Masaki Mikami
  • Patent number: 9715175
    Abstract: A reticle protection device capable of keeping a reticle therein is provided with an inner pod capable of keeping the reticle therein; an outer pod capable of keeping the inner pod therein; an electroconductive movable contact portion provided on at least one of the inner pod and the outer pod and being capable of coming into contact with an electroconductive film of the reticle; and a leaf spring for achieving electric conduction of the contact portion to at least one of the inner pod and the outer pod. The reticle is kept in the inner pod and the inner pod is kept in the outer pod, thereby enabling stable grounding of the reticle.
    Type: Grant
    Filed: June 15, 2012
    Date of Patent: July 25, 2017
    Assignee: NIKON CORPORATION
    Inventor: Kazuya Ota
  • Patent number: 9715569
    Abstract: Disclosed are techniques for devising an electronic design with disconnected field domains. These techniques identify a plurality of electrically conductive shapes of an electronic design, add a plurality of patches to a model of the electronic design for multiple apertures in the electronic design, analyze the model to generate analysis results for the electronic design, and devise or implement the electronic design based in part or in whole upon the analysis, wherein an aperture of the multiple apertures causes disconnected electromagnetic field domains in the model.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: July 25, 2017
    Assignee: Cadence Design Systems, Inc.
    Inventors: Jian Liu, Xiande Cao, Jian Chen
  • Patent number: 9715170
    Abstract: Provided are an optical proximity correction (OPC) method capable of correcting a slit-effect in an extreme ultraviolet (EUV) exposure process and a method of manufacturing an EUV mask by using the OPC method. The OPC method includes, dividing a transmission cross coefficient (TCC) according to regions of a slit that is used in an EUV exposure process, generating OPC models reflecting the TCCs that are divided, and correcting the OPC method.
    Type: Grant
    Filed: June 16, 2015
    Date of Patent: July 25, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-hoon Jang, Sang-hwa Lee
  • Patent number: 9709884
    Abstract: The present disclosure provides a photolithography mask. The photolithography mask includes a substrate that contains a low thermal expansion material (LTEM). A reflective structure is disposed over the substrate. A capping layer is disposed over the reflective structure. An absorber layer is disposed over the capping layer. The absorber layer contains a material that has a refractive index in a range from about 0.95 to about 1.01 and an extinction coefficient greater than about 0.03.
    Type: Grant
    Filed: June 11, 2015
    Date of Patent: July 18, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Tsung Shih, Shinn-Sheng Yu, Jeng-Horng Chen, Anthony Yen
  • Patent number: 9709905
    Abstract: A method for fabricating a semiconductor structure includes providing a substrate and a first layer over the substrate, wherein the first layer includes one or more overlay marks. The method further includes forming one or more layers on the first layer and performing a dark field (DF) inspection on the one or more overlay marks underlying the one or more layers to receive a post-film-formation data.
    Type: Grant
    Filed: September 10, 2015
    Date of Patent: July 18, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bo-Jiun Lin, Hai-Ching Chen, Hsin-Chieh Yao, Tien-I Bao
  • Patent number: 9709481
    Abstract: A method determines the tack of a material placed in contact with a surface. A sample is provided of the material, the sample including a sheet whose width increases from a first narrow end to a second wide end. The sample is applied to an upwards facing supporting surface of plate. The sample is compacted against the supporting surface of plate and a weight is attached to the first end of the sample. The plate is turned over in such a way that the supporting surface faces downwards. The detachment of the sample from the supporting surface is measured in terms of distance detached from the first end of the sample as a function of time.
    Type: Grant
    Filed: February 4, 2015
    Date of Patent: July 18, 2017
    Assignee: ALENIA AERMACCHI S.p.A.
    Inventor: Stefano Giuseppe Corvaglia
  • Patent number: 9709885
    Abstract: A method for manufacturing a photomask blank having at least a silicon-containing inorganic film over a transparent substrate includes forming the silicon-containing inorganic film such that a surface has an oxygen concentration not less than 55 atomic percent and not more than 75 atomic percent, the silicon-containing inorganic film being an SiO film or an SiON film and serving as a hard mask film.
    Type: Grant
    Filed: October 3, 2016
    Date of Patent: July 18, 2017
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Yukio Inazuki, Takashi Yoshii, Toyohisa Sakurada, Akira Ikeda, Hideo Kaneko, Satoshi Watanabe, Yoshio Kawai
  • Patent number: 9703188
    Abstract: A pellicle is proposed in which the agglutinant layer which enable the pellicle to be adhered to a photomask is doped with a mechanoluminescent material so that the uniformness of the thickness of the agglutinant layer can be confirmed, when the pellicle is adhered to the photomask, by observing visually or by CCD camera for any irregularity in the pattern of the light emitted from the agglutinant layer.
    Type: Grant
    Filed: November 3, 2015
    Date of Patent: July 11, 2017
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Jun Horikoshi, Yu Yanase
  • Patent number: 9703187
    Abstract: The present invention addresses the problem of providing a pellicle which has high EUV transmittance and high strength, while being not susceptible to damage by heat. In order to solve the above-mentioned problem, the present invention provides a pellicle which comprises a pellicle film that has a refractive index (n) of light having a wavelength of 550 nm of 1.9-5.0 and a pellicle frame to which the pellicle film is bonded. The pellicle film has a composition that contains 30-100% by mole of carbon and 0-30% by mole of hydrogen. The intensity ratio of the 2D-band to the G-band, namely (intensity in 2D-band)/(intensity in G-band) is 1 or less, or alternatively, the intensity in the 2D-band and the intensity in the G-band are 0 in the Raman spectrum of the pellicle film.
    Type: Grant
    Filed: May 20, 2014
    Date of Patent: July 11, 2017
    Assignee: MITSUI CHEMICALS, INC.
    Inventors: Yosuke Ono, Kazuo Kohmura
  • Patent number: 9696649
    Abstract: An optical head includes a lens array including resin lenses, a holder that holds the lens array, and a positioning mechanism that positions the holder such that the holder is opposed to a target. The positioning mechanism is configured to change a distance between the lens array and the target depending on a change in at least any one of temperature and humidity.
    Type: Grant
    Filed: March 16, 2016
    Date of Patent: July 4, 2017
    Assignee: Oki Data Corporation
    Inventor: Taishi Kaneto
  • Patent number: 9697325
    Abstract: In a method, a layout of a device having a pattern of features is provided. The method continues to include identifying a first portion of at least one feature of the plurality of features. An image criteria for the first portion may be assigned. A lithography optimization parameter is determined based on the assigned image criteria for the first portion. Finally, the first portion of the at least one feature is imaged onto a semiconductor substrate using the determined lithography optimization parameter.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: July 4, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Ming Chang, Ming-Yo Chung, Tzu-Chun Lo, Ying-Hao Su
  • Patent number: RE46464
    Abstract: A method for forming a stair-step structure in a substrate is provided. An organic mask is formed over the substrate. A hardmask with a top layer and sidewall layer is formed over the organic mask. The sidewall layer of the hard mask is removed while leaving the top layer of the hardmask. The organic mask is trimmed. The hardmask is removed. The substrate is etched. The forming the hardmask, removing the sidewall layer, trimming the organic mask, and etching the substrate are repeated a plurality of times.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: July 4, 2017
    Assignee: Lam Research Corporation
    Inventors: Qian Fu, Ce Qin, Hyun-Yong Yu