Abstract: In a method of manufacturing a photo mask for lithography, circuit pattern data are acquired. A pattern density, which is a total pattern area per predetermined area, is calculated from the circuit pattern data. Dummy pattern data for areas having pattern density less than a threshold density are generated. Mask drawing data is generated from the circuit pattern data and the dummy pattern data. By using an electron beam from an electron beam lithography apparatus, patterns are drawn according to the mask drawing data on a resist layer formed on a mask blank substrate. The drawn resist layer is developed using a developing solution. Dummy patterns included in the dummy pattern data are not printed as a photo mask pattern when the resist layer is exposed with the electron beam and is developed.

Abstract: A pellicle for a lithographic apparatus, the pellicle including nitridated metal silicide or nitridated silicon as well as a method of manufacturing the same. Also disclosed is the use of a nitridated metal silicide or nitridated silicon pellicle in a lithographic apparatus. Also disclosed is a pellicle for a lithographic apparatus including at least one compensating layer selected and configured to counteract changes in transmissivity of the pellicle upon exposure to EUV radiation as well as a method of controlling the transmissivity of a pellicle and a method of designing a pellicle.

Abstract: A substrate with a multilayer reflective film, a reflective mask blank, a reflective mask and a method of manufacturing a semiconductor device that can prevent contamination of the surface of the multilayer reflective film even in the case of having formed reference marks on the multilayer reflective film. A substrate with a multilayer reflective film contains a substrate and a multilayer reflective film that reflects EUV light formed on the substrate. Reference marks are formed to a concave shape on the surface of the substrate with the multilayer reflective film. The reference marks have grooves or protrusions roughly in the center. The shape of the grooves or protrusions when viewed from overhead is similar or roughly similar to the shape of the reference marks.

Abstract: Extreme ultraviolet (EUV) mask blanks, methods for their manufacture and production systems therefor are disclosed. The EUV mask blanks comprise a substrate; a multilayer stack of reflective layers on the substrate; and an absorber layer comprising tantalum and iridium or ruthenium and antimony.

Abstract: Exemplary deposition methods may include delivering a silicon-containing precursor and a boron-containing precursor to a processing region of a semiconductor processing chamber. The methods may include delivering a dopant-containing precursor with the silicon-containing precursor and the boron-containing precursor. The dopant-containing precursor may include one or more of carbon, nitrogen, oxygen, or sulfur. The methods may include forming a plasma of all precursors within the processing region of the semiconductor processing chamber. The methods may include depositing a silicon-and-boron material on a substrate disposed within the processing region of the semiconductor processing chamber. The silicon-and-boron material may include greater than or about 1 at. % of a dopant from the dopant-containing precursor.

Abstract: A material for forming an organic film using a polymer including an imide group for forming an organic underlayer film that cures under film-forming conditions in the air and in an inert gas, generates no by-product in heat resistance and embedding and flattening characteristics of a pattern formed on a substrate, also adhesiveness to a substrate for manufacturing a semiconductor apparatus, a method for forming an organic film, and a patterning process. The material includes (A) a polymer having a repeating unit represented by the following general formula (1A) whose terminal group is a group represented by either of the following general formulae (1B) or (1C), and (B) an organic solvent: wherein, W1 represents a tetravalent organic group, and W2 represents a divalent organic group: wherein, R1 represents any of the groups represented by the following formula (1D), and two or more of R1s may be used in combination.

Abstract: A reticle structure includes a reticle having patterned features and a first border section enclosing the patterned features. The reticle structure includes a membrane having a middle section a second border section enclosing the middle section. The reticle structure includes a frame disposed between the membrane and the reticle to mount the membrane over the patterned features of the reticle. The frame creates an enclosure between the reticle and the membrane and encircles the patterned features of the reticle. The frame includes a plurality of holes and the plurality of holes produces a threshold percentage of opening in the frame to maintain an equalized pressure difference between the enclosure and outside the enclosure below a threshold pressure.

Abstract: A fusible structure includes a metal line with different portions having different thicknesses. Thinner portions of the metal line are designed to be destructively altered at lower voltages while thicker portions of the metal line are designed to be destructively altered at lower voltages. Furthermore, one or more dummy structures are disposed proximal to the thinner portions of the metal line. In some embodiments, dummy structures are placed with sufficient proximity so as to protect against metal sputtering when metal line is destructively altered.

Abstract: A robust, high-transmission pellicle for extreme ultraviolet lithography systems is disclosed. In one example, the present disclosure provides a pellicle that includes a membrane and a frame supporting the membrane. The membrane may be formed from at least one of a transparent carbon-based film and a transparent silicon based film. The at least one of the transparent carbon-based film and the transparent silicon based film may further be coated with a protective shell. The frame may include at least one aperture to allow for a flow of air through a portion of the pellicle.

Abstract: The present disclosure describes a method of patterning a semiconductor wafer using extreme ultraviolet lithography (EUVL). The method includes receiving an EUVL mask that includes a substrate having a low temperature expansion material, a reflective multilayer over the substrate, a capping layer over the reflective multilayer, and an absorber layer over the capping layer. The method further includes patterning the absorber layer to form a trench on the EUVL mask, wherein the trench has a first width above a target width. The method further includes treating the EUVL mask with oxygen plasma to reduce the trench to a second width, wherein the second width is below the target width. The method may also include treating the EUVL mask with nitrogen plasma to protect the capping layer, wherein the treating of the EUVL mask with the nitrogen plasma expands the trench to a third width at the target width.

Abstract: The substrate with a multilayer reflective film includes a substrate and the multilayer reflective film configured to reflect exposure light, the multilayer reflective film comprising a stack of alternating layers on a substrate, the alternating layers including a low refractive index layer and a high refractive index layer, in which the multilayer reflective film contains molybdenum (Mo) and at least one additive element selected from nitrogen (N), boron (B), carbon (C), zirconium (Zr), oxygen (O), hydrogen (H) and deuterium (D), and the crystallite size of the multilayer reflective film calculated from a diffraction peak of Mo (110) by X-ray diffraction is 2.5 nm or less.

Abstract: Some implementations described herein provide a reticle cleaning device and a method of use. The reticle cleaning device includes a support member configured for extension toward a reticle within an extreme ultraviolet lithography tool. The reticle cleaning device also includes a contact surface disposed at an end of the support member and configured to bond to particles contacted by the contact surface. The reticle cleaning device further includes a stress sensor configured to measure an amount of stress applied to the support member at the contact surface. During a cleaning operation in which the contact surface is moving toward the reticle, the stress sensor may provide an indication that the amount of stress applied to the support member satisfies a threshold. Based on satisfying the threshold, movement of the contact surface and/or the support member toward the reticle ceases to avoid damaging the reticle.

Abstract: The present application discloses a display panel, a manufacturing method of a display panel and a mask used thereof. The manufacturing method of the display panel comprises the following steps: doping a photo-initiator in photoresist for manufacturing photo spacers; coating the photoresist on the substrates to form photo spacers, and arranging a shade on the same layer; and respectively irradiating corresponding photo spacers by at least two types of light rays of different wavelengths, to control the photo-initiator so as to enable different photo spacers to have different shrinkages.

Abstract: A measuring device includes a measuring stage on which a subject is placed, an X-ray irradiation unit, an X-ray detection unit that detects scattered X-rays generated from the subject and an analysis unit that analyzes the diffraction image obtained by photo-electrically converting scattered X-rays and presumes (estimates) the three-dimensional shape of the subject. In the subject, holes are formed in the ON stack film from the opening of the etching mask film formed on the ON stack film. The analysis unit presumes the three-dimensional shape of the subject based a plurality of the diffraction images acquired while changing a rotation angle of the measuring stage and the measurement data of the subject by at least one of measuring methods of a multi-wavelength light measurement and a laser ultrasonic wave measurement.

Abstract: A semiconductor device is disclosed, which relates to a three-dimensional (3D) semiconductor memory device. The semiconductor device includes a first connection pattern, a bit line disposed over the first connection pattern in a vertical direction, and a bit-line contact pad, disposed in a first layer between the bit line and the first connection pattern to electrically couple the bit line to the first connection pattern so that the bit-line contact pad, and formed as an island when viewed along the vertical direction.

Abstract: Provided is a phase shift mask blank including a substrate, and a phase shift film thereon, the phase shift film composed of a material containing silicon and nitrogen and free of a transition metal, exposure light being KrF excimer laser, the phase shift film consisting of a single layer or a plurality of layers, the single layer or each of the plurality of layers having a refractive index n of at least 2.5 and an extinction coefficient k of 0.4 to 1, with respect to the exposure light, and the phase shift film having a phase shift of 170 to 190° and a transmittance of 4 to 8%, with respect to the exposure light, and a thickness of up to 85 nm.

Abstract: Extreme ultraviolet (EUV) mask blanks, methods for their manufacture and production systems therefor are disclosed. The EUV mask blanks comprise a substrate; a multilayer stack of reflective layers on the substrate; a capping layer on the multilayer stack of reflecting layers; and an absorber layer on the capping layer, the absorber layer made from carbon and antimony.

Abstract: Extreme ultraviolet (EUV) mask blanks, methods for their manufacture and production systems therefor are disclosed. The EUV mask blanks comprise a substrate; a multilayer stack of reflective layers on the substrate; a capping layer on the multilayer stack of reflecting layers; and an absorber layer on the capping layer, the absorber layer made from antimony and nitrogen.

Abstract: An IC layout diagram generation system includes a processor and a non-transitory, computer readable storage medium including computer program code for one or more programs. The non-transitory, computer readable storage medium and the computer program code are configured to, with the processor, cause the system to align a border segment of a cell at a predetermined location relative to a plurality of second metal layer tracks, position the cell relative to a first metal layer cut region alignment pattern based on the plurality of second metal layer tracks, overlap the cell with a first metal layer cut region based on the first metal layer cut region alignment pattern, and generate an IC layout diagram of an IC device based on the cell and the first metal layer cut region.

Abstract: A method comprising the steps of receiving a mask assembly comprising a mask and a removable EUV transparent pellicle held by a pellicle frame, removing the pellicle frame and EUV transparent pellicle from the mask, using an inspection tool to inspect the mask pattern on the mask, and subsequently attaching to the mask an EUV transparent pellicle held by a pellicle frame. The method may also comprise the following steps: after removing the pellicle frame and EUV transparent pellicle from the mask, attaching to the mask an alternative pellicle frame holding an alternative pellicle formed from a material which is substantially transparent to an inspection beam of the inspection tool; and after using an inspection tool to inspect the mask pattern on the mask, removing the alternative pellicle held by the alternative pellicle frame from the mask in order to attach to the mask the EUV transparent pellicle held by the pellicle frame.

Abstract: Placement methods described in this disclosure provide placement and routing rules where a system implementing the automatic placement and routing (APR) method arranges standard cell structures in a vertical direction that is perpendicular to the fins but parallel to the cell height. Layout methods described in this disclosure also improve device density and further reduce cell height by incorporating vertical power supply lines into standard cell structures. Pin connections can be used to electrically connect the power supply lines to standard cell structures, thus improving device density and performance. The APR process is also configured to rotate standard cells to optimize device layout.

Abstract: The prevent disclosure provides a reflective mask. In some embodiments, the reflective mask includes a substrate, a sp2-hybrid carbon layer, a reflective multilayer, and an absorption pattern. The sp2-hybrid carbon layer is over the substrate. The reflective multilayer is over the sp2-hybrid carbon layer. The absorption pattern is over the reflective multilayer.

Abstract: Extreme ultraviolet (EUV) mask blanks, methods for their manufacture and production systems therefor are disclosed. The EUV mask blanks comprise a substrate; a multilayer stack of reflective layers on the substrate; a capping layer on the multilayer stack of reflecting layers; and an absorber layer on the capping layer, the absorber layer made from tantalum and ruthenium.

Abstract: Embodiments of the present disclosure relate to methods for defect inspection. After pattern features are formed in a structure layer, a dummy filling material having dissimilar optical properties from the structure layer is filled in the pattern features. The dissimilar optical properties between materials in the pattern features and the structure layer increase contrast in images captured by an inspection tool, thus increasing the defect capture rate.

Abstract: An integrated circuit, and method of forming the same. The integrated circuit includes standard logic cells and a combined logic cell over a semiconductor substrate. Each standard logic cell includes a standard height, a width that is an integer multiple of a unit width, first and second power rails, and at least one transistor and interconnections configured to implement a logic function that produces a single logic output. The combined logic cell includes the standard height, a width that is an integer multiple of the unit width, the first and second power rails, and at least two transistors and interconnections configured to implement a first logic function and a second logic function. The first and second logic functions produce first and second logic outputs, respectively. The interconnections are configured to direct the first logic output and the second logic output to destinations outside the combined logic cell.

Abstract: Systems and methods for custom photolithography masking via a precision dispense apparatus and process are disclosed. Methods include creating a toolpath instruction for depositing opaque onto a substrate, programming a precision dispense apparatus to execute the created toolpath instruction, and causing the precision dispense tool to deposit opaque material onto the substrate to form the photomask. The substrate may be an optically transparent plate or film or may be an electronic substrate where the opaque material is deposited directly onto a photoresist coating. Capabilities of the systems and methods disclosed herein extend to 3D substrates and custom photolithography masking, among others.

Abstract: A method for manufacturing a membrane assembly for EUV lithography, the method including: providing a stack having a planar substrate and at least one membrane layer, wherein the planar substrate includes an inner region and a border region around the inner region; and selectively removing the inner region of the planar substrate. The membrane assembly includes: a membrane formed from the at least one membrane layer; and a border holding the membrane, the border formed from the border region of the planar substrate. The stack is provided with a mechanical protection material configured to mechanically protect the border region during the selectively removing the inner region of the planar substrate.

Abstract: Provided is a mask blank in which a light shielding film which is a single layer film formed of a silicon nitride-based material has high light shielding performance against ArF exposure light and is capable of reducing EMF bias of a pattern of the light shielding film. The mask blank includes the light shielding film on a transparent substrate. The light shielding film has an optical density of 3.0 or greater to ArF exposure light. A refractive index n and an extinction coefficient k of the light shielding film to ArF exposure light simultaneously satisfy relationships defined by Formulas (1) and (2) below. n?0.0733×k2+0.4069×k+1.0083 ??Formula (1) n?29.316×k2?92.292×k+72.

Abstract: Correction method of mask layout and mask containing corrected layout are provided. The method includes providing a target layout including a plurality of main patterns. Each main pattern includes a first side and an opposite second side. Extending directions of the first side and the second side are perpendicular to a first direction. Each main pattern also includes a third side and an opposite fourth side. Extension directions of the third side and the fourth side are perpendicular to a second direction. The second direction and the first direction are perpendicular to each other. The method also includes acquiring position information of each main pattern, and obtaining position information of auxiliary patterns adjacent to each main pattern. The method also includes, according to the position information of the auxiliary patterns adjacent to each main pattern, arranging the auxiliary patterns adjacent to each main pattern around each main pattern.

Abstract: A method for manufacturing a compound semiconductor substrate that can achieve thinning of SiC film, wherein the method includes forming a SiC film on one principal surface side of a Si substrate and forming a recessed part in which a bottom surface is Si in a central part of another principal surface of the Si substrate.

Abstract: In a method of manufacturing a reflective mask, a photo resist layer is formed over a mask blank. The mask blank includes a substrate, a reflective multilayer on the substrate, a capping layer on the reflective multilayer, an absorber layer on the capping layer and a hard mask layer, and the absorber layer is made of Cr, CrO or CrON. The photo resist layer is patterned, the hard mask layer is patterned by using the patterned photo resist layer, the absorber layer is patterned by using the patterned hard mask layer, and an additional element is introduced into the patterned absorber layer to form a converted absorber layer.

Abstract: Extreme ultraviolet (EUV) mask blanks, methods for their manufacture and production systems therefor are disclosed. The EUV mask blanks comprise a substrate; a multilayer stack of reflective layers on the substrate; a capping layer on the multilayer stack of reflecting layers; and an absorber layer on the capping layer, the absorber layer comprising an alloy selected from an alloy of tantalum, iridium and antimony; an alloy of iridium and antimony; and an alloy of tantalum, ruthenium and antimony.

Abstract: Embodiments disclosed herein include EUV reticles and methods of forming such reticles. In an embodiment a method of forming an EUV reticle comprises providing a reticle, where the reticle comprises, a substrate, a mirror layer over the substrate, where the mirror layer comprises a plurality of first mirror layers and second mirror layers in an alternating pattern, and a capping layer over the mirror layer. In an embodiment, the method may further comprise disposing a first layer over the capping layer, patterning an opening in the first layer, and disposing a second layer in the opening, where the second layer is disposed with an electroless deposition process.

Abstract: Provided are an overlay mark, and an overlay measurement method and a semiconductor device manufacturing method using the overlay mark. Specifically, provided is an overlay mark for determining relative misalignment between two or more pattern layers or between two or more patterns separately formed in one pattern layer, the overlay mark including a first overlay mark positioned in the center, a second overlay mark positioned above and below the first overlay mark or on the left and right thereof, and a third overlay mark and a fourth overlay mark each positioned in a diagonal line with the first overlay mark in between.

Abstract: A physical vapor deposition (PVD) chamber and a method of operation thereof are disclosed. Chambers and methods are described that provide a chamber comprising an upper shield with two holes that are positioned to permit alternate sputtering from two targets. A process for improving reflectivity from a multilayer stack is also disclosed.

Abstract: The present invention is to provide a pellicle characterized by including a pellicle film and a pellicle frame, in which the pellicle film is stretched on the pellicle frame, and the pellicle film is an annealed pellicle film, and to provide a method for producing a pellicle by stretching a pellicle film on a pellicle frame, including the step of annealing the pellicle film alone before stretching the pellicle film on the pellicle frame, annealing the pellicle after stretching the pellicle film on the pellicle frame, or annealing the pellicle film alone and the pellicle both before and after stretching the pellicle film on the pellicle frame.

Abstract: According to an aspect of the present disclosure there is provided a method for forming an EUVL pellicle, the method comprising: coating a carbon nanotube, CNT, membrane, and mounting the CNT membrane to a pellicle frame, wherein coating the CNT membrane comprises: pre-coating CNTs of the membrane with a seed material, and forming an outer coating on the pre-coated CNTs, the outer coating covering the pre-coated CNTs, the forming of the outer coating comprising depositing a coating material on the pre-coated CNTs by atomic layer deposition.

Abstract: A reflective mask includes a substrate, a reflective multilayer disposed on the substrate, a capping layer disposed on the reflective multilayer, and an absorber layer disposed on the capping layer. The absorber layer includes a base material made of one or more of a Cr based material, an Ir based material, a Pt based material, or Co based material, and further contains one or more additional elements selected from the group consisting of Si, B, Ge, Al, As, Sb, Te, Se and Bi.

Abstract: Extreme ultraviolet (EUV) mask blanks, methods for their manufacture and production systems therefor are disclosed. The EUV mask blanks comprise a substrate; a multilayer stack of reflective layers on the substrate; a capping layer on the multilayer stack of reflecting layers; and an absorber layer on the capping layer, the absorber layer comprising an alloy of molybdenum (Mo) and antimony (Sb).

Abstract: The present invention is to provide a pellicle frame in a frame shape, having an upper end face to arrange a pellicle film thereon and a lower end face to face a photomask, and which is characterized by being provided with a notched part from an outer side face toward an inner side face of the upper end face, and to provide a pellicle characterized by including the pellicle frame as a component.

Abstract: A method for aligning molecular orientations of liquid crystals and/or polymeric materials into spatially variant patterns uses metamasks. When non-polarized or circularly polarized light is transmitted through or reflected by the metamasks, spatially varied polarization direction and intensity patterns of light can be generated. By projecting the optical patterns of the metamasks onto substrates coated with photoalignment materials, spatially variant molecular orientations encoded in the polarization and intensity patterns are induced in the photoalignment materials, and transfer into the liquid crystals. Possible designs for the metamask use nanostructures of metallic materials (e.g., rectangular nanocuboids of metallic materials arrayed on a transparent substrate).

Abstract: Integrated circuit devices and methods of forming the same are provided. The methods may include sequentially forming an underlying mask layer and a preliminary first mask layer on a substrate, forming a first mask structure by removing a portion of the preliminary first mask layer, and then forming a preliminary second mask layer. The preliminary second mask layer may enclose the first mask structure in a plan view. The methods may also include forming a second mask structure by removing a portion of the preliminary second mask layer and forming a vertical channel region including a portion of the substrate by sequentially etching the underlying mask layer and the substrate. The second mask structure may be connected to the first mask structure, and etching the underlying mask layer may be performed using the first and the second mask structures as an etch mask.

Abstract: A semiconductor device of an embodiment includes a plurality of chip regions, each including a memory region in which a plurality of memory cells is arranged, and a kerf region disposed between the chip regions and surrounding each chip region. Paired marks are arranged in a vicinity of the memory region of one of the plurality of chip regions and in a common hierarchical layer in the kerf region, and the paired marks are disposed over upper and lower hierarchical layers.

Abstract: Disclosed is a blankmask for EUV includes a substrate, a reflection film that is stacked on the substrate; and an absorbing film that is stacked on the reflection film. The reflection film has a structure in which a pair including a first layer made of Ru or a Ru compound in which one or more of Mo, Nb, and Zr are added to Ru, and a second layer made of Si is stacked plural times. Interdiffusion between the respective layers constituting the reflection film is suppressed.

Abstract: A thermoplastic elastomer compound includes polyolefin elastomer, high softening point tackifier, and, optionally, styrenic block copolymer. When styrenic block copolymer is present, the weight ratio of polyolefin elastomer to styrenic block copolymer is no less than about 1:1. The polyolefin elastomer has a POE Tan Delta Peak Temperature, the styrenic block copolymer has a SBC Tan Delta Peak Temperature, and the thermoplastic elastomer compound has a Compound Tan Delta Peak Temperature. The Compound Tan Delta Peak Temperature is greater than the POE Tan Delta Peak Temperature. When styrenic block copolymer is present, Compound Tan Delta Peak Temperature is also greater than the SBC Tan Delta Peak Temperature. The thermoplastic elastomer compound exhibits useful damping properties at or above room temperature and can be formed into plastic articles, including foamed plastic articles and/or crosslinked plastic articles, which can be useful for a variety of damping applications.

Abstract: A pellicle having a metal oxysilicide layer. A pellicle having a molybdenum layer, a ruthenium layer and a silicon oxynitride layer, wherein the molybdenum layer is disposed between the ruthenium layer and the silicon oxynitride layer. A method of manufacturing a pellicle for a lithographic apparatus, the method including providing a metal oxysilicide layer. A lithographic assembly including a pellicle having a metal oxysilicide layer. The use of a pellicle having a metal oxysilicide layer in a lithographic apparatus.

Abstract: An extreme ultra-violet mask includes a substrate, a multi-layered mirror layer, a capping layer, a first tantalum-containing oxide layer, a tantalum-containing nitride layer, and a second tantalum-containing oxide layer. The multi-layered mirror layer is over the substrate. The capping layer is over the multi-layered mirror layer. The first tantalum-containing oxide layer is over the capping layer. The tantalum-containing nitride layer is over the first tantalum-containing oxide layer. The second tantalum-containing oxide layer is over the tantalum-containing nitride layer.

Abstract: Monolithic framed pellicle membrane integrating a structural framing member with a membrane spanning the framing member. The monolithic frame pellicle membrane is suitable as an overlay of a reticle employed in lithography operations of integrated circuit manufacture. A semiconductor-on-insulator (SOI) wafer may be machined from the backside, for example with a bonnet polisher, to form a pellicle framing member by removing a portion of a base semiconductor substrate of the SOI wafer selectively to top semiconductor layer of the SOI wafer, which is retained as a pellicle membrane. In some exemplary embodiments suitable for extreme ultraviolet (EUV) lithography applications, at least the top semiconductor layer of the SOI wafer is a substantially monocrystalline silicon layer.

Abstract: Extreme ultraviolet (EUV) mask blanks, methods for their manufacture and production systems therefor are disclosed. The EUV mask blanks comprise a substrate; a multilayer stack of reflective layers on the substrate; a capping layer on the multilayer stack of reflecting layers; an absorber layer on the capping layer, the absorber layer comprising an antimony-containing material; and a hard mask layer on the absorber layer, the hard mask layer comprising a hard mask material selected from the group consisting of CrO, CrON, TaNi, TaRu and TaCu.

Abstract: Provided is a reflective mask blank with which it is possible to further reduce the shadowing effect of a reflective mask, and also possible to form a fine and highly accurate phase-shift pattern. A reflective mask blank having, in the following order on a substrate, a multilayer reflective film and a phase-shift film that shifts the phase of EUV light, said reflective mask blank characterized in that: the phase-shift film has a first layer and a second layer; the first layer comprises a material that contains at least one element from among tantalum (Ta) and chromium (Cr); and the second layer comprises a metal-containing material that contains ruthenium (Ru) and at least one element from among chromium (Cr), nickel (Ni), cobalt (Co), vanadium (V), niobium (Nb), molybdenum (Mo), tungsten (W), and rhenium (Re).