Abstract: A multilayer flexible wiring board, suited for mounting semiconductor elements. The flexible wiring board is fabricated in the following manner. A flexible wiring board piece having a metal wiring, in which a metal coating is exposed on at least a part of surface of the metal wiring, is adhered to another flexible wiring board piece having a metal projection on which a metal coating is formed. One of or both of the metal coatings on the metal wiring and the metal projection is composed of a soft metal coating a surface of which has a Vickers' hardness of 80 kgf/mm2 or lower. The metal coating of the metal wiring contacts with the metal coating of said metal projection and ultrasonic wave is applied thereto to connect the metal wiring with the metal projection.

Abstract: The present invention provides a method, apparatus and system for building a wafer-interposer assembly. The method includes the steps of forming a redistribution layer (RDL) pad on a semiconductor wafer. The semiconductor wafer has a semiconductor die and the RDL pad has an electrical connection to the semiconductor die. A layer of epoxy is placed on the semiconductor wafer and on the RDL pad. The epoxy is then leveled generally parallel to the surface of the semiconductor wafer and removed from a portion of the RDL pad. An interposer pad is formed on the RDL pad where the epoxy was removed.

Abstract: Disclosed herein is a technique which performs the thinning of a wafer and the separation thereof from a support substrate with high yields and in a short time. Described specifically, a hole-free support substrate is bonded to a second surface of a support substrate having holes with an adhesive layer melted by heating so as to bloc the holes. A wafer is bonded to a first surface of the support substrate having the holes with an adhesive layer melted by solvent. The wafer is thinned by grinding and etching. The adhesive layer is melted by heating and the support substrate having the holes is slid with respect to the hole-free support substrate to thereby separate the support substrate having the holes from the hole-free support substrate. Further, the adhesive layer is melted by solvent from the holes defined in the support substrate having the holes to thereby separate the wafer from the support substrate having the holes.

Abstract: A structure and a method which can reliably electrically connect opposed terminals with each other are disclosed. First and second terminals are opposed to each other, so that an anisotropic conductive film is interposed therebetween. Ultrasonic vibration is supplied between the terminals while applying pressure so that the first and second terminals approach to each other. The first and second terminals are electrically connected with each other through conductive grains contained in the anisotropic conductive film. The conductive grains and the terminals are alloy-bonded with each other.

Abstract: A two step wire bonding process is used to ultrasonically attach a wire (18) to a contact pad (13) on a semiconductor device (10). A first step is used to flatten a rounded tip (19) of the wire (18), and to start the bonding process. This is accomplished by applying a relatively large force to the rounded tip (19), and a relatively low vibrating displacement to the flattened wire tip (19). During a second step the large force is reduced, however; the vibrating displacement is increased. The total time for the two step wire bonding process is slightly less than a prior art one step process.

Abstract: A method and apparatus for attaching a semiconductor device to a substrate. One end of the substrate is elevated to position the substrate and the coupled semiconductor device on an inclined plane. An underfill material is introduced along a wall of the semiconductor device located at the elevated end of the inclined substrate with the underfill material being placed between the substrate and the semiconductor device. An optional but preferred additional step of the invention includes coupling a barrier means to the substrate at a point on the substrate adjacent to a sidewall of the semiconductor device located at the lowest point of the slope created by the inclined substrate. The barrier means prevents the underfill material from spreading beyond the sidewalls of the semiconductor device, particularly in instances where the substrate is inclined at a steep angle.

Abstract: Improved methods and apparatus for forming an assembly by attaching an electronic package to a substrate are disclosed. The electronic package includes a microelectronic device, conductive leads to couple the device to the substrate, and an encapsulant surrounding the device and a portion of the conductive leads. A filler is added to the assembly to surround the otherwise exposed portion of the leads. The filler material is selected such that the dielectric constant of the filler is approximately the same as the dielectric constant of the encapsulant. Surrounding the lead with material having substantially similar dielectric constants reduces impedance variation along the length of the lead.

Abstract: The invention provides a method for manufacturing a semiconductor device for preventing the low bonding strength reliability in flip tip mounting of a semiconductor chip on an organic substrate. In the thermal hardening process for hardening the under fill resin filled between a semiconductor chip and organic substrate. The thermal expansion due to rapid heating of an organic substrate is mitigated by applying multi-step heating process in which under fill resin is heated at a temperature T1 lower than the hardening temperature T2 of the under fill resin for a predetermined time.

Abstract: A method for forming a semiconductor device includes providing a lead frame which has a die pad and a plurality of leads extending toward the outside of the die pad, mounting a semiconductor chip on the die pad, defining a plurality of inner leads by cutting a predetermined cut portion on each of the leads located around the semiconductor chip, and bonding a wire between the inner leads and the semiconductor chip. Accordingly, an applicable lead frame is provided for several sizes of a semiconductor chip.

Abstract: A process for manufacturing a silicon-on-insulator wafer from a silicon wafer assembly. The assembly is made of two wafers. One of the wafers contains a fragile layer. The fragile layer is a layer containing a high amount of hydrogen. An amount of energy from an energy source is applied to the assembly to separate the assembly along the fragile layer thus forming a silicon-on-insulator wafer and a leftover wafer. The energy source is selected from the group consisting of: ultrasound, infrared, hydrostatic pressure, hydrodynamic pressure, or mechanical energy. The amount of energy is chosen to be sufficient to transform the fragile layer into a quasi-continuous gaseous layer. Under separation the hydrogen-enriched layer transforms into layer consisting of hydrogen platelets and hydrogen microbubbles.

Abstract: A plurality of separate semiconductor chips, each having a contact-bearing surface and contacts on such surface, are disposed in an array so that the contact-bearing surfaces face and define a first surface of the array. A flexible, dielectric sheet with terminals thereon overlies the first or contact bearing surface of the semiconductor chips. Elongated leads are disposed between the dielectric element and the semiconductor chips. Each lead has a first end connected to a terminal on the dielectric element, and a second end connected to a contact on a semiconductor chip in the array. All of the leads are formed simultaneously by moving the dielectric element and the array relative to one another to simultaneously displace all of the first ends of the leads relative to all of the second ends. The dielectric element is subdivided after the forming step so as to leave one region of the dielectric element connected to each chip and thereby form individual units each including one chip, or a small number of chips.

Abstract: In a method of coating a semiconductor wafer with a resin of the present invention, first, a semiconductor wafer is placed on a bottom surface of a cavity provided in a molding surface of a lower mold of a mold with its surface having a bump facing upward. Thereafter, a required amount of resin material is supplied to cavity, and a film for exposing the bump is applied to a molding surface of the upper one of the molds. In this state, molds are closed together. Resin material is heated to melt in cavity. Then, film is pressed against the bottom surface of cavity by a pressing member provided on the molding surface of the upper mold, so that film is abutted against a leading edge of bump in cavity. A pressure is applied to the resin in cavity through film, and the surface having the bump of semiconductor wafer is coated with resin. According to the method, pressing member is provided on the upper mold, so that melted resin does not enter a sliding portion.

Abstract: A method for fabricating an electric circuit device able to ensure bonding strength and bond bumps without occurrence of cratering or other mechanical damages

Abstract: A method of manufacturing a semiconductor device having reliable electrical connections between projected electrodes of a semiconductor pellet and pad electrodes of a wiring substrate. In this method, the semiconductor pellet having a plurality of projected electrodes and the wiring substrate having a plurality of pad electrodes are prepared. Liquid resin material including inorganic filler dispersed therein is applied on the wiring substrate. The semiconductor pellet is opposed to the wiring substrate via the resin material, and the projected electrodes are superposed and pressed onto the pad electrodes. The projected electrodes and the pad electrodes are electrically coupled while vibrating the resin material in the proximity of the projected electrodes and excluding the inorganic filler from superposed interface portions between the projected electrodes and the pad electrodes.

Abstract: A method for producing a semiconductor device, comprises the steps of: introducing a plurality of semiconductor element supporting substrates or semiconductor elements into a conductive-ball attaching system for collectively attaching conductive balls onto the supporting substrates or semiconductor elements; detecting the position of a defective substrate or defective semiconductor element of the introduced semiconductor element supporting substrates or semiconductor elements, or an undesired position, at which it is not necessary to load the conductive balls; vacuum holding a plurality of conductive balls, which are stored in the conductive-ball attaching system, by conductive-ball holding means; and selectively attaching the plurality of conductive balls, which are vacuum-held by the conductive-ball holding means, onto a desired supporting substrate or semiconductor element of the supporting substrates or semiconductor elements introduced into the conductive-ball attaching system, wherein the conductive-bal

Abstract: A semiconductor chip mounting method to prevent the occurrence of particles created while mounting the semiconductor chip onto a substrate using ultrasonic thermocompression bonding. The mounting method of the present invention utilizing ultrasonic vibrations involves the following steps: a semiconductor chip having conductive bumps on its main surface is held by its back via an elastic film using a suction tool having a suction hole, the semiconductor chip is positioned against a substrate provided with connection wires corresponding to said conductive bumps, and the semiconductor chip is mounted onto the substrate in such a manner that the conductive bumps connect to said connection wires, and ultrasonic vibrations are applied from the suction tool to the semiconductor chip via said film while said semiconductor chip is being pressed against said substrate in order to bond said conductive bumps with said connection wires.

Abstract: A process for producing a microencapsulated electroconductive filler comprising conductive filler particles each having an insulating resin coated on the surface thereof, which comprises: a first step of treating the surface of conductive filler particles with a coupling agent having reactive functional group A at a terminal end or in a side chain of its molecule; and a second step of allowing the coupling agent having functional group A present on the surface of the conductive filler particles to undergo nonaqueous polymerization reaction with a reactant B which is polymerizable with the functional group A, to thereby form an insulating resin layer on the surface of the conductive filler particles.

Abstract: Provided is a method of fabricating a vacuum micro-structure, which is used for an element operating in a vacuum, the method comprising the steps of: (1) entirely etching an epitaxial layer of a silicon substrate having an SOI structure including an upper silicon epitaxial layer, an interlevel insulating layer and a lower silicon bulk layer to form two electrode structures and a floating vibratory structure, and encapsulating them with a vacuum sealing substrate in a vacuum; and (2) etching the silicon substrate having the SOI stricture from the back side to the interlevel insulating layer to open the electrode structures, and forming a metal electrode.

Abstract: A method and apparatus for attaching a semiconductor device to a substrate. One end of the substrate is elevated to position the substrate and the coupled semiconductor device on an inclined plane. An underfill material is introduced along a wall of the semiconductor device located at the elevated end of the inclined substrate with the underfill material being placed between the substrate and the semiconductor device. An optional but preferred additional step of the invention includes coupling a barrier means to the substrate at a point on the substrate adjacent to a sidewall of the semiconductor device located at the lowest point of the slope created by the inclined substrate. The barrier means prevents the underfill material from spreading beyond the sidewalls of the semiconductor device, particularly in instances where the substrate is inclined at a steep angle.

Abstract: A method for assembling electronic devices by moving particles (12) on an adhesive sheet (35) having a plurality of adhesive areas (30), comprising the steps of loading the particles (12) onto the adhesive sheet (35) and transferring kinetic energy from a mechanical device (39) to the particles (12) for moving the particles (12) is disclosed. The adhesive sheet (35) may be composed of an adhesive coating (22) laminated to a film (24). The particles (12) may be composed of a variety of materials, including minerals and compounds such as solder or polymers.

Abstract: A microelectronic package (10) is formed by placing a lead frame (22) onto an adhesive polyimide tape (38). The lead frame (22) includes a plurality of metallic leads (16) and an opening. An integrated circuit die (12) is positioned onto the molding support (38) within the opening such that a non-active face (32) of the integrated circuit die (12) rests against the molding support (38). Wire leads (18) connect an active face (28) of the integrated circuit die (12) to the metallic leads (16). A plurality of metallic bumps (20) are attached to the metallic leads (16), and a polymeric precursor is dispensed. The precursor embeds the active face (28) of the integrated circuit die (12), the inner surface (19) of the metallic leads (16), the wire leads (18), and the metallic bumps (20). The microelectronic package (10) is then heated to cure the polymeric precursor to form a polymeric body (14).

Abstract: A two step wire bonding process is used to ultrasonically attach a wire (18) to a contact pad (13) on a semiconductor device (10). A first step is used to flatten a rounded tip (19) of the wire (18), and to start the bonding process. This is accomplished by applying a relatively large force to the rounded tip (19), and a relatively low vibrating displacement to the flattened wire tip (19). During a second step the large force is reduced, however; the vibrating displacement is increased. The total time for the two step wire bonding process is slightly less than a prior art one step process.

Abstract: An ovonic phase-change semiconductor memory device having a reduced area of contact between electrodes of chalcogenide memories, and methods of forming the same. Such memory devices are formed by forming a tip protruding from a lower surface of a lower electrode element. An insulative material is applied over the lower electrode such that an upper surface of the tip is exposed. A chalcogenide material and an upper electrode are either formed atop the tip, or the tip is etched into the insulative material and the chalcogenide material and upper electrode are deposited within the recess. This allows the memory cells to be made smaller and allows the overall power requirements for the memory cell to be minimized.

Abstract: A method for stripping positive photoresist from a keyhole 17 in a passivation layer 18 before a heating process using NMP solvent strips after a photoresist strip. The process is summarized by the 5 steps as follows: (1) Photoresist strip 1 (e.g., EKC 830), (2) Photoresist strip 2 (e.g., EKC 830 photoresist stripper), (3) N-methly-2-pyrolidone (NMP) solvent strip-agitated (solvent is preferably the same solvent in the photoresist stripper (1 &2) (4) NMP solvent strip-agitated and (5) H.sub.2 O rinse. The NMP solvent strip steps (3) and (4) remove photoresist residue (16, FIG. 1) in the key hole 17. This prevents the formation of photoresist extrusions 24 while annealing the metal lines 14.

Abstract: A semiconductor device comprises a semiconductor chip, an Au bump formed on the semiconductor chip, and Cu lead bonded to the Au bump through a bonding part. The Cu lead has a Cu core and a plated Sn layer formed on the Cu core, and the bonding part is formed of an Au-rich Au--Cu--Sn alloy of a ternary system having a single-phase structure containing 15 at. % or less Sn and 25 at. % or less Cu.

Abstract: A method of bumping a semiconductor device, including the steps of providing a semiconductor device (100) having a plurality of bumping sites (104), providing a plurality of solder spheres (210), providing a stencil (200) having a plurality of stencil sites (202), each stencil site (202) having a depression and a through hole (204) extending through the stencil(200), placing the plurality of solder spheres (210) on the stencil such that each stencil site of the plurality of stencil sites (202) holds a single solder sphere of the plurality of solder spheres (210), applying a vacuum to the plurality of solder spheres (210), through the vacuum through holes (204), aligning the plurality of solder spheres (210) with the plurality of bumping sites (104) of the semiconductor device (100), releasing the vacuum to release the plurality of solder spheres (210) from the stencil (200) such that the plurality of solder spheres (210) is placed on the plurality of bumping sites (104), and reflowing the plurality of solder

Abstract: A PBGA package includes PBGA member, a stiffener ring, and a stiffener fixture which includes a retaining recess having a floor for receiving the stiffener ring and includes a ledge positioned above the recess floor for receiving the PBGA member. An adhesive layer is applied to the stiffener ring, which is adhered to the PBGA member. The stiffener ring and PBGA member are essentially coplanar to less than 8 mils. A top plate is placed on top of the PBGA member and the ring and member are secured together tightly.

Abstract: A method and apparatus for attaching a semiconductor device to a substrate. One end of the substrate is elevated to position the substrate and the coupled semiconductor device on an inclined plane. An underfill material is introduced along a wall of the semiconductor device located at the elevated end of the inclined substrate with the underfill material being placed between the substrate and the semiconductor device. An optional but preferred additional step of the invention includes coupling a barrier means to the substrate at a point on the substrate adjacent to a sidewall of the semiconductor device located at the lowest point of the slope created by the inclined substrate. The barrier means prevents the underfill material from spreading beyond the sidewalls of the semiconductor device, particularly in instances where the substrate is inclined at a steep angle.

Abstract: In a lead frame flash removing method and apparatus, a lead frame is molded integrally with a case. After molding, abrasive agent-mixed water is sprayed to a surface of the lead frame where a flash is formed. The lead frame is dipped in an electrolytic solution and applying a DC voltage is applied across the lead frame and an electrode in the electrolytic solution, thereby electrolytically processing the lead frame. After the electrolytic process, an external force is applied to the surface of the lead frame, thereby removing the flash.

Abstract: A process for detachment and removal of microscopic contaminant particles from a surface includes a pulsed detach light directed at the surface to excite a contaminant particle thereon at or near its resonant frequency, to thereby detach the particle from the surface; and a photophoresis light directed at the particle to move it by photophoresis, to thereby prevent its reattachment to the surface. A thermal gradient may also be applied to control the velocity and direction of particle movement by thermophoresis. Detach light is of variable pulse frequency and angle of incidence.

Abstract: A semiconductor die is mounted to a die receiving area, which is defined by inner ends of conductive leads to which the die is connected. The die is temporarily retained in a substantially fixed position relative to the die receiving area by various techniques for the purpose of permitting bond wires to be attached between the conductive leads and the die. Preferred techniques include employing a mechanical chuck, dispensing an adhesive between the die and its die receiving area, and forming an ultrasonic bond between the die and the die receiving area. Once electrical connections between the die and the conductive lines are formed, the die need not be retained in a fixed position, as the electrical connections will provide sufficient support for the die. Accordingly, conventional die attach techniques, which expose the semiconductor die to substantially elevated temperatures, are avoided.

Abstract: A die attach procedure for SiC uses the scrubbing technique to bond a SiC die to a package. A first layer is formed on the SiC die. This first layer, preferably of nickel, bonds to the SiC die. A second layer, preferably amorphous silicon, is then formed on the first layer. The second layer bonds to the first layer, and forms a eutectic with the material, usually gold, plating the package when the SiC die is scrubbed onto the package.

Abstract: A method and apparatus for vertically interconnecting stacks of silicon segments. Each segment includes a plurality of adjacent die on a semiconductor wafer. The plurality of die on a segment are interconnected on the segment using one or more layers of metal interconnects which extend to all four sides of the segment to provide edge bonding pads for external electrical connection points. After the die are interconnected, each segment is cut from the backside of the wafer using a bevel cut to provide four inwardly sloping edge walls on each of the segments. After the segments are cut from the wafer, the segments are placed on top of one another to form a stack. Vertically adjacent segments in the stack are electrically interconnected by applying electrically conductive epoxy to all four sides of the stack.