Abstract: In an embodiment, a package includes: a first redistribution structure; a first integrated circuit die connected to the first redistribution structure; a ring-shaped substrate surrounding the first integrated circuit die, the ring-shaped substrate connected to the first redistribution structure, the ring-shaped substrate including a core and conductive vias extending through the core; a encapsulant surrounding the ring-shaped substrate and the first integrated circuit die, the encapsulant extending through the ring-shaped substrate; and a second redistribution structure on the encapsulant, the second redistribution structure connected to the first redistribution structure through the conductive vias of the ring-shaped substrate.

Abstract: A method for forming a semiconductor device includes receiving a first bonded to a second substrate by a dielectric layer, wherein a conductive layer is disposed in the dielectric layer and a cavity is formed between the first substrate, the second substrate and the dielectric layer; forming a via opening in the second substrate to expose the conductive layer and a vent hole in the substrate to couple to the cavity; forming a first buffer layer covering sidewalls of the via opening and a second buffer layer covering sidewalls of the vent hole; and forming a connecting structure in the via opening and a sealing structure to seal the vent hole.

Abstract: A pre-soldered circuit carrier includes a carrier having a metal die attach surface, a plated solder region on the metal die attach surface, wherein a maximum thickness of the plated solder region is at most 50 ?m, the plated solder region has a lower melting point than the first bond pad, and the plated solder region forms one or more intermetallic phases with the die attach surface at a soldering temperature that is above the melting point of the plated solder region.

Abstract: Embodiments of the disclosure include a mask apparatus used in an optical sensing system. The apparatus may include an optical encoding mask configured to facilitate a scanning procedure of the optical sensing system, wherein the scanning procedure comprises a plurality of scanning lines. The apparatus may further include an actuator coupled to the optical encoding mask and configured to generate a force to drive the optical encoding mask to resonate in a direction perpendicular to the scanning lines during the scanning procedure.

Abstract: A semiconductor package includes a redistribution substrate having first and second surfaces, a first semiconductor chip on the first surface, external terminals on the second surface, a second semiconductor chip above the first semiconductor chip, external connection members below the second semiconductor chip, conductive pillars electrically connecting the external connection members to the redistribution substrate. The second semiconductor chip includes a device layer, a wiring layer, and a redistribution layer on a semiconductor substrate. The wiring layer includes intermetallic dielectric layers, wiring lines, and a conductive pad connected to an uppermost wiring line. The redistribution layer includes a first redistribution dielectric layer, a first redistribution pattern, and a second redistribution dielectric layer. A vertical distance between the semiconductor substrate and the conductive pillars is less than that between the first semiconductor chip and the external terminals.

Abstract: A method for forming the conductive layer includes: providing a first conductive film and a solution with a conductive material; coating a surface of the first conductive film with the solution, before performing the coating, a temperature of the first conductive film being lower than an evaporation temperature or a sublimation temperature of the solution; and in a process step of performing the coating or after performing the coating, heating the first conductive film, such that the temperature of the first conductive film is higher than or equal to the evaporation temperature or the sublimation temperature of the solution, and forming a second conductive film covering the surface of the first conductive film, wherein the second conductive film including the conductive material.

Abstract: There is provided herein a resin composition comprising: (i) a silane coupling agent of the general formula (I): as described herein, and (ii) at least one resin which is interactive with one or more of the R1, R2 and X groups of silane coupling agent (i) wherein: R1 and R2 each represent a hydrogen atom or a monovalent organic group having 1 to 40 carbon atoms; R3 is independently a monovalent group selected from the group consisting of a straight chain alkyl containing from 1 to 12 carbon atoms, a branched chain alkyl containing from 3 to 12 carbon atoms, a cycloalkyl containing from 5 or 6 carbon atoms, an alkenyl containing from 2 to 12 carbon atoms, an aryl group containing 6 carbon atoms, or aralkyl containing from 7 to 12 carbon atoms, a straight chain alkyl containing 2 to 12 carbon atoms and a hydroxyl group, a branched chain alkyl containing 3 to 6 carbon atoms and a hydroxyl group, an alkyl group containing at least one oxygen atom having the structure: —R5—(OCH2CH2)m(OCH2CH(CH3))nOR6, an

Abstract: The present disclosure provides a packaging method and packaging structure of an FBAR. A second cavity in a resonator cover provided includes a groove in a second substrate and a space surrounded by an elastic bonding material layer. The elastic bonding material layer bonds the resonator cover to a resonant cavity main structure, and elasticity of the elastic bonding material layer is removed after the bonding. Through holes and a conductive interconnection layer on inner surfaces of the through holes are formed on the resonator cover. Since the second cavity includes the groove in the second substrate and the space surrounded by the elastic bonding material layer, which can avoid problems that performance of the elastic bonding material layer is unstable with temperature and humidity changes when the second cavity is entirely surrounded by the elastic bonding material layer, that is, the stability of the resonator is improved.

Abstract: The surface emitting laser device according to the embodiment includes a substrate, a first metal layer disposed on the substrate, a second metal layer disposed on the first metal layer, and a third metal layer disposed between the first metal layer and the second metal layer. The first to third metal layers may include different materials, and the second metal layer may include copper (Cu). The third metal layer may prevent diffusion of copper from the second metal layer into the first metal layer.

Abstract: A LED device includes multiple LED chips each including opposite first and second surfaces, a side surface, and an electrode assembly disposed on the second surface and including first and second electrodes. The first surface of each of the LED chips is a light exit surface. The LED device further includes an electric circuit layer assembly disposed on the second surfaces of the LED chips and having opposite first and second surfaces and a side surface. The first surface is electrically connected to the first and second electrodes. The LED device further includes an encapsulating layer enclosing the LED chips and the electric circuit layer assembly to expose the second surface of the electric circuit layer assembly.

Abstract: A ball grid array (BGA) assembly can include a component substrate having at least one underfill channel defined therethrough providing fluidic communication between a first side of the component substrate and a second side of the component substrate, a plurality of pads or leads exposed on the second side and configured to be soldered to a mating PCB, a cover mounted to the component substrate defining a reservoir cavity between the first side and the cover, and an underfill material disposed within the reservoir cavity such that the underfill material can flow through the at least one underfill channel to a gap defined between the second side and the mating PCB when the component substrate is being soldered to the mating PCB.

Abstract: A device for controlling trapped ions includes a first semiconductor substrate. A second semiconductor substrate is disposed over the first semiconductor substrate. At least one ion trap is configured to trap ions in a space between the first semiconductor substrate and the second semiconductor substrate. A spacer is disposed between the first semiconductor substrate and the second semiconductor substrate, the spacer including an electrical interconnect which electrically connects a first metal layer structure of the first semiconductor substrate to a second metal layer structure of the second semiconductor substrate.

Abstract: The present invention features a system and manufacturing arrangement for multiple die chips onto a receiver substrate. The system includes a donor chuck; a receiver chuck configured for supporting the receiver substrate; a pick and place gripper mechanism configured for retrieving a die chip supported on the donor chuck; a gang carrier configured for receiving the die chip from the gripper mechanism; a flipper mechanism configured for delivering the die chip in an inverted orientation relative to the orientation of the die chip when received by the gang carrier; and computer controlled interconnected inspection cameras configured for ensuring accurate alignment of the receiver substrate relative to the die chip in the inverted orientation. The gang carrier has a thermocouple controlled heating element therein to maintain a proper computer controlled temperature therewithin.

Abstract: In some examples, a sensor package includes a semiconductor die having a sensor; a mold compound covering a portion of the semiconductor die; and a cavity formed in a top surface of the mold compound, the sensor being in the cavity. The sensor package includes an adhesive abutting the top surface of the mold compound, and a semi-permeable film abutting the adhesive and covering the cavity. The semi-permeable film is approximately flush with at least four edges of the top surface of the mold compound.

Abstract: Methods of manufacturing a semiconductor chip are provided. The methods may include providing a semiconductor substrate including integrated circuit regions and a cut region. The cut region may be between the integrated circuit regions. The methods may also include forming a modified layer by emitting a laser beam into the semiconductor substrate along the cut region, polishing an inactive surface of the semiconductor substrate to propagate a crack from the modified layer, and separating the integrated circuit regions along the crack. The cut region may include a plurality of multilayer metal patterns on an active surface of the semiconductor substrate, which is opposite to the inactive surface of the semiconductor substrate. The plurality of multilayer metal patterns may form a pyramid structure when viewed in cross section.

Abstract: A semiconductor package that includes a support wiring structure. A semiconductor chip is on the support wiring structure. A cover wiring structure is on the semiconductor chip. A plurality of connection structures penetrates a filling member and electrically connects the support wiring structure to the cover wiring structure. The filling member fills a space between the support wiring structure and the cover wiring structure. The filling member surrounds the plurality of connection structures and the semiconductor chip and includes a plurality of fillers. A partial portion of the plurality of fillers includes cutting fillers having a flat surface that extends along a vertical level that is a reference level.

Abstract: A semiconductor package comprising a package substrate that extends in a first direction and a second direction perpendicular to the first direction, a plurality of logic dies and a memory stack structure on the package substrate, and an interposer substrate mounted in the package substrate. The memory stack structure vertically overlaps the interposer substrate. Each of the logic dies includes a first part that is horizontally offset from the interposer substrate and a second part that vertically overlaps the interposer substrate. The interposer substrate includes an interlayer dielectric layer and a plurality of wiring lines in the interlayer dielectric layer. The memory stack structure is electrically connected to at least one of the logic dies through the wiring lines of the interposer substrate.

Abstract: An additively manufactured component and a method for manufacturing the same are provided. The additively manufactured component includes a cross sectional layer having a surface surrounding the cross sectional layer. The cross sectional layer is formed by moving a focal point of an energy source over a bed of additive material. A surface irregularity is formed on the surface by manipulating the energy level of the energy source. The surface may include a datum feature positioned at a predetermined location relative to the surface irregularity and the surface irregularity may be greater than a surface roughness of the surface but less than one millimeter.

Abstract: Embodiments of the disclosure include a receiver of an optical sensing system. The receiver may include a Hadamard mask configured to resonate during a scanning procedure performed by the optical sensing system. The Hadamard mask may include a frame beginning pattern corresponding to a start of a frame captured during the scanning procedure. The Hadamard mask may also include a coded pattern configured to provide sub-pixelization of the frame. The receiver may also include a photodetector array positioned on a first side of the Hadamard mask. The photodetector array may be configured to detect light that passes through the Hadamard mask during the scanning procedure to generate the frame.

Abstract: A chip package structure includes at least one semiconductor die attached to a redistribution structure, a first underfill material portion located between the redistribution structure and the at least one semiconductor die and laterally surrounding the solder material portions, a molding compound laterally surrounding at least one semiconductor die, and a second underfill material portion contacting sidewalls of the redistribution structure and sidewalls of the molding compound and including at least one cut region. The second underfill material portion includes a vertically-extending portion having a uniform lateral width and a horizontally-extending portion having a uniform vertical thickness and adjoined to a bottom end of the vertically-extending portion within each of the at least one cut region.

Abstract: A semiconductor package includes: a redistribution substrate; a frame including first and second vertical connection conductors, and having a through-hole; first and second semiconductor chips; an encapsulant; a second redistribution structure disposed on the encapsulant, a conductive wire electrically connecting the second semiconductor chip and the second vertical connection conductor; and a vertical connection via penetrating a portion of the encapsulant, and electrically connecting the second redistribution structure and the first vertical connection conductor. The first semiconductor chip is connected to the second vertical connection conductor by the first redistribution structure.

Abstract: A semiconductor device and a method of manufacturing a semiconductor device. For example, various aspects of this disclosure provide a semiconductor device having an ultra-thin substrate, and a method of manufacturing a semiconductor device having an ultra-thin substrate. As a non-limiting example, a substrate structure comprising a carrier, an adhesive layer formed on the carrier, and an ultra-thin substrate formed on the adhesive layer may be received and/or formed, components may then be mounted to the ultra-thin substrate and encapsulated, and the carrier and adhesive layer may then be removed.

Abstract: A system for calibrating an equipment, the system including a beam splitter; a first reticle configured to be removably attached to the equipment; and an image capture device including an image plane, wherein an image of the first reticle is configured to be received by way of the beam splitter at the image plane along an optical axis of the beam splitter, wherein the orientation as indicated by the first reticle is compared to an orientation of the image plane and if the orientation as indicated by the first reticle differs from the orientation of the image plane, the equipment is rotated about the optical axis of the beam splitter such that the orientation as indicated by the first reticle matches the orientation of the image plane.

Abstract: A packaging method and a packaging structure of a film bulk acoustic resonator are provided. The packaging method includes: providing a resonant cavity main structure including a first substrate and a film bulk acoustic resonant structure having a first cavity formed therebetween; forming a resonator cover by providing a second substrate and forming an elastic bonding material layer containing a second cavity; bonding the resonant cavity main structure and the resonator cover together through the elastic bonding material layer and removing elasticity of the elastic bonding material layer, where the second cavity is at least partially aligned with the first cavity; forming a through-hole penetrating through the resonator cover and exposing a corresponding electrical connection part of the film bulk acoustic resonant structure; and forming a conductive interconnection layer on a sidewall of the through-hole and on a portion of a surface of the resonator cover.

Abstract: Discussed is an apparatus for self-assembling semiconductor light-emitting devices, the apparatus including a fluid chamber to accommodate the semiconductor light-emitting devices, each semiconductor light-emitting device having a magnetic body; a magnet to apply a magnetic force to the semiconductor light-emitting devices while an assembly substrate is disposed at an assembly position of the self-assembly apparatus; a power supply to induce formation of an electric field on the assembly substrate to allow the semiconductor light-emitting devices to be seated at a preset positions on the assembly substrate in a process of moving the semiconductor light-emitting devices due to a change in a position of the magnet; and a fluid injector to shoot a fluid to some of the semiconductor light-emitting devices to allow the some of the semiconductor light-emitting devices seated on the assembly substrate to be separated from the assembly substrate.

Abstract: A thin film transistor substrate includes: a substrate, a first electrode disposed on the substrate, a bank disposed on the substrate and having an inclined surface inclined at an angle with respect to the substrate, a second electrode disposed on the bank, an active pattern electrically connected to the first electrode and the second electrode, disposed on the inclined surface, and including a first conductive region and a second conductive region in which impurities are doped, and a channel region between the first conductive region and the second conductive region, and a gate electrode overlapping at least a portion of the channel region of the active pattern. The inclined surface extends in a first direction in a plan view. The first conductive region, the channel region, and the second conductive region are sequentially disposed on the inclined surface along a second direction that crosses the first direction.

Abstract: In certain embodiments, a system includes: an inspection station configured to receive a die vessel, wherein the inspection station is configured to inspect the die vessel for defects; a desiccant station configured to receive the die vessel from the inspection station, wherein the desiccant station is configured to add a desiccant to the die vessel; a bundle station configured to receive the die vessel from the desiccant station, wherein the bundle station is configured to combine the die vessel with another die vessel as a die bundle; and a bagging station configured to receive the die bundle from the bundle station, wherein the bagging station is configured to dispose the die bundle in a die bag and to heat seal the die bag with the die bundle inside.

Abstract: A package substrate includes a substrate, an insulating protective layer and an interposer. The substrate has a first surface and a second surface opposing to the first surface. The substrate includes a plurality of first conductive pads embedded in the first surface. The insulating protective layer is disposed on the first surface of the substrate. The insulating protective layer has an opening for exposing the first conductive pads embedded in the first surface of the substrate. The interposer has a top surface and a bottom surface opposing to the top surface. The interposer includes a plurality of conductive vias and a plurality of second conductive pads located on the bottom surface. The interposer is located in a recess defined by the opening of the insulating protective layer and the first surface of the substrate. Each of the second conductive pads is electrically connected to corresponding first conductive pad.

Abstract: A micro-transfer structure comprises a stamp comprising a rigid support, only a single contiguous bulk layer disposed on the rigid support, and posts disposed on the bulk layer. Components are adhered to (e.g., disposed in contact with) some but not all of the posts. The posts can be substantially identical and disposed in a regular array on the bulk layer. Each component is adhered to (e.g., in contact with) two or more posts. Components can be disposed on a source wafer entirely over sacrificial portions of a sacrificial layer on or in the source wafer and attached to anchors disposed between sacrificial portions with a tether.

Abstract: A semiconductor device including a semiconductor chip having a first conduction element; a substrate having second and third conduction elements; and external connection elements configured to form an electrical path between the second and third conduction elements via the first conduction element.

Abstract: A surface acoustic wave (SAW) device including a substrate is provided. Multiple surface acoustic wave elements are disposed on the substrate. A conductive surrounding structure includes: a wall part, disposed on the substrate and surrounding the surface acoustic wave elements; and a lateral layer part, disposed on the wall part. The lateral layer part has an opening above the surface acoustic wave elements. A cap layer covers the lateral layer part and closes the opening.

Abstract: The invention relates to a geometric design and corresponding methods for components 22, which are produced on a carrier substrate 10 and prepared by detachment in an etching process 30 for a subsequent absorption and a transfer with a stamp for application to a further substrate. The components 22 are designed in such a way that additional active surfaces are provided for the etching process 30 for undercut the components, so that a faster, more reliable and more homogeneous etching profile is achieved.

Abstract: Semiconductor devices and methods of manufacture are provided, in which an adhesive is removed from a semiconductor die embedded within an encapsulant, and an interface material is utilized to remove heat from the semiconductor device. The removal of the adhesive leaves behind a recess adjacent to a sidewall of the semiconductor, and the recess is filled.

Abstract: An apparatus includes a substrate, a frame, and a socket. The frame defines a slot. The frame is coupled to the substrate such that the slot is aligned with an attachment location on the substrate. The socket receives a first device. The socket aligns with the attachment location on the substrate when the socket is inserted in the slot.

Abstract: A package device and a manufacturing method thereof are provided. The package device includes a redistribution layer. The redistribution layer includes a first dielectric layer, a conductive layer, and a second dielectric layer, and the conductive layer is disposed between the first dielectric layer and the second dielectric layer, wherein the redistribution layer has a test mark, the test mark includes a conductive pattern formed of the conductive layer, the conductive pattern includes a center portion and a plurality of extension portions, and the plurality of extension portions are respectively connected to the center portion.

Abstract: A method for forming a gate structure of a 3D memory device is provided. The method comprises: forming a plurality of hybrid shallow trench isolation structures in a substrate, each hybrid shallow trench isolation structure comprising a dielectric sublayer and a conductive sublayer, both of which are embedded in the substrate; forming an alternating dielectric stack on the substrate; forming a slit penetrating vertically through the alternating dielectric stack and extending in a horizontal direction to expose a row of hybrid shallow trench isolation structures; forming a plurality of array common source contacts in the slit, each array common source contact being in electric contact with a corresponding hybrid shallow trench isolation structure.

Abstract: A semiconductor device package includes an embedded plurality of solder balls within an integrated circuit die (ICD) substrate In one embodiment, the integrated circuit die (ICD) substrate has a top surface and a bottom surface, and a plurality of solder balls at least partially embedded in the ICD substrate, where each of the plurality of solder balls comprises an exposed surface that is substantially flat and parallel planar to the bottom surface, and where the exposed surface of each of the plurality of solder balls is disposed in the bottom surface. In certain examples, the apparatuses also include a plurality of integrated circuit dies stacked on the top surface of the ICD substrate.

Abstract: An encapsulant compound apparatus, includes a mechanical operator, and an insert disposed on a surface of the mechanical operator. The insert operates to capture foreign material in the encapsulant compound.

Abstract: Methods, systems, and apparatus for using antennas for millimeter wave contactless communication. One of the apparatuses is a communication device that includes a transducer configured to convert electrical signals into extremely high frequency (EHF) electromagnetic signals, the EHF electromagnetic signals substantially emitted from a first surface of the communication device, wherein the transducer is positioned on a substrate of the communication device, and an integrated circuit coupled to the substrate, wherein the transducer includes multiple parallel resonant antenna elements in an array.

Abstract: A method of repairing a light emitting device, comprises: providing a light emitting device comprising a carrier board and a first light emitting unit; destroying the first light emitting unit and forming a removal surface on the light emitting device; planarizing the removal surface; providing a bonding structure on the removal surface; and fixing a second light emitting unit on the planarized removal surface through the bonding material.

Abstract: A manufacturing method of a semiconductor package is provided. The manufacturing method includes the following. A plurality of semiconductor components are provided. Each semiconductor component has at least one conductive bump. A substrate is provided. The substrate has a plurality of conductive pads. A transfer device is provided. The transfer device transfers the semiconductor components onto the substrate. A heating device is provided. The heating device heats or pressurizes at least two semiconductor components. During transferring of the semiconductor components to the substrate, the at least one conductive bump of each semiconductor component is docked to a corresponding one of the conductive pads.

Abstract: A processing apparatus includes a wafer conveying-out mechanism; a wafer table; a frame conveying-out mechanism; a frame table; a tape attaching mechanism that attaches a tape to a frame; a tape-attached frame conveying mechanism that conveys the tape-attached frame; a tape pressure bonding mechanism that pressure bonds the tape of the tape-attached frame to a back surface of a wafer; a frame unit conveying-out mechanism that conveys out a frame unit in which the tape of the tape-attached frame and the back surface of the wafer are pressure bonded; a reinforcement section removing mechanism that cuts and removes a ring-shaped reinforcement section from the wafer; a ringless unit conveying-out mechanism that conveys out a ringless unit from which the reinforcement section has been removed; and a frame cassette table on which a frame cassette accommodating the ringless unit is to be placed.

Abstract: Embodiments of 3D memory devices and the fabrication methods to form the 3D memory devices are provided. A 3D memory device includes a substrate, a memory deck, and a memory string. The memory deck includes a plurality of interleaved conductor layers and dielectric layers on the substrate. The memory string extends vertically through the memory deck. A bottom conductor layer of the plurality of interleaved conductor layers and dielectric layers can intersect with and contact the memory string.

Abstract: An IC package includes a heat-generating device and an electrical device on a surface of a substrate, a mold compound disposed on the electrical device, and a thermal structure disposed on the heat-generating device, without the mold compound, to improve heat dissipation. In an example, the thermal structure includes a thermal interface material (TIM) layer and a heat sink. In the example, the TIM layer extends from the heat-generating device to a height equal to or less than the mold compound and the heat sink includes a planar exterior surface above the heat-generating device and the electrical device. In an example, a first heat sink portion of the heat sink on the heat-generating device may be a different thickness than a second heat sink portion of the heat sink on the electrical device. The thermal structure reduces a thermal resistance between the heat-generating device and the heat sink.

Abstract: A method for manufacturing electronic apparatus includes: a step (A) of preparing a structure provided with an adhesive film and one or two or more electronic components affixed to an adhesive surface of the adhesive film; a step (B) of disposing the structure in the electronic component testing apparatus such that the electronic component is positioned over an electronic component installation region of a sample stand of the electronic component testing apparatus in a defined manner; a step (C) of evaluating the properties of the electronic component in a state of being affixed to the adhesive film with the probe terminal being in contact with a terminal of the electronic component; and a step (D) of picking up the electronic component from the adhesive film after the step (C). A defined sample stand is also provided.

Abstract: A method for forming a semiconductor device package is provided. The method includes bonding a semiconductor device to a package substrate; placing a metal lid over the semiconductor device and the package substrate with a metal thermal interface material (TIM) provided between the metal lid and the semiconductor device; heating the metal TIM to melt the metal TIM; pressing the metal lid downward so that the molten metal TIM flows toward the boundary of the semiconductor device, and the outermost point of the lateral sidewall of the molten metal TIM extends beyond the boundary of the semiconductor device; lifting the metal lid upward so that the molten metal TIM flows back, and the outermost point of the lateral sidewall is within the boundary of the semiconductor device; and bonding the metal lid to the semiconductor device through the metal TIM by curing the molten metal TIM.

Abstract: A semiconductor device has a substrate including a terminal and an insulating layer formed over the terminal. An electrical component is disposed over the substrate. An encapsulant is deposited over the electrical component and substrate. A portion of the insulating layer over the terminal is exposed from the encapsulant. A shielding layer is formed over the encapsulant and terminal. A portion of the shielding layer is removed to expose the portion of the insulating layer. The portion of the insulating layer is removed to expose the terminal. The portion of the shielding layer and the portion of the insulating layer can be removed by laser ablation.

Abstract: Microelectronic assemblies, related devices, and methods are disclosed herein. In some embodiments, a microelectronic assembly may include a die having a first surface and an opposing second surface; a capacitor having a surface, wherein the surface of the capacitor is coupled to the first surface of the die; and a conductive pillar coupled to the first surface of the die. In some embodiments, a microelectronic assembly may include a capacitor in a first dielectric layer; a conductive pillar in the first dielectric layer; a first die having a surface in the first dielectric layer; and a second die having a surface in a second dielectric layer, wherein the second dielectric layer is on the first dielectric layer, and wherein the surface of the second die is coupled to the capacitor, to the surface of the first die, and to the conductive pillar.

Abstract: A communication control circuit for a power supply chip, can include: a main control die having a main control circuit; a plurality of sub-control dice configured to respectively receive a control signal sent by the main control die, where each sub-control die comprises a sub-control circuit; and where a reference ground of each sub-control die is different from a reference ground of the main control die, the reference grounds of the plurality of sub-control dice are different with each other, and communication between the main control die and each sub-control die is achieved by a corresponding level conversion circuit.

Abstract: Described herein is a die-to-wafer bonding process that utilizes micro-transfer printing to transfer die from a source wafer onto an intermediate handle wafer. The resulting intermediate handle wafer structure can then be bonded die-down onto the target wafer, followed by removal of only the intermediate handle wafer, leaving the die in place bonded to the target wafer.