Packaging (e.g., With Mounting, Encapsulating, Etc.) Or Treatment Of Packaged Semiconductor Patents (Class 438/106)
  • Patent number: 10700037
    Abstract: In some examples, a device includes a semiconductor element, a layer element, and a single connector element electrically connecting the semiconductor element and the layer element. In some examples, the single connector element includes two or more discrete connector elements, and each discrete connector element of the two or more discrete connector elements electrically connects the semiconductor element and the layer element. In some examples, the single connector element also includes conductive material attached to the two or more discrete connector elements.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: June 30, 2020
    Assignee: Infineon Technologies AG
    Inventors: Eung San Cho, Thorsten Meyer, Xaver Schloegel, Thomas Behrens, Josef Hoeglauer
  • Patent number: 10700032
    Abstract: An embodiment is a device comprising a substrate, a metal pad over the substrate, and a passivation layer comprising a portion over the metal pad. The device further comprises a metal pillar over and electrically coupled to the metal pad, and a passive device comprising a first portion at a same level as the metal pillar, wherein the first portion of the passive device is formed of a same material as the metal pillar.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: June 30, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shuo-Mao Chen, Der-Chyang Yeh, Li-Hsien Huang
  • Patent number: 10692764
    Abstract: A device includes a substrate, and an alignment mark including a conductive through-substrate via (TSV) penetrating through the substrate.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: June 23, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsin Chang, Fang Wen Tsai, Jing-Cheng Lin, Wen-Chih Chiou, Shin-Puu Jeng
  • Patent number: 10693020
    Abstract: An optical detector device including: a glass substrate having conductive traces plated thereon; a semiconductor device having an optical detector exposed on a side facing the glass substrate, the semiconductor device further including a plurality of bond pads electrically coupled to a first subset of the conductive traces; a metallic seal structure bonding a side of the glass substrate having the conductive traces with the side of the semiconductor device facing the glass substrate; and a plurality of conductive structures outside of a perimeter of the semiconductor device, the plurality of conductive structures being electrically coupled to a second subset of the conductive traces.
    Type: Grant
    Filed: June 1, 2018
    Date of Patent: June 23, 2020
    Assignee: TT ELECTRONICS PLC
    Inventors: Virgil Cotoco Ararao, Brent Hans Larson
  • Patent number: 10672631
    Abstract: A method and a system for thinning a substrate are provided. The method includes at least the following steps. A liquid seal is provided at an interface between a chuck and a substrate disposed on the chuck. The substrate is thinned during the liquid seal is provided.
    Type: Grant
    Filed: August 15, 2018
    Date of Patent: June 2, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Chao Mao, Chin-Chuan Chang, Szu-Wei Lu
  • Patent number: 10665549
    Abstract: A fan-out semiconductor package includes: a frame, including a wiring layer, and having a through-hole; a semiconductor chip disposed in the through-hole, and including a connection pad; an encapsulant covering at least a portion of each of the frame and an inactive surface of the semiconductor chip, and having a first opening exposing at least a portion of the wiring layer; an insulating layer disposed on the encapsulant, and having a second opening formed in the first opening to expose at least a portion of the wiring layer; a conductive pattern layer disposed on the insulating layer; a conductive via disposed in the second opening; and a connection structure disposed on the frame and an active surface of the semiconductor chip, and including one or more redistribution layers. The conductive pattern layer and the redistribution layer are electrically connected to the connection pad.
    Type: Grant
    Filed: February 6, 2019
    Date of Patent: May 26, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung Hawn Bae, Jung Soo Kim, Won Choi, Sung Hoan Kim
  • Patent number: 10654712
    Abstract: A micro electro mechanical system (MEMS) microphone includes a base including a port extending through the base, a shim assembly, an ingress protection element, and a MEMS device. The shim assembly is disposed on the base and over the port. The shim assembly has a plurality of walls that form a hollow interior cavity. The shim assembly also has a top surface and a bottom surface coupled to the base. The ingress protection element extends over and is coupled to the top of the shim assembly to enclose the cavity of the shim assembly. The shim assembly elevates the ingress protection element above the base and is effective to prevent the passage of contaminants there through. The MEMS device includes a diaphragm and a back plate and is disposed over the ingress protection element.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: May 19, 2020
    Assignee: Knowles Electronics, LLC
    Inventors: John J. Albers, Brandon Harrington, Sung Bok Lee
  • Patent number: 10651102
    Abstract: An electronic assembly that includes an electronic component; and an interposer that includes a body having upper and lower surfaces and side walls extending between the upper and lower surfaces, the interposer further including conductive routings that are exposed on at least one of the side walls, wherein the electronic component is connected directly to the interposer. The conductive routings are exposed on each side wall and on the upper and lower surfaces. The electronic assembly may further includes a substrate having a cavity such that the interposer is within the cavity, wherein the cavity includes sidewalls and substrate includes conductive traces that are exposed from the sidewalls of the cavity, wherein the conductive traces that are exposed from the sidewalls of the cavity are electrically connected directly to the conductive routings that are exposed on at least one of the side walls of the interposer.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: May 12, 2020
    Assignee: Intel IP Corporation
    Inventors: Klaus Reingruber, Christian Geissler, Georg Seidemann, Sonja Koller
  • Patent number: 10651126
    Abstract: A wafer-level bridge die is affixed with an adhesive layer to a redistribution layer (RDL) that has been temporarily bonded to a carrier. Electrical interconnects are formed on the RDL and on the bridge die and encapsulated in a first mold layer. A plurality of dies are coupled to the RDL and the bridge die such that a die is electrically connected to at least one electrical interconnect of the RDL and to at least one electrical interconnect of the bridge die. A second mold layer is formed on the first mold layer to encapsulate the plurality of dies. The temporary bond is then broken and the carrier is removed, exposing the RDL connections.
    Type: Grant
    Filed: December 8, 2017
    Date of Patent: May 12, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Chien-Kang Hsiung, Arvind Sundarrajan
  • Patent number: 10636754
    Abstract: A semiconductor chip with different chip pads and a method for forming a semiconductor chip with different chip pads are disclosed. In some embodiments, a semiconductor chip includes a chip front side, a first chip pad located on the chip front side, a second chip pad located on the chip front side and an electrically insulating material located between the first chip pad and the second chip pad, wherein the first chip pad includes a surface layer predominantly comprising copper and the second chip pad includes a surface layer predominantly comprising aluminum.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: April 28, 2020
    Assignee: Infineon Technologies AG
    Inventors: Stefan Kramp, Marco Koitz
  • Patent number: 10629376
    Abstract: There are disclosed a multilayer ceramic capacitor and a method of manufacturing the same. The multilayer ceramic capacitor includes: a ceramic body having a first side and a second side opposed to each other and having a third side and a fourth side connecting the first side to the second side, a plurality of inner electrodes formed within the ceramic body, and outer electrodes formed on the third side and the fourth side and electrically connected to the inner electrodes. A distance from distal edges of the inner electrodes to the first side or the second side of the ceramic body is 30 ?m or less.
    Type: Grant
    Filed: March 21, 2018
    Date of Patent: April 21, 2020
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Hyung Joon Kim, Dae Bok Oh
  • Patent number: 10629554
    Abstract: A package structure includes a die, an encapsulant, a dam structure, and a redistribution structure. The die has an active surface and a rear surface opposite to the active surface. The encapsulant encapsulates sidewalls of the die. The encapsulant has a first surface and a second surface opposite to the first surface. The first surface is coplanar with the rear surface of the die. The second surface is located at a level height different from the active surface of the die. The dam structure is disposed on the active surface of the die. A top surface of the dam structure is substantially coplanar with the second surface of the encapsulant. The redistribution structure is over the encapsulant, the dam structure, and the die. The redistribution structure is electrically connected to the die.
    Type: Grant
    Filed: April 13, 2018
    Date of Patent: April 21, 2020
    Assignee: Powertech Technology Inc.
    Inventors: Nan-Chun Lin, Hung-Hsin Hsu
  • Patent number: 10615133
    Abstract: A die package is described that includes a substrate to carry passive components. In one example, the package has a semiconductor die having active circuitry near a front side of the die and having a back side opposite the front side, and a component substrate near the back side of the die. A plurality of passive electrical components are on the component substrate and a conductive path connects a passive component to the active circuitry. The die has a silicon substrate between the front side and the back side and the conductive path is a through-silicon via through the die from the back side to the active circuit.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: April 7, 2020
    Assignee: Intel Corporation
    Inventors: Telesphor Kamgaing, Valluri R. Rao
  • Patent number: 10573582
    Abstract: A dual leadframe (100) for semiconductor systems comprising a first leadframe (110) having first metal zones separated by first gaps, the first zones including portions of reduced thickness and joint provisions in selected first locations, and further a second leadframe (120) having second metal zones separated by second gaps, the second zones including portions of reduced thickness and joint provisions (150) in selected second locations matching the first locations. The second leadframe is stacked on top of the first leadframe and the joint provisions of the matching second and first locations linked together. The resulting dual leadframe may further include insulating material (140) filling the first and second gaps and the zone portions of reduced thickness, and has insulating surfaces coplanar with the top and bottom metallic surfaces.
    Type: Grant
    Filed: April 8, 2019
    Date of Patent: February 25, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Rajeev D. Joshi, Hau Nguyen, Anindya Poddar, Ken Pham
  • Patent number: 10566307
    Abstract: The disclosure includes: a first lifting step for bonding a wire at a first position (13) with a capillary and for lifting the capillary up to a first height H1 while feeding the wire; a circular arc lifting step for carrying out a circular arc motion for moving the capillary in a circular arc toward a second position (14) by a first distance (L5), and then carrying out a lifting motion for lifting the capillary while feeding the wire; a circular arc motion step for moving the capillary in a circular arc toward the first position (13) by a second distance (L3+L4); a second lifting step for lifting the capillary up to a second height H4; and a looping step for looping the capillary to the second position (14), thereby forming a wire loop having a predetermined height on a substrate by bonding the wire at the second position (14).
    Type: Grant
    Filed: November 2, 2016
    Date of Patent: February 18, 2020
    Assignee: SHINKAWA LTD.
    Inventors: Yuu Hasegawa, Naoki Sekine, Yoshihito Hagiwara
  • Patent number: 10559539
    Abstract: A wafer level package and or a semiconductor device unit may be provided. The wafer level package may include semiconductor chips disposed on an interconnection structure layer and laterally spaced apart from each other. The wafer level package may include a reinforcement zig attached to the semiconductor chips. The wafer level package may include a molded layer covering the semiconductor chips and embedding the reinforcement zig. Related methods are also provided.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: February 11, 2020
    Assignee: SK hynix Inc.
    Inventor: Jong Hyun Nam
  • Patent number: 10559478
    Abstract: Manufacturing method for an electronic device comprises a step of placing a substrate 10, which has a metal plate 11 on a back-surface side, on a back-surface-side mold 110 having a mold recessed part 111, a step of placing a front-surface-side mold 120 on the back-surface-side mold so as to cover the substrate 10; and a step of pouring resin between the front-surface mold 100 and the back-surface-side mold 110, when the substrate 10 is pressed against the back-surface-side mold 110. Circumferential part of the metal plate 11 is in contact with an edge of the mold recessed part 111 when the substrate 10 is pressed against the back-surface-side mold 110 in the step of pouring resin.
    Type: Grant
    Filed: December 26, 2016
    Date of Patent: February 11, 2020
    Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventor: Hideki Kamada
  • Patent number: 10559734
    Abstract: Disclosed are a light emitting device package. The light emitting device package includes a body having recess; a first lead frame including a first and second portions on a first region of the body; a second lead frame including a third and fourth portions on a second region of the body; a third lead frame between the first and second lead frame. The body has a length of the first direction greater than a width of the second direction, wherein the second portion of the first lead frame extends toward the second lead frame and has a small width, and wherein the fourth portion of the second lead frame extends toward the first lead frame. A first light emitting device is disposed on the first portion of the first lead frame and a second light emitting device is disposed on the third portion of the second lead frame.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: February 11, 2020
    Assignee: LG Innotek Co., Ltd.
    Inventor: Dong Yong Lee
  • Patent number: 10553515
    Abstract: Integrated circuit (IC) structures with extended conductive pathways, as well as related structures, devices, and methods, are disclosed herein. For example, in some embodiments, an IC structure may include a die having a device side and an opposing back side; a mold compound disposed at the back side; and a conductive pathway extending into the die from the back side and extending into the mold compound from the back side.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: February 4, 2020
    Assignee: Intel Corporation
    Inventor: Yen Hsiang Chew
  • Patent number: 10541196
    Abstract: The present disclosure is directed to a leadframe package having solder wettable sidewalls that is formed using a pre-molded leadframe and methods of manufacturing the same. A metal plated leadframe with a plurality of recesses and a plurality of apertures is placed into a top and bottom mold tool. A molding compound is then formed in the plurality of recesses and apertures in the leadframe to form a pre-molded leadframe. A plurality of die and wires are coupled to the pre-molded leadframe and the resulting combination is covered in an encapsulant. Alternatively, a bare leadframe can be processed and the metal layer can be applied after encapsulation. A saw or other cutting means is used for singulation to form leadframe packages. Each resulting leadframe package has a solder wettable sidewall for improving the strength of solder joints between the package and a circuit board.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: January 21, 2020
    Assignee: STMicroelectronics, Inc.
    Inventors: Aaron Cadag, Ernesto Antilano, Jr., Ela Mia Cadag
  • Patent number: 10532445
    Abstract: A processing apparatus includes a chuck table that holds a workpiece by a holding face, a processing unit that processes the workpiece with a grinding whetstone or a polishing pad, a movement unit for moving the chuck table and the processing unit parallel to the holding face, a processing feeding unit for moving the chuck table and the processing unit in a direction orthogonal to the holding face, an inspection unit to inspect a process mark of the workpiece during processing, a dressing unit to dress the grinding whetstone or the polishing pad of the processing unit, and a control unit. When a process mark of a size exceeding a threshold value is detected on the process face of the workpiece, the control unit stops processing of the workpiece, and after the grinding whetstone or the polishing pad is dressed, restarts processing.
    Type: Grant
    Filed: October 11, 2017
    Date of Patent: January 14, 2020
    Assignee: DISCO CORPORATION
    Inventor: Kazuma Sekiya
  • Patent number: 10535609
    Abstract: Package structures and methods for forming the same are provided. A package structure includes a package layer. The package structure also includes an integrated circuit die and a first connector embedded in the package layer. The package structure further includes a redistribution layer over the package layer. The integrated circuit die is electrically connected to the redistribution layer through the first connector. In addition, the package structure includes a passivation layer over the redistribution layer. The package structure also includes a second connector over the passivation layer. A first portion of the redistribution layer and a second portion of the second connector extend into the passivation layer. The second portion of the second connector has a tapered profile along a direction from the integrated circuit die towards the first connector.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: January 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Da Tsai, Cheng-Ping Lin, Wei-Hung Lin, Chih-Wei Lin, Ming-Da Cheng, Ching-Hua Hsieh, Chung-Shi Liu
  • Patent number: 10522446
    Abstract: In order to improve reliability of a semiconductor device, the semiconductor device includes a semiconductor chip, a die pad, a plurality of leads, and a sealing portion. The die pad and the leads are made of a metal material mainly containing copper. A plating layer is formed on a top surface of the die pad. The plating layer is formed by a silver plating layer, a gold plating layer, or a platinum plating layer. The semiconductor chip is mounted on the plating layer on the top surface of the die pad via a bonding material. The plating layer is covered by the bonding material not to be in contact with the sealing portion.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: December 31, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Atsushi Nishikizawa, Tadatoshi Danno
  • Patent number: 10524350
    Abstract: A radio-frequency (RF) module is disclosed to include a packaging substrate configured to receive a plurality of components. The RF module also includes a surface mount device (SMD) mounted on the packaging substrate, the SMD including a metal layer that faces upward when mounted. The RF module further includes an overmold formed over the packaging substrate, the overmold dimensioned to cover the SMD. The RF module further includes an opening defined by the overmold at a region over the SMD, the opening having a depth sufficient to expose at least a portion of the metal layer. The RF module further includes a conformal conductive layer formed over the overmold, the conformal conductive layer configured to fill at least a portion of the opening to provide an electrical path between the conformal conductive layer and the metal layer of the SMD.
    Type: Grant
    Filed: August 10, 2016
    Date of Patent: December 31, 2019
    Assignee: Skyworks Solutions, Inc.
    Inventors: Anthony James Lobianco, Howard E. Chen, Robert Francis Darveaux, Hoang Mong Nguyen, Matthew Sean Read, Lori Ann Deorio
  • Patent number: 10515874
    Abstract: A semiconductor device including a test pad contact and a method of manufacturing the semiconductor device are disclosed. In an embodiment, a semiconductor device may include a first metal feature and a second metal feature disposed in a single top metal layer over a substrate. A test pad may be formed over and electrically connected to the first metal feature. A first passivation layer may be formed over the second metal feature and the test pad and may cover top and side surfaces of the test pad. A first via may be formed penetrating the first passivation layer and contacting the test pad and a second via may be formed penetrating the first passivation layer and contacting the second metal feature.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: December 24, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chia Hu, Sen-Bor Jan, Hsien-Wei Chen, Ming-Fa Chen
  • Patent number: 10510576
    Abstract: A thin sheet (20) disposed on a carrier (10) via a surface modification layer (30) to form an article (2), wherein the article may be subjected to high temperature processing, as in FEOL semiconductor processing, not outgas and have the thin sheet maintained on the carrier without separation therefrom during the processing, yet be separated therefrom upon room temperature peeling force that leaves the thinner one of the thin sheet and carrier intact. Interposers (56) having arrays (50) of vias (60) may be formed on the thin sheet, and devices (66) formed on the interposers. Alternatively, the thin sheet may be a substrate on which semiconductor circuits are formed during FEOL processing.
    Type: Grant
    Filed: October 10, 2014
    Date of Patent: December 17, 2019
    Assignee: CORNING INCORPORATED
    Inventors: Darwin Gene Enicks, John Tyler Keech, Aric Bruce Shorey, Windsor Pipes Thomas, III
  • Patent number: 10511790
    Abstract: Image capturing accuracy is improved while a simple optical system is used. An image capture device includes: a polarizing filter that blocks non-transmitted light that has been in polarized light of an infrared ray radiated from a light source and has not been transmitted through an image capturing target and transmitted light that has been in the polarized light and has been transmitted through the image capturing target without diffusion inside the image capturing target, and transmits transmitted light that has been in the polarized light and has been diffused inside the image capturing target and transmitted therethrough; and an image sensor that receives the light that has been transmitted through the polarizing filter and captures an image of the image capturing target.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: December 17, 2019
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Shin Itoh, Tohru Murata, Kazuhiro Tsuchida
  • Patent number: 10510717
    Abstract: A system and method for packaging semiconductor device is provided. An embodiment comprises forming vias over a carrier wafer and attaching a first die over the carrier wafer and between a first two of the vias. A second die is attached over the carrier wafer and between a second two of the vias. The first die and the second die are encapsulated to form a first package, and at least one third die is connected to the first die or the second die. A second package is connected to the first package over the at least one third die.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Der-Chyang Yeh, Kuo-Chung Yee, Jui-Pin Hung
  • Patent number: 10504854
    Abstract: A stiffener includes a through-stiffener interconnect that couples a semiconductor package substrate to a package-on-package device. The through-stiffener interconnect is insulated by a through-stiffener dielectric within a through-stiffener contact corridor. A semiconductive die is coupled to the semiconductor package substrate and to the package-on-package device.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: December 10, 2019
    Assignee: Intel Corporation
    Inventors: Bok Eng Cheah, Seok Ling Lim, Jenny Shio Yin Ong, Jackson Chung Peng Kong
  • Patent number: 10497665
    Abstract: Provided are a flip chip laser bonding apparatus and a flip chip laser bonding method, and more particularly, to an apparatus and method for flip chip laser bonding, in which a semiconductor chip in a flip chip form is bonded to a substrate by using a laser beam. According to the flip chip laser bonding apparatus and the flip chip laser bonding method, even a semiconductor chip that is bent or is likely to bend may also be bonded to a substrate without contact failure of solder bumps by bonding the semiconductor chip to the substrate by laser bonding while pressurizing the semiconductor chip.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: December 3, 2019
    Assignee: PROTEC CO., LTD.
    Inventor: Geunsik Ahn
  • Patent number: 10483228
    Abstract: Provided are a semiconductor chip bonding apparatus and a semiconductor chip bonding method, and more particularly, to an apparatus and method of bonding a semiconductor chip to an upper surface of a substrate or another semiconductor chip. According to the semiconductor chip bonding apparatus and the semiconductor chip bonding method, productivity may be increased by quickly and accurately bonding a semiconductor chip to a substrate or another semiconductor chip.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: November 19, 2019
    Assignee: PROTEC CO., LTD.
    Inventor: Geunsik Ahn
  • Patent number: 10475666
    Abstract: A routable electroforming substrate for assembling a semiconductor package is manufactured by providing a carrier and plating a patterned first metallic layer onto the carrier which is configured to function as a surface mount pad or input/output pad in an assembled semiconductor package. A patterned second metallic layer comprising copper is plated over the first metallic layer, and a third metallic layer, which is configured for mounting a plurality of semiconductor dice, is plated over the second metallic layer. The carrier is then removed to expose the first metallic layer.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: November 12, 2019
    Assignee: ASM TECHNOLOGY SINGAPORE PTE LTD
    Inventors: Tat Chi Chan, Yiu Fai Kwan, Gio Jose Asumo Villaespin, Yu Lung Lam, Hang Ren
  • Patent number: 10475723
    Abstract: An IGBT heat dissipation structure includes a layer of IGBT chips, a bonding layer, a cold spray layer, a thermal spray layer, and a heat dissipation layer. The thermal spray layer is disposed on top of the heat dissipation layer. The cold spray layer is disposed on top of the thermal spray layer. The bonding layer is disposed on top of the cold spray layer, and the layer of IGBT chips is disposed on top of the bonding layer.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: November 12, 2019
    Assignee: Amulaire thermal technology, INC.
    Inventors: Tze-Yang Yeh, Chun-Lung Wu
  • Patent number: 10461399
    Abstract: A wafer level package with integrated antenna includes a contacting layer, a redistribution layer as well as a chip layer arranged between the contacting layer and the redistribution layer. An antenna is integrated in the redistribution layer. The antenna is shielded from the chip by means of a via, offset and provided with a reflector. Alternatively, the antenna can also be provided as antenna element in the chip layer.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: October 29, 2019
    Assignee: Fraunhofer-Gesellschaft zur Foerderung der angewandten Forschung e.V.
    Inventors: Ivan Ndip, Tanja Braun
  • Patent number: 10454241
    Abstract: An optoelectronic device includes a semiconductor substrate, having front and back sides and having at least one cavity extending from the back side through the semiconductor substrate into proximity with the front side. At least one optoelectronic emitter is formed on the front side of the semiconductor substrate in proximity with the at least one cavity. A heat-conducting material at least partially fills the at least one cavity and is configured to serve as a heat sink for the at least one optoelectronic emitter.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: October 22, 2019
    Assignee: APPLE INC.
    Inventors: Tongbi T. Jiang, Weiping Li, Xiaofeng Fan
  • Patent number: 10438802
    Abstract: A method of fabricating a semiconductor device, the method including forming a deposition active layer and a guide pattern on a semiconductor substrate such that the guide pattern delimits an exposed surface of the deposition active layer; and selectively depositing a metal-containing layer on the exposed surface of the deposition active layer exposed by the guide pattern, wherein the deposition active layer is a nonmetal layer.
    Type: Grant
    Filed: August 17, 2017
    Date of Patent: October 8, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyun Park, Naein Lee
  • Patent number: 10431509
    Abstract: A non-magnetic hermetic package includes walls that surround an open cavity, with a generally planar non-magnetic and metallic seal ring disposed in a continuous loop around upper edges of the walls; a sensitive component that is bonded within the cavity; and a non-magnetic lid that is sealed to the seal ring to close the cavity by a metallic seal.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: October 1, 2019
    Assignee: General Electric Company
    Inventors: Christopher James Kapusta, Marco Francesco Aimi
  • Patent number: 10424706
    Abstract: An LED flip chip die-bond conductive adhesive structure includes an LED flip chip and an electronic circuit board. An LED flip chip negative electrode, an LED flip chip nonmetallic region and an LED flip chip positive electrode are sequentially arranged on a lower surface of the LED flip chip from left to right; a circuit board negative electrode, a circuit board nonmetallic region and a circuit board positive electrode are sequentially arranged on an upper surface of the electronic circuit board from left to right. The LED flip chip and the electronic circuit board are fixedly connected through a thermosetting die-bond insulating adhesive bonded between the LED flip chip nonmetallic region and the circuit board nonmetallic region; and the LED flip chip positive and negative electrodes are respectively conductively connected with the circuit board positive and negative electrodes in a direct metal-metal contact manner.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: September 24, 2019
    Inventor: Jianwei Chen
  • Patent number: 10424827
    Abstract: A wafer level package with integrated antenna includes a contacting layer, a redistribution layer as well as a chip layer arranged between the contacting layer and the redistribution layer. An antenna is integrated in the redistribution layer. The antenna is shielded from the chip by means of a via, offset and provided with a reflector. Alternatively, the antenna can also be provided as antenna element in the chip layer.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: September 24, 2019
    Assignee: Fraunhofer-Gesellschaft zur Foerderung der angewandten Forschung e.V.
    Inventors: Ivan Ndip, Tanja Braun
  • Patent number: 10418351
    Abstract: Optoelectronic devices and method of forming the same include an optoelectronic component in a substrate layer. An integrated circuit chip is positioned on the substrate layer. A lens is positioned on the substrate layer directly above the optoelectronic component and above at least part of the integrated circuit chip. The lens has a cut-out portion that accommodates the integrated circuit chip.
    Type: Grant
    Filed: May 24, 2018
    Date of Patent: September 17, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Masao Tokunari
  • Patent number: 10418299
    Abstract: A semiconductor device includes a first die including a first pad and a first passivation layer, a second die including a second pad and a second passivation layer, and an encapsulant surrounding the first die and the second die. Surfaces of the first die are not coplanar with corresponding surfaces of the second die. A dielectric layer covers at least portions of the first passivation layer and the second passivation layer, and further covers the encapsulant between the first die and the second die. The encapsulant has a first surface. The dielectric layer has a second surface adjacent to the first passivation layer, the second passivation layer and the encapsulant, and further has a third surface opposite the second surface. The semiconductor device further includes a redistribution layer electrically connected to the first pad and the second pad and disposed above the third surface of the dielectric layer.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: September 17, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chung-Hsuan Tsai, Chuehan Hsieh
  • Patent number: 10410973
    Abstract: A semiconductor device and a method of manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a semiconductor device comprising one or more conductive shielding members and an EMI shielding layer, and a method of manufacturing thereof.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: September 10, 2019
    Assignee: Amkor Technology, Inc.
    Inventors: Yi Seul Han, Tae Yong Lee, Ji Yeon Ryu
  • Patent number: 10412834
    Abstract: A mounting structure includes a bonding material (106) that bonds second electrodes (104) of a circuit board (105) and bumps (103) of a semiconductor package (101), the bonding material (106) being surrounded by a first reinforcing resin (107). Moreover, a portion between the outer periphery of the semiconductor package (101) and the circuit board (105) is covered with a second reinforcing resin (108). Even if the bonding material (106) is a solder material having a lower melting point than a conventional bonding material, high drop resistance is obtained.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: September 10, 2019
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Arata Kishi, Hironori Munakata, Koji Motomura, Hiroki Maruo
  • Patent number: 10381313
    Abstract: An exemplary semiconductor device can comprise a die, a redistribution structure (RDS), an interconnect, a conductive strap, an encapsulant, and an EMI shield. The redistribution structure can comprise an RDS top surface coupled to the die bottom side. The interconnect can be coupled to the RDS bottom surface. The conductive strap can be coupled to the RDS, and can comprise a strap inner end coupled to the RDS bottom surface, and a strap outer end located lower than the RDS bottom surface. The encapsulant can encapsulate the conductive strap and the RDS bottom surface. The EMI shield can cover and contact the encapsulant sidewall and the strap outer end. Other examples and related methods are also disclosed herein.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: August 13, 2019
    Assignee: Amkor Technology, Inc.
    Inventors: Hee Sung Kim, Yeong Beom Ko, Joon Dong Kim, Dong Jean Kim, Sang Seon Oh
  • Patent number: 10381331
    Abstract: A semiconductor light emitting device (A) includes an elongated substrate (1) formed with a through-hole (11), a first, a second and a third semiconductor light emitting elements (3R, 3G, 3B) mounted on the main surface of the substrate (1), and an electrode (2R) electrically connected to the first semiconductor light emitting element (3R) and extending to the reverse surface of the substrate (1) via the through-hole (11). The first semiconductor light emitting element (3R) and the through-hole (11) are positioned between the second semiconductor light emitting element (3G) and the third semiconductor light emitting element (3B) in the longitudinal direction of the substrate (1). The second semiconductor light emitting element (3G) is arranged closer to one end of the substrate (1), whereas the third semiconductor light emitting element (3B) is arranged closer to the other end of the substrate (1).
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: August 13, 2019
    Assignee: ROHM CO., LTD.
    Inventor: Hideyuki Taguchi
  • Patent number: 10381541
    Abstract: A cryogenic electronic package includes a first superconducting multi-chip module (SMCM), a superconducting interposer, a second SMCM and a superconducting semiconductor structure. The interposer is disposed over and coupled to the first SMCM, the second SMCM is disposed over and coupled to the interposer, and the superconducting semiconductor structure is disposed over and coupled to the second SMCM. The second SMCM and the superconducting semiconductor structure are electrically coupled to the first SMCM through the interposer. A method of fabricating a cryogenic electronic package is also provided.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: August 13, 2019
    Assignee: Massachusetts Institute of Technology
    Inventors: Rabindra N. Das, Eric A. Dauler
  • Patent number: 10383231
    Abstract: Provided is a component-embedded board which includes: a first board including a first insulation layer, a first conductive layer formed on a second face of the first insulation layer, and an interlayer conductive portion penetrating the first insulation layer to be connected to the first conductive layer and protruding from a first face of the first insulation layer; an electric component connected to the interlayer conductive portion; and a second board including a second insulation layer having an opening portion incorporating the electric component, and a second conductive layer formed on at least either one of a first face and a second face of the second insulation layer. The second conductive layer includes a frame portion. The opening portion is formed so as to penetrate the second insulation layer in a thickness direction thereof over the entirety of the inner region of the frame portion.
    Type: Grant
    Filed: February 8, 2013
    Date of Patent: August 13, 2019
    Assignee: FUJIKURA LTD.
    Inventors: Yoshinori Sano, Masahiro Okamoto
  • Patent number: 10366925
    Abstract: A method of processing a wafer includes a laser beam applying step of applying a laser beam to the wafer to form modified layers in the inside of the wafer along division lines and to extend device layer splitting cracks from the modified layers to the front surface of the wafer. After the laser beam applying step is performed, a cutting step of cutting the wafer is performed by a cutting blade from the back surface side to form cut grooves and to remove the modified layers. Therefore, the modified layers are not left on chips, and the die strength of the chips is enhanced.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: July 30, 2019
    Assignee: Disco Corporation
    Inventor: Tetsukazu Sugiya
  • Patent number: 10359892
    Abstract: A flexible touch sensing unit includes a substrate including a plane region and a bending region, a plurality of sensing electrodes disposed on the substrate, a plurality of sensing lines surrounding the plurality of sensing electrodes and electrically connected to the plurality of sensing electrodes, and a damage prevention layer disposed in the bending region. Cracks on the sensing electrodes and the sensing lines which are disposed in the bending region may be prevented by the damage prevention layer in the bending region. A resulting flexible display device using the flexible touch sensing unit may be thinner by omission of a flexibility enhancing layer.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: July 23, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Kang-Won Lee, Young-Sik Kim, Hee-Woong Park, Young-Seok Yoo, Jeong-Heon Lee, Sung-Hwan Kim, Hyung-Chul Kim, Choon-Hyop Lee, Hyun-Jae Lee
  • Patent number: 10340259
    Abstract: A method for fabricating a semiconductor package is provided. Semiconductor dice are disposed on a top surface of a carrier. Each of the semiconductor dice has an active surface and a bottom surface that is opposite to the active surface. Input/output (I/O) pads are distributed on the active surface. Interconnect features are printed on the carrier and on the active surface of each of the semiconductor dice. The top surface of the carrier, the semiconductor dice and the interconnect features is encapsulated with an encapsulant. The carrier is then removed.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: July 2, 2019
    Assignee: MediaTek Inc.
    Inventor: Shiann-Tsong Tsai