Abstract: Methods of manufacturing a semiconductor chip are provided. The methods may include providing a semiconductor substrate including integrated circuit regions and a cut region. The cut region may be between the integrated circuit regions. The methods may also include forming a modified layer by emitting a laser beam into the semiconductor substrate along the cut region, polishing an inactive surface of the semiconductor substrate to propagate a crack from the modified layer, and separating the integrated circuit regions along the crack. The cut region may include a plurality of multilayer metal patterns on an active surface of the semiconductor substrate, which is opposite to the inactive surface of the semiconductor substrate. The plurality of multilayer metal patterns may form a pyramid structure when viewed in cross section.

Abstract: A semiconductor package that includes a support wiring structure. A semiconductor chip is on the support wiring structure. A cover wiring structure is on the semiconductor chip. A plurality of connection structures penetrates a filling member and electrically connects the support wiring structure to the cover wiring structure. The filling member fills a space between the support wiring structure and the cover wiring structure. The filling member surrounds the plurality of connection structures and the semiconductor chip and includes a plurality of fillers. A partial portion of the plurality of fillers includes cutting fillers having a flat surface that extends along a vertical level that is a reference level.

Abstract: A semiconductor package comprising a package substrate that extends in a first direction and a second direction perpendicular to the first direction, a plurality of logic dies and a memory stack structure on the package substrate, and an interposer substrate mounted in the package substrate. The memory stack structure vertically overlaps the interposer substrate. Each of the logic dies includes a first part that is horizontally offset from the interposer substrate and a second part that vertically overlaps the interposer substrate. The interposer substrate includes an interlayer dielectric layer and a plurality of wiring lines in the interlayer dielectric layer. The memory stack structure is electrically connected to at least one of the logic dies through the wiring lines of the interposer substrate.

Abstract: An additively manufactured component and a method for manufacturing the same are provided. The additively manufactured component includes a cross sectional layer having a surface surrounding the cross sectional layer. The cross sectional layer is formed by moving a focal point of an energy source over a bed of additive material. A surface irregularity is formed on the surface by manipulating the energy level of the energy source. The surface may include a datum feature positioned at a predetermined location relative to the surface irregularity and the surface irregularity may be greater than a surface roughness of the surface but less than one millimeter.

Abstract: A chip package structure includes at least one semiconductor die attached to a redistribution structure, a first underfill material portion located between the redistribution structure and the at least one semiconductor die and laterally surrounding the solder material portions, a molding compound laterally surrounding at least one semiconductor die, and a second underfill material portion contacting sidewalls of the redistribution structure and sidewalls of the molding compound and including at least one cut region. The second underfill material portion includes a vertically-extending portion having a uniform lateral width and a horizontally-extending portion having a uniform vertical thickness and adjoined to a bottom end of the vertically-extending portion within each of the at least one cut region.

Abstract: Embodiments of the disclosure include a receiver of an optical sensing system. The receiver may include a Hadamard mask configured to resonate during a scanning procedure performed by the optical sensing system. The Hadamard mask may include a frame beginning pattern corresponding to a start of a frame captured during the scanning procedure. The Hadamard mask may also include a coded pattern configured to provide sub-pixelization of the frame. The receiver may also include a photodetector array positioned on a first side of the Hadamard mask. The photodetector array may be configured to detect light that passes through the Hadamard mask during the scanning procedure to generate the frame.

Abstract: A semiconductor device and a method of manufacturing a semiconductor device. For example, various aspects of this disclosure provide a semiconductor device having an ultra-thin substrate, and a method of manufacturing a semiconductor device having an ultra-thin substrate. As a non-limiting example, a substrate structure comprising a carrier, an adhesive layer formed on the carrier, and an ultra-thin substrate formed on the adhesive layer may be received and/or formed, components may then be mounted to the ultra-thin substrate and encapsulated, and the carrier and adhesive layer may then be removed.

Abstract: A semiconductor package includes: a redistribution substrate; a frame including first and second vertical connection conductors, and having a through-hole; first and second semiconductor chips; an encapsulant; a second redistribution structure disposed on the encapsulant, a conductive wire electrically connecting the second semiconductor chip and the second vertical connection conductor; and a vertical connection via penetrating a portion of the encapsulant, and electrically connecting the second redistribution structure and the first vertical connection conductor. The first semiconductor chip is connected to the second vertical connection conductor by the first redistribution structure.

Abstract: A packaging method and a packaging structure of a film bulk acoustic resonator are provided. The packaging method includes: providing a resonant cavity main structure including a first substrate and a film bulk acoustic resonant structure having a first cavity formed therebetween; forming a resonator cover by providing a second substrate and forming an elastic bonding material layer containing a second cavity; bonding the resonant cavity main structure and the resonator cover together through the elastic bonding material layer and removing elasticity of the elastic bonding material layer, where the second cavity is at least partially aligned with the first cavity; forming a through-hole penetrating through the resonator cover and exposing a corresponding electrical connection part of the film bulk acoustic resonant structure; and forming a conductive interconnection layer on a sidewall of the through-hole and on a portion of a surface of the resonator cover.

Abstract: A system for calibrating an equipment, the system including a beam splitter; a first reticle configured to be removably attached to the equipment; and an image capture device including an image plane, wherein an image of the first reticle is configured to be received by way of the beam splitter at the image plane along an optical axis of the beam splitter, wherein the orientation as indicated by the first reticle is compared to an orientation of the image plane and if the orientation as indicated by the first reticle differs from the orientation of the image plane, the equipment is rotated about the optical axis of the beam splitter such that the orientation as indicated by the first reticle matches the orientation of the image plane.

Abstract: Discussed is an apparatus for self-assembling semiconductor light-emitting devices, the apparatus including a fluid chamber to accommodate the semiconductor light-emitting devices, each semiconductor light-emitting device having a magnetic body; a magnet to apply a magnetic force to the semiconductor light-emitting devices while an assembly substrate is disposed at an assembly position of the self-assembly apparatus; a power supply to induce formation of an electric field on the assembly substrate to allow the semiconductor light-emitting devices to be seated at a preset positions on the assembly substrate in a process of moving the semiconductor light-emitting devices due to a change in a position of the magnet; and a fluid injector to shoot a fluid to some of the semiconductor light-emitting devices to allow the some of the semiconductor light-emitting devices seated on the assembly substrate to be separated from the assembly substrate.

Abstract: A thin film transistor substrate includes: a substrate, a first electrode disposed on the substrate, a bank disposed on the substrate and having an inclined surface inclined at an angle with respect to the substrate, a second electrode disposed on the bank, an active pattern electrically connected to the first electrode and the second electrode, disposed on the inclined surface, and including a first conductive region and a second conductive region in which impurities are doped, and a channel region between the first conductive region and the second conductive region, and a gate electrode overlapping at least a portion of the channel region of the active pattern. The inclined surface extends in a first direction in a plan view. The first conductive region, the channel region, and the second conductive region are sequentially disposed on the inclined surface along a second direction that crosses the first direction.

Abstract: A package substrate includes a substrate, an insulating protective layer and an interposer. The substrate has a first surface and a second surface opposing to the first surface. The substrate includes a plurality of first conductive pads embedded in the first surface. The insulating protective layer is disposed on the first surface of the substrate. The insulating protective layer has an opening for exposing the first conductive pads embedded in the first surface of the substrate. The interposer has a top surface and a bottom surface opposing to the top surface. The interposer includes a plurality of conductive vias and a plurality of second conductive pads located on the bottom surface. The interposer is located in a recess defined by the opening of the insulating protective layer and the first surface of the substrate. Each of the second conductive pads is electrically connected to corresponding first conductive pad.

Abstract: In certain embodiments, a system includes: an inspection station configured to receive a die vessel, wherein the inspection station is configured to inspect the die vessel for defects; a desiccant station configured to receive the die vessel from the inspection station, wherein the desiccant station is configured to add a desiccant to the die vessel; a bundle station configured to receive the die vessel from the desiccant station, wherein the bundle station is configured to combine the die vessel with another die vessel as a die bundle; and a bagging station configured to receive the die bundle from the bundle station, wherein the bagging station is configured to dispose the die bundle in a die bag and to heat seal the die bag with the die bundle inside.

Abstract: A micro-transfer structure comprises a stamp comprising a rigid support, only a single contiguous bulk layer disposed on the rigid support, and posts disposed on the bulk layer. Components are adhered to (e.g., disposed in contact with) some but not all of the posts. The posts can be substantially identical and disposed in a regular array on the bulk layer. Each component is adhered to (e.g., in contact with) two or more posts. Components can be disposed on a source wafer entirely over sacrificial portions of a sacrificial layer on or in the source wafer and attached to anchors disposed between sacrificial portions with a tether.

Abstract: A semiconductor device including a semiconductor chip having a first conduction element; a substrate having second and third conduction elements; and external connection elements configured to form an electrical path between the second and third conduction elements via the first conduction element.

Abstract: A surface acoustic wave (SAW) device including a substrate is provided. Multiple surface acoustic wave elements are disposed on the substrate. A conductive surrounding structure includes: a wall part, disposed on the substrate and surrounding the surface acoustic wave elements; and a lateral layer part, disposed on the wall part. The lateral layer part has an opening above the surface acoustic wave elements. A cap layer covers the lateral layer part and closes the opening.

Abstract: The invention relates to a geometric design and corresponding methods for components 22, which are produced on a carrier substrate 10 and prepared by detachment in an etching process 30 for a subsequent absorption and a transfer with a stamp for application to a further substrate. The components 22 are designed in such a way that additional active surfaces are provided for the etching process 30 for undercut the components, so that a faster, more reliable and more homogeneous etching profile is achieved.

Abstract: Semiconductor devices and methods of manufacture are provided, in which an adhesive is removed from a semiconductor die embedded within an encapsulant, and an interface material is utilized to remove heat from the semiconductor device. The removal of the adhesive leaves behind a recess adjacent to a sidewall of the semiconductor, and the recess is filled.

Abstract: An apparatus includes a substrate, a frame, and a socket. The frame defines a slot. The frame is coupled to the substrate such that the slot is aligned with an attachment location on the substrate. The socket receives a first device. The socket aligns with the attachment location on the substrate when the socket is inserted in the slot.

Abstract: A package device and a manufacturing method thereof are provided. The package device includes a redistribution layer. The redistribution layer includes a first dielectric layer, a conductive layer, and a second dielectric layer, and the conductive layer is disposed between the first dielectric layer and the second dielectric layer, wherein the redistribution layer has a test mark, the test mark includes a conductive pattern formed of the conductive layer, the conductive pattern includes a center portion and a plurality of extension portions, and the plurality of extension portions are respectively connected to the center portion.

Abstract: A semiconductor device package includes an embedded plurality of solder balls within an integrated circuit die (ICD) substrate In one embodiment, the integrated circuit die (ICD) substrate has a top surface and a bottom surface, and a plurality of solder balls at least partially embedded in the ICD substrate, where each of the plurality of solder balls comprises an exposed surface that is substantially flat and parallel planar to the bottom surface, and where the exposed surface of each of the plurality of solder balls is disposed in the bottom surface. In certain examples, the apparatuses also include a plurality of integrated circuit dies stacked on the top surface of the ICD substrate.

Abstract: A method for forming a gate structure of a 3D memory device is provided. The method comprises: forming a plurality of hybrid shallow trench isolation structures in a substrate, each hybrid shallow trench isolation structure comprising a dielectric sublayer and a conductive sublayer, both of which are embedded in the substrate; forming an alternating dielectric stack on the substrate; forming a slit penetrating vertically through the alternating dielectric stack and extending in a horizontal direction to expose a row of hybrid shallow trench isolation structures; forming a plurality of array common source contacts in the slit, each array common source contact being in electric contact with a corresponding hybrid shallow trench isolation structure.

Abstract: An encapsulant compound apparatus, includes a mechanical operator, and an insert disposed on a surface of the mechanical operator. The insert operates to capture foreign material in the encapsulant compound.

Abstract: Methods, systems, and apparatus for using antennas for millimeter wave contactless communication. One of the apparatuses is a communication device that includes a transducer configured to convert electrical signals into extremely high frequency (EHF) electromagnetic signals, the EHF electromagnetic signals substantially emitted from a first surface of the communication device, wherein the transducer is positioned on a substrate of the communication device, and an integrated circuit coupled to the substrate, wherein the transducer includes multiple parallel resonant antenna elements in an array.

Abstract: A method of repairing a light emitting device, comprises: providing a light emitting device comprising a carrier board and a first light emitting unit; destroying the first light emitting unit and forming a removal surface on the light emitting device; planarizing the removal surface; providing a bonding structure on the removal surface; and fixing a second light emitting unit on the planarized removal surface through the bonding material.

Abstract: A manufacturing method of a semiconductor package is provided. The manufacturing method includes the following. A plurality of semiconductor components are provided. Each semiconductor component has at least one conductive bump. A substrate is provided. The substrate has a plurality of conductive pads. A transfer device is provided. The transfer device transfers the semiconductor components onto the substrate. A heating device is provided. The heating device heats or pressurizes at least two semiconductor components. During transferring of the semiconductor components to the substrate, the at least one conductive bump of each semiconductor component is docked to a corresponding one of the conductive pads.

Abstract: A processing apparatus includes a wafer conveying-out mechanism; a wafer table; a frame conveying-out mechanism; a frame table; a tape attaching mechanism that attaches a tape to a frame; a tape-attached frame conveying mechanism that conveys the tape-attached frame; a tape pressure bonding mechanism that pressure bonds the tape of the tape-attached frame to a back surface of a wafer; a frame unit conveying-out mechanism that conveys out a frame unit in which the tape of the tape-attached frame and the back surface of the wafer are pressure bonded; a reinforcement section removing mechanism that cuts and removes a ring-shaped reinforcement section from the wafer; a ringless unit conveying-out mechanism that conveys out a ringless unit from which the reinforcement section has been removed; and a frame cassette table on which a frame cassette accommodating the ringless unit is to be placed.

Abstract: Embodiments of 3D memory devices and the fabrication methods to form the 3D memory devices are provided. A 3D memory device includes a substrate, a memory deck, and a memory string. The memory deck includes a plurality of interleaved conductor layers and dielectric layers on the substrate. The memory string extends vertically through the memory deck. A bottom conductor layer of the plurality of interleaved conductor layers and dielectric layers can intersect with and contact the memory string.

Abstract: A method for manufacturing electronic apparatus includes: a step (A) of preparing a structure provided with an adhesive film and one or two or more electronic components affixed to an adhesive surface of the adhesive film; a step (B) of disposing the structure in the electronic component testing apparatus such that the electronic component is positioned over an electronic component installation region of a sample stand of the electronic component testing apparatus in a defined manner; a step (C) of evaluating the properties of the electronic component in a state of being affixed to the adhesive film with the probe terminal being in contact with a terminal of the electronic component; and a step (D) of picking up the electronic component from the adhesive film after the step (C). A defined sample stand is also provided.

Abstract: An IC package includes a heat-generating device and an electrical device on a surface of a substrate, a mold compound disposed on the electrical device, and a thermal structure disposed on the heat-generating device, without the mold compound, to improve heat dissipation. In an example, the thermal structure includes a thermal interface material (TIM) layer and a heat sink. In the example, the TIM layer extends from the heat-generating device to a height equal to or less than the mold compound and the heat sink includes a planar exterior surface above the heat-generating device and the electrical device. In an example, a first heat sink portion of the heat sink on the heat-generating device may be a different thickness than a second heat sink portion of the heat sink on the electrical device. The thermal structure reduces a thermal resistance between the heat-generating device and the heat sink.

Abstract: A method for forming a semiconductor device package is provided. The method includes bonding a semiconductor device to a package substrate; placing a metal lid over the semiconductor device and the package substrate with a metal thermal interface material (TIM) provided between the metal lid and the semiconductor device; heating the metal TIM to melt the metal TIM; pressing the metal lid downward so that the molten metal TIM flows toward the boundary of the semiconductor device, and the outermost point of the lateral sidewall of the molten metal TIM extends beyond the boundary of the semiconductor device; lifting the metal lid upward so that the molten metal TIM flows back, and the outermost point of the lateral sidewall is within the boundary of the semiconductor device; and bonding the metal lid to the semiconductor device through the metal TIM by curing the molten metal TIM.

Abstract: A semiconductor device has a substrate including a terminal and an insulating layer formed over the terminal. An electrical component is disposed over the substrate. An encapsulant is deposited over the electrical component and substrate. A portion of the insulating layer over the terminal is exposed from the encapsulant. A shielding layer is formed over the encapsulant and terminal. A portion of the shielding layer is removed to expose the portion of the insulating layer. The portion of the insulating layer is removed to expose the terminal. The portion of the shielding layer and the portion of the insulating layer can be removed by laser ablation.

Abstract: Microelectronic assemblies, related devices, and methods are disclosed herein. In some embodiments, a microelectronic assembly may include a die having a first surface and an opposing second surface; a capacitor having a surface, wherein the surface of the capacitor is coupled to the first surface of the die; and a conductive pillar coupled to the first surface of the die. In some embodiments, a microelectronic assembly may include a capacitor in a first dielectric layer; a conductive pillar in the first dielectric layer; a first die having a surface in the first dielectric layer; and a second die having a surface in a second dielectric layer, wherein the second dielectric layer is on the first dielectric layer, and wherein the surface of the second die is coupled to the capacitor, to the surface of the first die, and to the conductive pillar.

Abstract: A communication control circuit for a power supply chip, can include: a main control die having a main control circuit; a plurality of sub-control dice configured to respectively receive a control signal sent by the main control die, where each sub-control die comprises a sub-control circuit; and where a reference ground of each sub-control die is different from a reference ground of the main control die, the reference grounds of the plurality of sub-control dice are different with each other, and communication between the main control die and each sub-control die is achieved by a corresponding level conversion circuit.

Abstract: Described herein is a die-to-wafer bonding process that utilizes micro-transfer printing to transfer die from a source wafer onto an intermediate handle wafer. The resulting intermediate handle wafer structure can then be bonded die-down onto the target wafer, followed by removal of only the intermediate handle wafer, leaving the die in place bonded to the target wafer.

Abstract: Structures and formation methods of a chip package structure are provided. The chip package structure includes a semiconductor die bonded over an interposer substrate. The chip package structure also includes a warpage release layer structure. The warpage release layer structure includes an organic material layer and an overlying high coefficient of thermal expansion (CTE) material layer with a CTE that is substantially equal to or greater than 9 ppm/° C. The organic material layer is in direct contact with the upper surface of the semiconductor die, and the overlying high CTE material layer covers the upper surface of the semiconductor die.

Abstract: A method for transferring at least one chip, from a first support to a second support, includes forming, while the chip is assembled to the first support, an interlayer in the liquid state between, and in contact with, a front face of the chip and an assembly surface of a face of the second support and a solidification of the interlayer. Then, the chip is detached from the first support while maintaining the interlayer in the solid state.

Abstract: According to one aspect, a visualization device may include an image sensor, a lens for focusing light onto the image sensor, a first end, a second end opposite the first end, a lateral wall surface extending between the first end and the second end, and a coating on the lateral wall surface. The coating may include at least one of an electrically-insulating layer and a light-blocking layer, and may be deposited on the lateral wall surface using, for example, physical vapor deposition (PVD).

Abstract: In a described example, an apparatus includes: a process chamber configured for a pressure greater than one atmosphere, having a device chuck configured to support electronic devices that are mounted on package substrates and partially covered in mold compound, the electronic devices spaced from one another by saw streets; and a saw in the process chamber configured to cut through the mold compound and package substrates in the saw streets to separate the molded electronic devices one from another.

Abstract: A circuit board includes a substrate, a plurality of contacts disposed on a surface of the substrate, and a solder mask. The contacts have a plurality of plating regions and a metal layer on the plating regions, and the plating regions have at least two different sizes. The solder mask covers the surface of the substrate and covers edges of the plating regions, in which topmost surfaces of the contacts are below a top surface of the solder mask, and a gap between the topmost surfaces of the contacts and the top surface of the solder mask is larger than 0 ?m and is smaller than 5 ?m.

Abstract: A semiconductor package includes: a connection structure having first and second surface opposing each other and including a plurality of insulating layers, a plurality of redistribution layers, and a plurality of connection vias; at least one semiconductor chip on the first surface having connection pads electrically connected to the plurality of redistribution layers; an encapsulant on the first surface encapsulating the at least one semiconductor chip; and UBM layers including UBM pads on the second surface and UBM vias connecting a redistribution layer. At least one connection via adjacent to the first surface has a tapered structure narrowed toward the second surface, and the other connection vias and the UBM vias have a tapered structure narrowed toward the first surface.

Abstract: A sheet holding unit of a resin sheet fixing apparatus includes: a Peltier element that has an upper surface parallel to a sheet holding surface of a sheet holding table and near the sheet holding surface and a lower surface far from the sheet holding surface; a direct current (DC) power source that supplies the Peltier element with a DC; and a switch that switches a direction of the DC supplied to the Peltier element. By causing a current to flow in the Peltier element in a first direction, a resin sheet is softened and welded to a wafer, and by switching the switch to cause a current to flow in the Peltier element in a second direction, the resin sheet held on the sheet holding surface is cured and fixed to a surface on one side of the wafer.

Abstract: A method for manufacturing semiconductor modules for image-sensing devices is disclosed. The method may comprise applying a removable layer on a first surface of a printed circuit board (PCB) which comprises a plurality of PCB units; mounting a photosensitive member to a second surface of each of the PCB units; and encapsulating the photosensitive member with an encapsulation layer on each PCB unit. Each PCB unit may comprise at least a semiconductor component on a second surface of the PCB and one or more opening across the first surface and the second surface. The photosensitive member and the removable layer separate the one or more opening from outside, and the photosensitive member is positioned to receive light through the opening. At least one semiconductor component is also encapsulated by the encapsulation layer on each PCB unit.

Abstract: Multiple chip module (MCM) structures are described. In an embodiment, a module includes a first and second components on the top side of a module substrate, a stiffener structure mounted on the top side of the module substrate, and a lid mounted on the stiffener structure and covering the first component and the second component. The stiffener is joined to the lid within a trench formed in a roof of the lid.

Abstract: An apparatus comprising first and second interconnections spaced apart from one another, an interlayer insulating material over the first and second interconnections, first and second contacts in the interlayer insulating material and spaced apart from one another, third and fourth interconnections over the interlayer insulating material and spaced apart from one another, and compensation capacitors in a capacitor region. The third interconnections are coupled with the first interconnections through the first contacts and the fourth interconnections are coupled with the second interconnections through the second contacts. The compensation capacitors comprise lower electrodes over the interlayer insulating material, dielectric materials over the lower electrodes, and upper electrodes over the dielectric materials. The lower electrodes comprise edge portions in contact with the second contacts.

Abstract: Methods and systems for a thin bonded interposer package are disclosed and may, for example, include bonding a semiconductor die to a first surface of a substrate, forming contacts on the first surface of the substrate, encapsulating the semiconductor die, formed contacts, and first surface of the substrate using a mold material while leaving a top surface of the semiconductor die not encapsulated by mold material, forming vias through the mold material to expose the formed contacts. A bond line may be dispensed on the mold material and the semiconductor die for bonding the substrate to an interposer. A thickness of the bond line may be defined by standoffs formed on the top surface of the semiconductor die.

Abstract: MEMS-based sensors can experience undesirable signal frequencies caused by vibrations, shocks, and accelerations, among other phenomena. A microisolation system can isolate individual MEMS-based sensors from undesirable signal frequencies and shocks. An embodiment of a system for microisolation of a MEMS-based sensor can include an isolation platform connected to one or more folded springs. Another embodiment of a system for microisolation can include an isolation platform and/or a frame connected to a mesh damping mechanism. In at least one embodiment, a mesh damping mechanism can be a microfibrous metal mesh damper. In one or more embodiments, a system for microisolation can include an isolation platform connected to one or more L-shaped springs, and a thickness of the one or more L-shaped springs can be less than a thickness of the isolation platform.

Abstract: A semiconductor device includes a semiconductor die having a front side surface, a backside surface opposite the front side surface and side faces. A backside metallization layer is deposited over the backside surface and projects laterally outwards beyond the side faces. A side face protection layer covers the side faces.

Abstract: Embodiments disclosed herein include an electronics package comprising stacked dies. In an embodiment, the electronics package comprises a first die that includes a plurality of first conductive interconnects extending out from a first surface of the first die. In an embodiment, the first die further comprises a keep out zone. In an embodiment, the electronic package may also comprise a second die. In an embodiment, the second die is positioned entirely within a perimeter of the keep out zone of the first die. In an embodiment, a first surface of the second die faces the first surface of the first die.