Packaging (e.g., With Mounting, Encapsulating, Etc.) Or Treatment Of Packaged Semiconductor Patents (Class 438/106)
  • Patent number: 11133289
    Abstract: A semiconductor package includes a first integrated circuit structure, a second integrated circuit structure, a plurality of conductive bumps, an encapsulating material, and a redistribution structure. The first integrated circuit structure includes an active surface having a plurality of contact pads, a back surface opposite to the active surface, and a plurality of through vias extending through the first integrated circuit structure and connecting the active surface and the back surface. The second integrated circuit structure is disposed on the back surface of the first integrated circuit structure. The conductive bumps are disposed between the first integrated circuit structure and the second integrated circuit structure, and electrically connecting the plurality of through vias and the second integrated circuit structure. The encapsulating material at least encapsulates the second integrated circuit structure.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: September 28, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Fu Tsai, Shih-Ting Lin, Szu-Wei Lu, Ying-Ching Shih
  • Patent number: 11117796
    Abstract: An embodiment is a MEMS device including a first MEMS die having a first cavity at a first pressure, a second MEMS die having a second cavity at a second pressure, the second pressure being different from the first pressure, and a molding material surrounding the first MEMS die and the second MEMS die, the molding material having a first surface over the first and the second MEMS dies. The device further includes a first set of electrical connectors in the molding material, each of the first set of electrical connectors coupling at least one of the first and the second MEMS dies to the first surface of the molding material, and a second set of electrical connectors over the first surface of the molding material, each of the second set of electrical connectors being coupled to at least one of the first set of electrical connectors.
    Type: Grant
    Filed: July 8, 2020
    Date of Patent: September 14, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Wen Cheng, Jung-Huei Peng, Shang-Ying Tsai, Hung-Chia Tsai, Yi-Chuan Teng
  • Patent number: 11121077
    Abstract: In one example, a semiconductor device comprises a substrate comprising a dielectric, a first conductor on a top side of the dielectric, and a second conductor on a bottom side of the dielectric, wherein the dielectric has an aperture, and the first conductor comprises a partial via contacting a pad of the second conductor through the aperture, an electronic device having an interconnect electrically coupled to the first conductor, and an encapsulant on a top side of the substrate contacting a side of the electronic device. Other examples and related methods are also disclosed herein.
    Type: Grant
    Filed: July 10, 2019
    Date of Patent: September 14, 2021
    Assignee: Amkor Technology Singapore Holding PTE. LTD.
    Inventors: Ji Yeon Ryu, Jae Beom Shim
  • Patent number: 11121011
    Abstract: A process system includes a substrate, first wafers, second wafers, and a roller. The first wafers are arranged at predetermined intervals along a first column which is parallel to an edge of the substrate, wherein each of the first wafers includes first chips. The second wafers are arranged at the predetermined intervals and at an offset from the first wafers, along a second column which is parallel to the first column, wherein each of the second wafers includes second chips. The roller is configured to roll in a first direction to pick up the plurality of first chips, roll in a second direction opposite to the first direction while suspended from the first wafers, pick up the second chips included in the wafers by rolling in the first direction, and transport the first chips and the second chips to the substrate.
    Type: Grant
    Filed: May 2, 2019
    Date of Patent: September 14, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Sang-moo Park
  • Patent number: 11094645
    Abstract: An exemplary semiconductor device can comprise a die, a redistribution structure (RDS), an interconnect, a conductive strap, an encapsulant, and an EMI shield. The redistribution structure can comprise an RDS top surface coupled to the die bottom side. The interconnect can be coupled to the RDS bottom surface. The conductive strap can be coupled to the RDS, and can comprise a strap inner end coupled to the RDS bottom surface, and a strap outer end located lower than the RDS bottom surface. The encapsulant can encapsulate the conductive strap and the RDS bottom surface. The EMI shield can cover and contact the encapsulant sidewall and the strap outer end. Other examples and related methods are also disclosed herein.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: August 17, 2021
    Assignee: Amkor Technology Singapore Holding Pte. Ltd.
    Inventors: Hee Sung Kim, Yeong Beom Ko, Joon Dong Kim, Dong Jean Kim, Sang Seon Oh
  • Patent number: 11088054
    Abstract: A lead frame includes a die pad having a pad top surface and a pad bottom surface opposite to the top pad surface, a plurality of leads, each having a top lead surface and a bottom lead surface opposite to the top lead surface and disposed around the die pad, and a first molding compound disposed between the die pad and each of the leads. The first molding compound exposes the top pad surface of the die pad by covering a portion of the periphery of the top pad surface of the die pad. A method for manufacturing the lead frame is also disclosed.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: August 10, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chi Sheng Tseng, Lu-Ming Lai, Ying-Chung Chen, Hui-Chung Liu
  • Patent number: 11081455
    Abstract: A semiconductor device includes a semiconductor die having a main surface, a rear surface, outer edge sides extending between the main and rear surfaces, and a first conductive bond pad disposed on the main surface, an electrically insulating mold compound body formed around the outer edge sides of the semiconductor die with the main surface of the semiconductor die exposed from an upper surface of the mold compound body, a first metallization layer formed on the upper surface of the mold compound body and on the main surface of the semiconductor die, and a first bond pad extension formed in the first metallization layer. The first bond pad extension overlaps with the upper surface of the mold compound body. The first bond pad extension is conductively connected with the first conductive bond pad. The first bond pad extension is an externally accessible point of electrical contact of the device.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: August 3, 2021
    Assignee: Infineon Technologies Austria AG
    Inventors: Chan Lam Cha, Wei Han Koo, Thorsten Meyer, Klaus Schiess, Guan Choon Matthew Nelson Tee
  • Patent number: 11075235
    Abstract: An image sensor mounting base includes a substrate, and a first, a second, a third and a fourth electrode pad. The substrate has an upper surface including a first mount area where a first image sensor is mountable, and a second mount area where a second image sensor is mountable. The second mount area is spaced from the first mount area. The first and second electrode pads are located on the upper surface of the substrate and across the first mount area each other. The third and fourth electrode pads on the upper surface of the substrate are spaced from the first electrode pad and the second electrode pad and face each other across the second mount area. The substrate has, on the upper surface, a recess between the third electrode pad and the fourth electrode pad. The second mount area is located on a bottom of the recess.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: July 27, 2021
    Assignee: KYOCERA CORPORATION
    Inventors: Kenichi Kohama, Fumiaki Takeshita
  • Patent number: 11069646
    Abstract: The disclosure provides a printed circuit board structure. The printed circuit board structure includes a printed circuit board, a semiconductor chip, a first pad, a second pad, a conductive wire, and a third pad. The semiconductor chip is disposed on the printed circuit board. The first pad is disposed on the semiconductor chip. The second pad is disposed on the printed circuit board. The conductive wire electrically connects the first pad and the second pad. The third pad is disposed between the first pad and the second pad. The conductive wire has a portion located on the third pad.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: July 20, 2021
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Wu-Der Yang
  • Patent number: 11069589
    Abstract: Provided is a circuit board including: a metal core layer having a first main surface capable of supporting a mounting component and a second main surface which is opposite to the first main surface; a first exterior coating base material which is arranged facing the first main surface; and a second exterior coating base material which is arranged facing the second main surface and includes a heat dissipation layer having a via which is connected to the second main surface.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: July 20, 2021
    Assignee: TAIYO YUDEN CO., LTD.
    Inventors: Yutaka Hata, Masashi Miyazaki, Yuichi Sugiyama
  • Patent number: 11062994
    Abstract: A semiconductor device package includes a substrate and an electronic component disposed on the substrate. The electronic component has an active surface facing away from the substrate. The substrate has a first conductive pad and a second conductive pad disposed thereon. The electronic component has a first electrical contact and a second electrical contact disposed on the active surface. The semiconductor device package further includes a first metal layer connecting the first electrical contact with the first conductive pad, a second metal layer connecting the second electrical contact with the second conductive pad, a first seed layer disposed below the first metal layer; and a first isolation layer disposed between the first metal layer and the second metal layer. A method of manufacturing a semiconductor device package is also disclosed.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: July 13, 2021
    Assignee: ADVANCED SEMICONDUCOR ENGINEERING, INC.
    Inventor: Wen-Long Lu
  • Patent number: 11063001
    Abstract: A semiconductor device and a method of manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a semiconductor device comprising one or more conductive shielding members and an EMI shielding layer, and a method of manufacturing thereof.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: July 13, 2021
    Assignee: Amkor Technology Singapore Holding Pte. Ltd.
    Inventors: Yi Seul Han, Tae Yong Lee, Ji Yeon Ryu
  • Patent number: 11056525
    Abstract: The present disclosure relates to a semiconductor photomultiplier comprising a a substrate; an array of photosensitive elements formed on a first major surface of the substrate; a plurality of primary bus lines interconnecting the photosensitive elements; at least one segmented secondary bus line provided on a second major surface of the substrate which is operably coupled to one or more terminals; and multiple vertical interconnect access (via) extending through the substrate operably coupling the primary bus lines to the at least one segmented secondary bus line.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: July 6, 2021
    Assignee: SensL Technologies LTD
    Inventors: Brian McGarvey, Stephen John Bellis, John Carlton Jackson
  • Patent number: 11056410
    Abstract: A method of manufacturing a semiconductor package and a semiconductor package in which positional alignment between a wafer and a substrate until the wafer is mounted and packaged on the substrate is achieved accurately. A wafer is mounted on a package substrate by using first alignment marks and D-cuts as benchmarks, and then a mold resin layer is formed on the wafer in a state in which the first alignment mark is exposed. A part of the mold resin layer is removed by using the D-cuts exposed from the mold resin layer as benchmarks, so that the first alignment marks can be visually recognized. A second alignment marks are formed on the mold resin layer by using the first alignment marks as benchmarks. A Cu redistribution layer to be conducted to a pad portion is formed on a mold resin layer by using the second alignment marks as benchmarks.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: July 6, 2021
    Assignee: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
    Inventors: Shiro Hara, Sommawan Khumpuang, Fumito Imura
  • Patent number: 11049898
    Abstract: A method for manufacturing semiconductor modules for image-sensing devices is disclosed. The method may comprise applying a removable layer on a first surface of a printed circuit board (PCB) which comprises a plurality of PCB units; mounting a photosensitive member to a second surface of each of the PCB units; and encapsulating the photosensitive member with an encapsulation layer on each PCB unit. Each PCB unit may comprise at least a semiconductor component on a second surface of the PCB and one or more opening across the first surface and the second surface. The photosensitive member and the removable layer separate the one or more opening from outside, and the photosensitive member is positioned to receive light through the opening. At least one semiconductor component is also encapsulated by the encapsulation layer on each PCB unit.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: June 29, 2021
    Assignee: Ningbo Sunny Opotech Co., Ltd.
    Inventors: Mingzhu Wang, Nan Guo, Jingfei He, Zhenyu Chen, Bojie Zhao, Takehiko Tanaka, Feifan Chen, Ye Wu, Zhen Huang, Zhongyu Luan
  • Patent number: 11037856
    Abstract: A semiconductor chip package may comprise a semiconductor chip disposed on a substrate. The semiconductor chip may have a first surface and a second surface. The first surface of the semiconductor chip may be connected to the substrate. The semiconductor chip package may comprise a leadframe that includes a first lead and a second lead. The first lead of the leadframe may be directly attached to the second surface of the semiconductor chip. The second lead of the leadframe may be directly attached to the substrate. An important aspect in development of the semiconductor chip package is improvement of connections between different components within the package.
    Type: Grant
    Filed: April 23, 2020
    Date of Patent: June 15, 2021
    Assignee: Infineon Technologies AG
    Inventors: Christian Neugirg, Peter Scherl
  • Patent number: 11037865
    Abstract: An aspect of the present disclosure provides a method of manufacturing a semiconductor device. The method includes preparing a lead frame. The lead frame includes a first lead including a pad and a first terminal. The pad includes a pad main surface and a pad back surface that face opposite sides to each other in a first direction. The first terminal extends from the pad along a second direction that is perpendicular to the first direction.
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: June 15, 2021
    Assignee: ROHM CO., LTD.
    Inventors: Koshun Saito, Katsuhiro Iwai
  • Patent number: 11024555
    Abstract: The present disclosure provides a semiconductor substrate, including a first patterned conductive layer, a dielectric structure on the first patterned conductive layer, wherein the dielectric structure having a side surface, a second patterned conductive layer on the dielectric structure and extending on the side surface, and a third patterned conductive layer on the second patterned conductive layer and extending on the side surface. The present disclosure provides a semiconductor package including the semiconductor substrate. A method for manufacturing the semiconductor substrate and the semiconductor package is also provided.
    Type: Grant
    Filed: May 19, 2020
    Date of Patent: June 1, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Cheng-Lin Ho, Chih-Cheng Lee
  • Patent number: 11024606
    Abstract: A semiconductor device includes n semiconductor chips stacked via electrical contacting means in the silicon substrate thickness direction, n being an integer larger than 2, a side face of the stacked semiconductor device in the substrate thickness direction being covered by a non-conductive layer. The shape of the side face with respect to a plan view of the stacked semiconductor device may be one of curved, convex, concave or circular.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: June 1, 2021
    Inventor: Makoto Shizukuishi
  • Patent number: 11024593
    Abstract: A method of forming an integrated circuit structure includes forming a patterned passivation layer over a metal pad, with a top surface of the metal pad revealed through a first opening in the patterned passivation layer, and applying a polymer layer over the patterned passivation layer. The polymer layer is substantially free from N-Methyl-2-pyrrolidone (NMP), and comprises aliphatic amide as a solvent. The method further includes performing a light-exposure process on the polymer layer, performing a development process on the polymer layer to form a second opening in the polymer layer, wherein the top surface of the metal pad is revealed to the second opening, baking the polymer, and forming a conductive region having a via portion extending into the second opening.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: June 1, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Da Cheng, Yung-Ching Chao, Chun Kai Tzeng, Cheng Jen Lin, Chin Wei Kang, Yu-Feng Chen, Mirng-Ji Lii
  • Patent number: 11018118
    Abstract: A backlight device and a manufacturing method thereof are provided. The backlight device includes a substrate, a Light-Emitting Diode (LED) layer and a band-pass filter. The LED layer is disposed on the substrate and includes a plurality of LED chips arranged at intervals. The band-pass filter is disposed on the LED layer and is provided with openings formed at positions corresponding to the LED chips.
    Type: Grant
    Filed: November 23, 2018
    Date of Patent: May 25, 2021
    Assignee: Wuhan China Star Optoelectronics Technology Co., Ltd.
    Inventor: Yong Yang
  • Patent number: 11011682
    Abstract: A composite board is provided with a board and a covering member. The board includes a base made of ceramics, first wiring provided on an upper surface of the base, and second wiring provided on a lower surface of the base and electrically connected to the first wiring. The covering member covers the base such that the first wiring and the second wiring are exposed.
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: May 18, 2021
    Assignee: NICHIA CORPORATION
    Inventor: Tadao Hayashi
  • Patent number: 11006514
    Abstract: Semiconductor packages and a method of forming a semiconductor package are described. The semiconductor package has a foundation layer mounted on a motherboard. The semiconductor package also includes a hole in motherboard (HiMB) that is formed in the motherboard. The semiconductor package has one or more capacitors mounted on an electrical shield. The electrical shield may be embedded in the HiMB of the motherboard. Accordingly, the semiconductor package has capacitors vertically embedded between the electrical shield and the HiMB of the motherboard. The semiconductor package may also have one or more HiMB sidewalls formed on the HiMB, where each of the one or more HiMB sidewalls includes at least one or more plated through holes (PTHs) with an exposed layer. The PTHs may be electrically coupled to the capacitors as the capacitors are vertically embedded between the electrical shield sidewalls and the HiMB sidewalls (i.e., three-dimensional (3D) capacitors).
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: May 11, 2021
    Assignee: Intel Corporation
    Inventors: Jia Yan Go, Min Suet Lim, Tin Poay Chuah, Seok Ling Lim, Howe Yin Loo
  • Patent number: 10998273
    Abstract: An electronic assembly, comprising a carrier wafer having a top wafer surface and a bottom wafer surface; an electronic integrated circuit being formed in the carrier wafer and comprising a wafer contact pad on the top wafer surface; said carrier wafer comprising a through-wafer cavity joining the top and bottom wafer surfaces; a component chip having a component chip top surface, a component chip bottom surface and component chip side surfaces, the component chip being held in said through-wafer cavity by direct contact of at least a side surface of said first component chip with an attachment metal that fills at least a portion of said through-wafer cavity; said component chip comprising at least one component contact pad on said component chip top surface; a first conductor connecting said wafer contact pad and said component contact pad.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: May 4, 2021
    Assignee: HRL Laboratories, LLC
    Inventors: Florian G. Herrault, David Brown, Hasan Sharifi, Joel C. Wong, Dean C. Regan, Yan Tang, Helen Fung
  • Patent number: 10998231
    Abstract: A device wafer is provided that includes a substrate having major and minor surfaces, and a plurality of active devices located at the major surface. A eutectic alloy composition is formed at the minor surface of the substrate. The eutectic alloy composition is removed from the minor surface of the substrate such that a portion of the eutectic alloy composition remains at an outer perimeter of the minor surface to strengthen the outer perimeter of the substrate. A bonding layer is deposited over the minor surface and over the portion of the eutectic alloy composition at the outer perimeter of the minor surface. The bonding layer is utilized for joining semiconductor components of the device wafer to secondary structures. Additional eutectic alloy composition may remain on the minor surface of the substrate at the streets to strengthen the substrate during device wafer separation.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: May 4, 2021
    Assignee: NXP USA, Inc.
    Inventors: Colby Greg Rampley, Alan J. Magnus, Jason R. Wright, Jeffrey Lynn Weibrecht, Elijah Blue Foster
  • Patent number: 10992222
    Abstract: A detection circuit and an electronic device using the detection circuit are provided. The detection circuit includes a fourth branch, a fifth branch and a third energy storage unit. The fourth branch includes multiple fourth switches, and the fifth branch includes multiple fifth switches. A preset electrical signal threshold is sampled and applied to the third energy storage unit by controlling the multiple fourth switches in the fourth branch, and a voltage difference between two detection terminals of a first energy storage unit is sampled and applied to the third energy storage unit by controlling the multiple fifth switches in the fifth branch, to compare the voltage difference between the two detection terminals with the preset electrical signal threshold.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: April 27, 2021
    Assignee: Shanghai Awinic Technology Co., LTD
    Inventors: Zhifei Yang, Haijun Zhang, Wei Yao, Jianing Zhou, Liming Du
  • Patent number: 10978408
    Abstract: A package structure including at least one semiconductor chip, an insulating encapsulant, a conductive frame, a supporting frame, a conductive layer and a redistribution layer is provided. The at least one semiconductor chip has an active surface and a backside surface opposite to the active surface. The insulating encapsulant is encapsulating the at least one semiconductor chip. The conductive frame is surrounding the insulating encapsulant. The supporting frame is surrounding the conductive frame. The conductive layer is disposed on the backside surface of the semiconductor chip. The redistribution layer is disposed on and electrically connected to the active surface of the semiconductor chip.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: April 13, 2021
    Assignee: Powertech Technology Inc.
    Inventors: Shang-Yu Chang Chien, Hung-Hsin Hsu, Nan-Chun Lin
  • Patent number: 10971474
    Abstract: A chip package and method of fabricating the same are described herein. The chip package generally includes a stand-off which spaces a die from a substrate to control the collapse of a solder joint coupling the die to the substrate.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: April 6, 2021
    Assignee: XILINX, INC.
    Inventors: Jaspreet Singh Gandhi, Henley Liu
  • Patent number: 10964671
    Abstract: A semiconductor device includes first and second chips that are stacked such that first surfaces of their element layers face each other. Each chip has a substrate, an element layer on a first surface of the substrate, pads on the element layer, and vias that penetrate through the substrate and the element layer. Each via is exposed from a second surface of the substrate and directly connected to one of the pads. The vias include a first via of the first chip directly connected to a first pad of the first chip and a second via of the second chip directly connected to a second pad of the second chip. The pads further include a third pad of the second chip which is electrically connected to the second pad by a wiring in the element layer of the second chip and to the first pad through a micro-bump.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: March 30, 2021
    Assignee: Toshiba Memory Corporation
    Inventor: Masaru Koyanagi
  • Patent number: 10950513
    Abstract: The method comprises the steps of 1) producing first and second blanks (EB1, EB2) by laminating insulating and conductive inner layers (PP, CP, E1) on copper plates forming a base (MB1, MB2), at least one electronic chip (MT, MD) being sandwiched between the blanks, said blanks being produced such that their upper lamination surfaces have matching profiles, 2) stacking and fitting the blanks via their matching profiles, and 3) press-fitting the blanks to form a laminated sub-assembly for an integrated power electronics device. The method uses IMS-type techniques.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: March 16, 2021
    Assignees: INSTITUT VEDECOM, ELVIA PCB
    Inventors: Friedbald Kiel, Olivier Belnoue
  • Patent number: 10924835
    Abstract: The present disclosure provides a voice collection device, comprising: a housing; a microphone assembly disposed inside the housing and including a microphone main body and a microphone circuit board; and a sealing structure disposed between the microphone assembly and an inner side of the housing and including a dust filter and a first adhesive layer. One side of the microphone circuit board is connected to the dust filter. The other side of the microphone circuit board is connected to the microphone main body. The microphone circuit board and the dust filter are bonded to the inner side of the housing. A sound hole is configured on the microphone main body. A first through-hole is configured at a position on the microphone circuit board corresponding to the sound hole. A second through-hole is configured at a position on the housing corresponding to the first through-hole.
    Type: Grant
    Filed: November 20, 2019
    Date of Patent: February 16, 2021
    Assignee: BEIJING SOGOU TECHNOLOGY DEVELOPMENT CO., LTD.
    Inventors: Zhiyu Sun, Walayiding Wailibieke, Peng Zhang
  • Patent number: 10910267
    Abstract: A device includes a substrate, and an alignment mark including a conductive through-substrate via (TSV) penetrating through the substrate.
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: February 2, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsin Chang, Fang Wen Tsai, Jing-Cheng Lin, Wen-Chih Chiou, Shin-Puu Jeng
  • Patent number: 10903231
    Abstract: Disclosed are three-dimensional semiconductor memory devices and methods of fabricating the same. The method includes sequentially forming a sacrificial pattern and a source conductive layer on a substrate, forming a mold structure including a plurality of insulating layers and a plurality of sacrificial layers on the source conductive layer; forming a plurality of vertical structures that penetrate the mold structure, forming a trench that penetrates the mold structure, forming a sacrificial spacer on a sidewall of the trench, removing the sacrificial pattern to form a horizontal recess region; removing the sacrificial spacer, and forming a source conductive pattern that fills the horizontal recess region.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: January 26, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sanghoon Lee, Sunggil Kim, Seulye Kim, Hwaeon Shin, Joonsuk Lee, Hyeeun Hong
  • Patent number: 10861761
    Abstract: Present disclosure provides a method for forming a semiconductor packaged wafer, including providing a semiconductor package having a die on a first side of a wafer, partially molding the die by disposing molding material on the first side of the wafer, a peripheral of the first side is free of molding material at a completion of the partially molding, and bonding the semiconductor package with a carrier from the first side of the wafer. Present disclosure also provides a semiconductor packaged wafer, including a die on a first side of a wafer, a molding encapsulating the die and partially positioning on the first side of the wafer by retracting from a peripheral of the first side of the wafer, and a sealing structure on the peripheral of the first side of the wafer.
    Type: Grant
    Filed: February 21, 2018
    Date of Patent: December 8, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Fu-Chen Chang, Cheng-Lin Huang, Wen-Ming Chen, Shih-Yen Chen, Ruei-Yi Tsai, Pin-Yi Hsin
  • Patent number: 10855250
    Abstract: A communication system using a single crystal acoustic resonator device. The device includes a piezoelectric substrate with a piezoelectric layer formed overlying a transfer substrate. A topside metal electrode is formed overlying the substrate. A topside micro-trench is formed within the piezoelectric layer. A topside metal with a topside metal plug is formed within the topside micro-trench. First and second backside cavities are formed within the transfer substrate under the topside metal electrode. A backside metal electrode is formed under the transfer substrate, within the first backside cavity, and under the topside metal electrode. A backside metal plug is formed under the transfer substrate, within the second backside cavity, and under the topside micro-trench. The backside metal plug is connected to the topside metal plug and the backside metal electrode. The topside micro-trench, the topside metal plug, the second backside cavity, and the backside metal plug form a micro-via.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: December 1, 2020
    Assignee: AKOUSTIS, INC.
    Inventors: Shawn R. Gibb, Ramakrishna Vetury, Jeffrey B. Shealy, Mark D. Boomgarden, Michael P. Lewis, Alexander Y. Feldman
  • Patent number: 10825796
    Abstract: The present disclosure provides a semiconductor package. The semiconductor package includes a device chip and a protecting material. The device chip has an active area and an inactive area arranged around the active area. The protecting material includes a first portion and a second portion, the first portion is disposed within the inactive area and encircles the active area, and the second portion is disposed over a lower surface of the device chip.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: November 3, 2020
    Assignee: Nanya Technology Corporation
    Inventor: Hsih-Yang Chiu
  • Patent number: 10825783
    Abstract: Some embodiments of the present disclosure disclose a method for forming semiconductor packages. The method includes disposing a plurality of semiconductor chips over a top side of a wafer, molding the plurality of semiconductor chips with a first molding material, and after molding the semiconductor chips, forming a composite layer over the plurality of semiconductor chips.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: November 3, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Shing-Yih Shih, Tieh-Chiang Wu
  • Patent number: 10814396
    Abstract: Sintering tool (10) with a cradle for receiving an electronic subassembly (BG) to be sintered, characterized by at least one support bracket (20), arranged at two locations opposite the cradle, for fixing a protective film (30) covering the electronic subassembly (BG).
    Type: Grant
    Filed: September 9, 2015
    Date of Patent: October 27, 2020
    Assignee: Danfoss Silicon Power GmbH
    Inventors: Frank Osterwald, Martin Becker, Lars Paulsen, Jacek Rudzki, Holger Ulrich, Ronald Eisele
  • Patent number: 10818623
    Abstract: Embodiments are directed to a method of forming a semiconductor chip package and resulting structures having a mixed under-bump metallization (UBM) size and pitch on a single die. A first set of UBMs having a first total plateable surface area is formed on a first region of a die. A second set of UBMs having an equal total plateable surface area is formed on a second region of the die. A solder bump having a calculated solder height is applied to a plateable surface of each UBM. The solder height is calculated such that a volume of solder in the first region is equal to a volume of solder in the second region.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: October 27, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Charles L. Arvin, Christopher D. Muzzy
  • Patent number: 10811390
    Abstract: Provided is a die stack structure including a first die and a second die. The first die and the second die are bonded together through a hybrid bonding structure. A bonding insulating layer of the hybrid bonding structure extends to contact with one interconnect structure of the first die or the second die.
    Type: Grant
    Filed: January 21, 2019
    Date of Patent: October 20, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jie Chen, Hsien-Wei Chen, Ming-Fa Chen
  • Patent number: 10811976
    Abstract: The electronic circuit device is provided with: a power conversion circuit having a switching element incorporated therein; and a circuit substrate on which a circuit element constituting the power conversion circuit is mounted and a wiring pattern configured to electrically connect circuit elements is disposed. The power conversion circuit is composed of a pair of switching elements configured to supply energy to a choke coil intermittently in phase. The circuit substrate is constituted of a double-sided substrate in which one switching element is mounted on one main surface while the other switching element is mounted on the other main surface and a wiring pattern is provided in a manner such that a current path including one switching element and a current path including the other switching element overlap each other in plan view and have opposite current directions.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: October 20, 2020
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Yusuke Okagawa, Masayoshi Hirota
  • Patent number: 10804226
    Abstract: The invention relates to a chip card manufacturing method. According to this method, there are produced on the one hand, a module including a substrate supporting contacts on one face, and bonding pads on the other, on the other hand, an antenna on a support. The ends of the antenna are linked to lands of connection lands receiving a drop of soldering material on a connection portion. In order to make the soldered electrical connection between the module and the antenna reliable, the bonding pads extend over a zone covering a surface area less than that of the connection portions. The invention relates also to a chip card whose module includes bonding pads extending over a zone covering a surface area less than that of the connection portions.
    Type: Grant
    Filed: May 3, 2017
    Date of Patent: October 13, 2020
    Assignee: Linxens Holding
    Inventors: Cyril Proye, Eric Eymard
  • Patent number: 10804217
    Abstract: A semiconductor device has a substrate and a semiconductor die disposed over the substrate. An encapsulant is deposited over the semiconductor die and substrate with a surface of the semiconductor die exposed from the encapsulant. A first shielding layer is formed over the semiconductor die. In some embodiments, the first shielding layer includes a stainless steel layer in contact with the surface of the semiconductor die and a copper layer formed over the stainless steel layer. The first shielding layer may further include a protective layer formed over the copper layer. One embodiment has a heatsink bonded to the semiconductor die through a solder layer. A second shielding layer can be formed over a side surface of the semiconductor die.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: October 13, 2020
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: SungWon Cho, ChangOh Kim, Il Kwon Shim, InSang Yoon, KyoungHee Park
  • Patent number: 10793429
    Abstract: A production method includes providing a semiconductor substrate with a wiring layer stack having cutouts on a first main surface region of the semiconductor substrate at which MEMS components are arranged in an exposed manner in the cutouts and projecting through contact elements are arranged at metallization regions of the wiring layer stack; applying a b-stage material layer cured in an intermediate stage on the wiring layer stack, such that the cutouts are covered by the b-stage material layer and the vertically projecting through contact elements are introduced into the b-stage material layer; curing the b-stage material layer to obtain a cured b-stage material layer; thinning the cured b-stage material layer; and applying a redistribution layer (RDL) structure on the thinned, cured b-stage material layer to obtain an electrical connection between the wiring layer stack and the RDL structure via the through contact elements.
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: October 6, 2020
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Matthias Steiert, Christian Geissler, Karolina Zogal
  • Patent number: 10784234
    Abstract: Structures and methods of fabricating semiconductor wafer assemblies that encapsulate one or die in a cavity etched into an oxide bonded semiconductor wafer stack. The methods generally include the steps of positioning the die in the cavity, mechanically and electrically mounting the die to the wafer stack, and encapsulating the die within the cavity by bonding a lid wafer to the wafer stack in one of multiple ways. Semiconductor processing steps are applied to construct the assemblies (e.g., deposition, annealing, chemical and mechanical polishing, etching, etc.) and connecting the die (e.g., bump bonding, wire interconnecting, ultrasonic bonding, oxide bonding, etc.) according to the embodiments described above.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: September 22, 2020
    Assignee: Raytheon Company
    Inventors: John J. Drab, Jason G. Milne
  • Patent number: 10763238
    Abstract: A method of aligning semiconductor chips in a medium includes providing an electrically insulating liquid medium; providing semiconductor chips; forming a suspension with the medium and the semiconductor chips; exposing the semiconductor chips to electromagnetic radiation that generates free charge carriers in the semiconductor chips; arranging the suspension in an electric field in which the semiconductor chips are aligned along the electric field; and curing the medium after aligning the semiconductor chips.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: September 1, 2020
    Assignee: OSRAM OLED GmbH
    Inventors: Philipp Kreuter, Andreas Biebersdorf, Christoph Klemp, Jens Ebbecke, Ines Pietzonka, Petrus Sundgren
  • Patent number: 10727196
    Abstract: A chip packaging structure comprises a die, a carrier, a die attach film, and a plastic package body. The die attach film is disposed on the bottom surface of the die, with a thickness of the die attach film being greater than or equal to 40 micrometers. The die is disposed on the carrier via the die attach film; and the plastic package body is disposed on the carrier and coats a top surface and side surfaces of the die, whereby the overall impact resistance of a chip is improved without changing the structure of the carrier, the expense for making a mold is saved, and moreover, the packaging structure is simple and easy for mass production.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: July 28, 2020
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventor: Junping Luo
  • Patent number: 10700032
    Abstract: An embodiment is a device comprising a substrate, a metal pad over the substrate, and a passivation layer comprising a portion over the metal pad. The device further comprises a metal pillar over and electrically coupled to the metal pad, and a passive device comprising a first portion at a same level as the metal pillar, wherein the first portion of the passive device is formed of a same material as the metal pillar.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: June 30, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shuo-Mao Chen, Der-Chyang Yeh, Li-Hsien Huang
  • Patent number: 10700037
    Abstract: In some examples, a device includes a semiconductor element, a layer element, and a single connector element electrically connecting the semiconductor element and the layer element. In some examples, the single connector element includes two or more discrete connector elements, and each discrete connector element of the two or more discrete connector elements electrically connects the semiconductor element and the layer element. In some examples, the single connector element also includes conductive material attached to the two or more discrete connector elements.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: June 30, 2020
    Assignee: Infineon Technologies AG
    Inventors: Eung San Cho, Thorsten Meyer, Xaver Schloegel, Thomas Behrens, Josef Hoeglauer
  • Patent number: 10692764
    Abstract: A device includes a substrate, and an alignment mark including a conductive through-substrate via (TSV) penetrating through the substrate.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: June 23, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsin Chang, Fang Wen Tsai, Jing-Cheng Lin, Wen-Chih Chiou, Shin-Puu Jeng