Packaging (e.g., With Mounting, Encapsulating, Etc.) Or Treatment Of Packaged Semiconductor Patents (Class 438/106)
  • Patent number: 11521878
    Abstract: An adsorption device includes a substrate and a magnetic film on a surface of the substrate. The substrate has magnetic properties and is capable of generating magnetic field. The magnetic film partially covers the surface. The magnetic film generates a magnetic field having a direction that is opposite to a direction of the magnetic field generated by the substrate. Portions of the surface of the substrate not covered by the magnetic film form positions to attract and adsorb target objects, and other portion of the surface of the substrate covered by the magnetic film is not able to attract any target object.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: December 6, 2022
    Assignee: Century Technology (Shenzhen) Corporation Limited
    Inventors: Po-Liang Chen, Yung-Fu Lin, Hirohisa Tanaka, Yasunori Shimada
  • Patent number: 11521947
    Abstract: An apparatus includes an Integrated Circuit (IC). A first pillar includes a first end and a second end. The first end is connected to the IC and the second end includes a first attachment point collinear with a first central axis of the first pillar. The first attachment point includes a first solder volume capacity. A second pillar includes a third end and a fourth end. The third end is connected to the IC and the fourth end includes a second attachment point disposed on a side of the second pillar facing the first pillar. The second attachment point includes a second solder volume capacity being less than the first solder volume capacity. A first distance between the first end and the second end is less than a second distance between the third end and the fourth end.
    Type: Grant
    Filed: July 14, 2021
    Date of Patent: December 6, 2022
    Assignee: NXP USA, INC.
    Inventor: Kabir Mirpuri
  • Patent number: 11515254
    Abstract: A semiconductor chip may include: a body portion including a front surface and a back surface; penetrating electrodes penetrating the body portion; and back connection electrodes disposed over the back surface of the body portion and connected to the penetrating electrodes, wherein the penetrating electrodes include a power penetrating electrode for transmitting a power voltage and a ground penetrating electrode for transmitting a ground voltage, the back connection electrodes include a power back connection electrode connected to the power penetrating electrode and a ground back connection electrode connected to the ground penetrating electrode, and one power back connection electrode is connected with two or more power penetrating electrodes, and one ground back connection electrode is connected with two or more ground penetrating electrodes.
    Type: Grant
    Filed: November 3, 2020
    Date of Patent: November 29, 2022
    Assignee: SK hynix Inc.
    Inventors: Ki Bum Kim, Bok Kyu Choi
  • Patent number: 11500256
    Abstract: System and method for a rewritable color display on soft material comprising: a textile platform; a canvas display, comprising color changing substances, polymers, and a stabilizer. The system functions as a textile (e.g. article of clothing, blanket, sport pennant, etc.) with a rewritable display, wherein the user may alter the design on the canvas display. The system may further include a processor module, wherein the processor module is configured to alter the rewritable display design and/or clean the textile platform.
    Type: Grant
    Filed: March 25, 2021
    Date of Patent: November 15, 2022
    Inventor: Raj Bhakta
  • Patent number: 11497142
    Abstract: An assembly (110) for dissipating heat generated by a heat generating electrical component (16) which is surface mounted on a circuit board (11) in a surface mounting process. The assembly comprises a heat buffer (120) made of a thermally and electrically conducing material, and being surface mounted on the circuit board (11) so as to be soldered to a thermal flag (18) of the heat generating electrical component (16). The assembly further comprises a heat sink (12) in thermal contact with the heat buffer, and a galvanic separation (13) between the heat buffer and heat sink. The heat capacitance of the heat buffer can absorb short term increases in heat dissipation from the electrical component, before the heat is further dissipated to the galvanically separated heat sink. This may drastically improve performance of the surface mounted component.
    Type: Grant
    Filed: October 3, 2019
    Date of Patent: November 8, 2022
    Assignee: AROS ELECTRONICS AB
    Inventor: Jerker Hellström
  • Patent number: 11482515
    Abstract: A semiconductor device includes a semiconductor module, a substrate, and a filler. The semiconductor module includes a semiconductor chip, a control integrated circuit (IC) configured to control driving of the semiconductor chip, and a package sealing the semiconductor chip and the control IC with an insulation material. On the substrate, the semiconductor module is mounted. The filler is provided between a lower surface of the package of the semiconductor module and the substrate. The substrate includes a through hole being provided at a position below the package and closer to the control IC than to the semiconductor chip in the package.
    Type: Grant
    Filed: August 11, 2020
    Date of Patent: October 25, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventor: Toma Takao
  • Patent number: 11450575
    Abstract: A system and method for die crack detection in a CMOS bonded array includes a capacitor that is formed in an edge seal, where one of the capacitor plates is in the edge seal portion of a first wafer, and the other capacitor plate is in the edge seal portion of a second wafer. A crack in the die can be detected by applying an alternating current waveform to a testing contact on the integrated circuit and monitoring for a shift in the alternating current waveform, as a crack would cause modulation in the capacitance.
    Type: Grant
    Filed: February 22, 2021
    Date of Patent: September 20, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Jayavel Pachamuthu, Kirubakaran Periyannan, Daniel Linnen
  • Patent number: 11451052
    Abstract: Systems and methods integrate advanced solar tracker, battery, inverter, and software technologies to improve performance, plant output, and costs. The systems may incorporate an advanced vanadium flow battery (VFB) that is DC-voltage (DV)-coupled to photovoltaic (PV) arrays for high, round-trip efficiency. The systems incorporate a DC architecture that optimizes performance for commercial, industrial, agricultural, and utility applications. A distributed direct current (DC) power system includes a centralized, single-stage inverter; PV arrays; maximum power point tracking (MPPT) converters coupled between the PV arrays and the centralized, single-stage inverter; batteries; and DC-DC battery converters (DCBCs) coupled to the batteries. The MPPT converters maximize solar power production by the PV arrays and minimize mismatch between the PV arrays.
    Type: Grant
    Filed: May 3, 2019
    Date of Patent: September 20, 2022
    Assignee: NEXTRACKER LLC
    Inventors: Alexander W. Au, Yang Liu
  • Patent number: 11450651
    Abstract: A LED device includes multiple LED chips each including opposite first and second surfaces, a side surface, and an electrode assembly disposed on the second surface and including first and second electrodes. The first surface of each of the LED chips is a light exit surface. The LED device further includes an electric circuit layer assembly disposed on the second surfaces of the LED chips and having opposite first and second surfaces and a side surface. The first surface is electrically connected to the first and second electrodes. The LED device further includes an encapsulating layer enclosing the LED chips and the electric circuit layer assembly to expose the second surface of the electric circuit layer assembly.
    Type: Grant
    Filed: January 14, 2020
    Date of Patent: September 20, 2022
    Assignee: QUANZHOU SAN'AN SEMICONDUCTOR TECHNOLOGY CO., LTD.
    Inventors: Junpeng Shi, Chen-Ke Hsu, Chang-Chin Yu, Yanqiu Liao, Zhenduan Lin, Zhaowu Huang, Senpeng Huang
  • Patent number: 11450697
    Abstract: A chip package including a substrate, a first conductive structure, and an electrical isolation structure is provided. The substrate has a first surface and a second surface opposite the first surface), and includes a first opening and a second opening surrounding the first opening. The substrate includes a sensor device adjacent to the first surface. A first conductive structure includes a first conductive portion in the first opening of the substrate, and a second conductive portion over the second surface of the substrate. An electrical isolation structure includes a first isolation portion in the second opening of the substrate, and a second isolation portion extending from the first isolation portion and between the second surface of the substrate and the second conductive portion. The first isolation portion surrounds the first conductive portion.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: September 20, 2022
    Assignee: XINTEC INC.
    Inventors: Kuei-Wei Chen, Chia-Ming Cheng, Chia-Sheng Lin
  • Patent number: 11443957
    Abstract: Some embodiment structures and methods are described. A structure includes an integrated circuit die at least laterally encapsulated by an encapsulant, and a redistribution structure on the integrated circuit die and encapsulant. The redistribution structure is electrically coupled to the integrated circuit die. The redistribution structure includes a first dielectric layer on at least the encapsulant, a metallization pattern on the first dielectric layer, a metal oxide layered structure on the metallization pattern, and a second dielectric layer on the first dielectric layer and the metallization pattern. The metal oxide layered structure includes a metal oxide layer having a ratio of metal atoms to oxygen atoms that is substantially 1:1, and a thickness of the metal oxide layered structure is at least 50 ?. The second dielectric layer is a photo-sensitive material. The metal oxide layered structure is disposed between the metallization pattern and the second dielectric layer.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: September 13, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jing-Cheng Lin, Cheng-Lin Huang
  • Patent number: 11443992
    Abstract: A semiconductor device includes a semiconductor chip including a substrate and a MEMS element, wherein the substrate includes a surface, and wherein the MEMS element is disposed at the surface of the substrate and the MEMS element includes a sensitive area; a first electrical interconnect structure electrically connected to the surface of the substrate; a carrier electrically connected to the first electrical interconnect structure; and a first stress relieve spring entrenched in the carrier, wherein the first stress relieve spring is a single integral channel that comprises two parallel channels that join together at a periphery of the first electrical interconnect structure to form the single integral channel that wraps around a portion of the periphery of the first electrical interconnect structure, wherein the two parallel channels extend outward, in parallel, from the periphery of the first electrical interconnect structure to a first termination region of the carrier.
    Type: Grant
    Filed: January 7, 2021
    Date of Patent: September 13, 2022
    Inventor: Dirk Hammerschmidt
  • Patent number: 11439037
    Abstract: Disclosed herein are integrated circuit (IC) packages with a heat generating electronic component and a fluid impingement cooling apparatus having a plurality of rotatable nozzles, as well as related devices and methods. In some embodiments, an IC device assembly may include a plurality of rotatable nozzles disposed in a nozzle plate, wherein the plurality of rotatable nozzles are rotatable individually; a microcontroller to identify a hotspot on a target surface of an IC device, wherein the hotspot has a temperature that is greater than a threshold temperature; and a motor coupled to the plurality of rotatable nozzles, wherein the motor causes one or more of the rotatable nozzles to rotate to impinge fluid on the hotspot.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: September 6, 2022
    Assignee: Intel Corporation
    Inventors: Prabhakar Subrahmanyam, Arun Krishnamoorthy
  • Patent number: 11435789
    Abstract: Disclosed is a portable communication device comprising: a display module comprising a display layer facing the front surface of the portable communication device, and a conductive layer formed beneath the display layer; a conductive supporting member arranged beneath the conductive layer; an antenna module arranged adjacent to the side of the conductive supporting member; a printed circuit board which is arranged beneath the conductive layer, and which has a display driving circuit arranged therein for controlling the display module; and a conductive adhesive layer arranged between the conductive layer and the conductive supporting member.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: September 6, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yongwoog Shin, Yonghyun Park, Joonyoung Son, Kyonghwan Cho, Sangho Hong
  • Patent number: 11429482
    Abstract: Systems and methods for correcting data errors in memory caused by high-temperature processing of the memory are provided. An integrated circuit (IC) die including a memory is formed. Addresses of memory locations that are susceptible to data loss when subjected to elevated temperatures are determined. Bits of data are written to the memory, where the bits of data include a set of bits written to the memory locations. The set of bits are written to a storage device of the IC die that is not susceptible to data loss when subjected to the elevated temperatures, the subset of bits comprise compressed code. At least one of the bits stored at the addresses is overwritten after subjecting the IC die to an elevated temperature. The at least one of the bits is overwritten based on the set of bits written to the storage device.
    Type: Grant
    Filed: February 18, 2021
    Date of Patent: August 30, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yu-Der Chih, Ching-Huang Wang, Yi-Chun Shih, Meng-Chun Shih, C. Y. Wang
  • Patent number: 11424152
    Abstract: Various embodiments process semiconductor devices. In one embodiment, a release layer is applied to a handler. The release layer comprises at least one additive that adjusts a frequency of electro-magnetic radiation absorption property of the release layer. The additive comprises, for example, a 355 nm chemical absorber and/or chemical absorber for one of more wavelengths in a range comprising 600 nm to 740 nm. The at least one singulated semiconductor device is bonded to the handler. The at least one singulated semiconductor device is packaged while it is bonded to the handler. The release layer is ablated by irradiating the release layer through the handler with a laser. The at least one singulated semiconductor device is removed from the transparent handler after the release layer has been ablated.
    Type: Grant
    Filed: February 3, 2020
    Date of Patent: August 23, 2022
    Assignee: International Business Machines Corporation
    Inventors: Paul S. Andry, Bing Dang, Jeffrey Donald Gelorme, Li-Wen Hung, John U. Knickerbocker, Cornelia Kang-I Tsang
  • Patent number: 11417627
    Abstract: A micro LED display manufacturing method according to various embodiments may include: a first operation of bonding an anisotropic conductive film including a plurality of conductive particles onto one surface of a prepared substrate, the one surface including a circuit part; a second operation of forming a bonding layer on the anisotropic conductive film; a third operation of positioning a plurality of micro LED chips above the bonding layer, the micro LED chips being arranged on a carrier substrate while being spaced a first distance apart from the substrate; a fourth operation of attaching the plurality of micro LED chips onto the bonding layer by means of laser transfer; and a fifth operation of forming a conductive structure for electrically connecting a connection pad to the circuit part through the conductive particles by means of heating and pressurizing.
    Type: Grant
    Filed: August 12, 2020
    Date of Patent: August 16, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jamyeong Koo, Sungyong Min, Byunghoon Lee, Changjoon Lee, Changkyu Chung, Youngkyong Jo
  • Patent number: 11417559
    Abstract: To manufacture a semiconductor package, a package intermediate structure having an element area and a dummy area is formed. A carrier substrate including an adhesion layer is formed. The adhesion layer includes a first area with a first adhesion strength and a second area with a second adhesion strength that is different from the first adhesion strength. The package intermediate structure is supported by the carrier substrate so that the element area is adjacent the first area and the dummy area is adjacent the second area. The package intermediate structure is processed while the package intermediate structure is supported by the carrier substrate.
    Type: Grant
    Filed: December 4, 2020
    Date of Patent: August 16, 2022
    Inventors: Yeonga Kim, Seonho Lee
  • Patent number: 11411038
    Abstract: To achieve a size reduction of a semiconductor package while securing stability in mounting. Three terminals t1, t2, and t4 are individually arranged on a semiconductor package 10 having a rectangular shape as viewed in plan in such a manner that the center in the longitudinal direction of the semiconductor package 10 of each of the three terminals t1, t2, and t4 and the center in the longitudinal direction of each of the other terminals are not overlapped with each other as viewed from the side of the long side.
    Type: Grant
    Filed: August 25, 2020
    Date of Patent: August 9, 2022
    Assignee: Asahi Kasei Microdevices Corporation
    Inventors: Osamu Shirata, Yusuke Hidaka
  • Patent number: 11383465
    Abstract: The machine comprises a solid matrix (1), a deformable body (2) joined to the surface of said matrix (1), a shaping mould (3) and a securing system system (5) for the fibre structure (4). The matrix (1) is a solid element having a functional face, the geometry of which depends on the part to be manufactured. The deformable body (2) has an initial geometry that depends on the geometry to be given to the fibre structure (4). The shaping mould (3) has the geometry to be given to the fibre structure (4) during the process of adaptation to the shaping mould (3), and the shaping mould (3) is located such that the deformable body (2) is located between said shaping mould (3) and the matrix (1).
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: July 12, 2022
    Assignee: UNIVERSIDAD POLITÉCNICA DE MADRID
    Inventors: Alejandro Abou-Assali Rodríguez, Enrique Chacón Tanarro, Juan Manuel Muñoz Gijosa, Rafael Escobar Orellana
  • Patent number: 11375619
    Abstract: A packaging structure, includes: a dielectric layer; at least one inner wiring layer embedded in the dielectric layer; at least two outer wiring layers arranged two sides of the at least one inner wiring layer and combined with the dielectric layer; and at least one electronic component embedded in the dielectric layer; each inner wiring layer including at least two spaced supporting pads, and each supporting pad including a main body and a protruding portion extending outward from a periphery of the main body, the packaging structure further including at least two spaced positioning pillars, and each positioning pillar correspondingly connected to one main body, each electronic component arranged between at least two positioning pillars, and an end of each electronic component being in contact with protruding portions of at least two supporting pads, thereby packaging the electronic component accurately. The present invention also needs to provide a method for manufacturing the packaging structure.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: June 28, 2022
    Assignees: HongQiSheng Precision Electronics (QinHuangDao) Co., Ltd., Avary Holding (Shenzhen) Co., Limited.
    Inventor: Chih-Chieh Fu
  • Patent number: 11372491
    Abstract: The present disclosure provides a touch screen, a manufacturing method thereof, and a touch display device. The touch screen includes: a substrate; a touch layer and a bonding layer that are on a side of the substrate, the bonding layer being connected to the touch layer by a metal wire; a flexible circuit board connected to the bonding layer; a polarizer on a side of the touch layer away from the substrate and provided with a notch exposing the bonding layer and at least a portion of the metal wire; an insulating light-shielding strip covering the portion of the metal wire exposed by the notch and extending to a side of the polarizer close to the substrate; and a cover plate on a side of the polarizer away from the substrate and including a transparent window area and a shielding area around the transparent window area.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: June 28, 2022
    Assignees: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Zewen Li, Hongqiang Luo, Kwanggyun Jang, Zhen Guo
  • Patent number: 11362101
    Abstract: A three-dimensional memory device includes a plurality of conductive layers and insulating layers alternately formed to define a multi-layer stacked structure on a first region of a semiconductor substrate. The multi-layer stacked structure includes a stair structure and a non-stair structure. A plurality of memory structures are located in the non-stair structure to form a memory array region, and each memory structure passes through the conductive layers and the insulating layers. A plurality of bow-height adjustment features are located in a second region of the semiconductor substrate.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: June 14, 2022
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chien-Lan Chiu, Chun-Min Cheng
  • Patent number: 11355446
    Abstract: The present disclosure relates to a semiconductor chip scale package including a semiconductor die. The semiconductor die has a first major surface opposing a second major surface, a plurality of side walls extending between the first major surface and second major surface, a plurality of electrical contacts arranged on the second major surface of the semiconductor die, and an insulating material disposed on the plurality of side walls and on the first major surface. The insulating material includes a machine readable identifier by which a semiconductor chip scale packaging type is identifiable by an identification apparatus that reads the machine readable identifier, and the machine readable identifier includes a colour component.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: June 7, 2022
    Assignee: Nexperia B.V.
    Inventors: Tobias Sprogies, Jan Fischer
  • Patent number: 11355474
    Abstract: A semiconductor package including an insulating encapsulation, an integrated circuit component, and conductive elements is provided. The integrated circuit component is encapsulated in the insulating encapsulation, wherein the integrated circuit component has at least one through silicon via protruding from the integrated circuit component. The conductive elements are located on the insulating encapsulation, wherein one of the conductive elements is connected to the at least one through silicon via, and the integrated circuit component is electrically connected to the one of the conductive elements through the at least one through silicon via.
    Type: Grant
    Filed: June 20, 2020
    Date of Patent: June 7, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Feng-Cheng Hsu, Shin-Puu Jeng
  • Patent number: 11349278
    Abstract: A stem for a semiconductor package, includes an eyelet having a first surface, a second surface opposite to the first surface, and a through-hole penetrating the eyelet from the first surface to the second surface, a metal base bonded to the second surface of the eyelet so as to cover one end of the through-hole, and a metal block having one end thereof inserted into the through-hole and bonded to the metal base inside the through-hole, and another end projecting from the first surface of the eyelet and including a device mounting surface on which a semiconductor device is mounted. The metal base has a thermal conductivity higher than or equal to a thermal conductivity of the eyelet, and a surface at the one end of the metal block matches the second surface of the eyelet.
    Type: Grant
    Filed: January 8, 2020
    Date of Patent: May 31, 2022
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Wataru Katayama, Ryota Mitsui
  • Patent number: 11349053
    Abstract: Embodiments relate to the design of an electronic device capable having flexible interconnects that connect together a first body and a second body of the electronic device. The flexible interconnects allow the electrical device to better withstand thermal-mechanical stress during fabrication of the electronic device and user usage of the electronic device.
    Type: Grant
    Filed: January 14, 2020
    Date of Patent: May 31, 2022
    Assignee: Facebook Technologies, LLC
    Inventors: Zheng Sung Chio, Daniel Brodoceanu, Ali Sengül, Oscar Torrents Abad, Jeb Wu, Pooya Saketi, Chao Kai Tung, Tennyson Nguty, Allan Pourchet
  • Patent number: 11349096
    Abstract: The present disclosure relates to a flexible display substrate and a method of manufacturing the same, a display panel and a display apparatus. The flexible display substrate has a display region and a non-display region. In some embodiments, the flexible display substrate comprises: a base substrate and an inorganic film layer provided on the base substrate, wherein the inorganic film layer of the non-display region is provided with a groove; and a filling structure for filling the groove.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: May 31, 2022
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Tao Wang, Peng Cai
  • Patent number: 11342274
    Abstract: A semiconductor package is disclosed. The semiconductor package includes a back-side wiring substrate and a front-side redistribution layer which are in parallel, and a connector, a semiconductor chip and an encapsulator which are between the back-side wiring substrate and the front-side redistribution layer. The encapsulator surrounds surfaces of the connector and the semiconductor chip. The back-side wiring substrate includes a core layer, a back-side via plug extending through the core layer, and a back-side redistribution layer on the back-side via plug.
    Type: Grant
    Filed: August 11, 2020
    Date of Patent: May 24, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sangkyu Lee, Jingu Kim, Kyungdon Mun, Shanghoon Seo, Jeongho Lee
  • Patent number: 11328930
    Abstract: Implementations of a method of forming a semiconductor package may include forming electrical contacts on a first side of a wafer, applying a photoresist layer to the first side of the wafer, patterning the photoresist layer, and etching notches into the first side of the wafer using the photoresist layer. The method may include applying a first mold compound into the notches and over the first side of the wafer, grinding a second side of the wafer opposite the first side of the wafer to the notches formed in the first side of the wafer, applying one of a second mold compound and a laminate resin to a second side of the wafer, and singulating the wafer into semiconductor packages. Six sides of a die included in each semiconductor package may be covered by one of the first mold compound, the second mold compound, and the laminate resin.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: May 10, 2022
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Eiji Kurose
  • Patent number: 11315866
    Abstract: A semiconductor device includes: a substrate including a main surface; a wiring portion including a first conductive layer formed on the main surface, and a first plating layer which is provided on the first conductive layer and on which an oxide film is formed; a semiconductor element including an element mounting surface and an element electrode formed on the element mounting surface; a bonding portion including a second plating layer made of the same material as the first plating layer and laminated on the first conductive layer, and a solder layer laminated on the second plating layer and bonded to the element electrode; and a sealing resin covering the semiconductor element.
    Type: Grant
    Filed: June 5, 2020
    Date of Patent: April 26, 2022
    Assignee: ROHM CO., LTD.
    Inventors: Isamu Nishimura, Hirofumi Takeda, Hideaki Yanagida, Taro Hayashi, Natsuki Sakamoto
  • Patent number: 11309133
    Abstract: The multilayer electronic component includes a capacitor body having first to sixth surfaces; first and second external electrodes including first and second connecting portions, and first and second band portions; first and second connection terminals connected to the first band portion; and third and fourth connection terminals connected to the second band portion. The first and second connection terminals include a first connection surface facing the first band portion, a second connection surface opposing the first connection surface, and a first circumferential surface connecting the first and second connection surfaces, a cross section of the first circumferential surface being circular.
    Type: Grant
    Filed: April 28, 2020
    Date of Patent: April 19, 2022
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Heung Kil Park, Hun Gyu Park, Se Hun Park, Gu Won Ji
  • Patent number: 11302651
    Abstract: A technique relates to an electronic package. A substrate is configured to receive a chip. A stiffener is attached to the substrate. The stiffener includes a core material with a first material formed on opposing sides of the core material.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: April 12, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kamal K. Sikka, Krishna R. Tunga, Hilton T. Toy, Thomas Weiss, Shidong Li, Sushumna Iruvanti
  • Patent number: 11276764
    Abstract: A device including a semiconductor die, a first contact, a second contact, a third contact, a first passivation layer, a second passivation layer and an interconnect metal. The semiconductor die may include a plurality of semiconductor layers disposed on a GaAs substrate. The first contact may be electrically coupled to a semiconductor emitter layer. The second contact may be electrically coupled to a semiconductor base layer. The third contact may be electrically coupled to a semiconductor sub-collector layer. The first passivation layer may cover one or more of the semiconductor and the contacts. The first passivation layer may comprise an inorganic insulator. The second passivation layer may comprise an inorganic insulator or organic polymer with low dielectric constant deposited on the passivation layer. The interconnect metal may be coupled to the first contact and separated from the first passivation layer by the second passivation layer.
    Type: Grant
    Filed: August 9, 2020
    Date of Patent: March 15, 2022
    Assignee: Global Communication Semiconductors, LLC
    Inventors: Yuefei Yang, Shing-Kuo Wang, Dheeraj Mohata, Liping Daniel Hou
  • Patent number: 11264356
    Abstract: A method of manufacturing packages is disclosed. In one example, the method comprises providing an electrically conductive sheet being continuous at least in a mounting region, mounting first main surfaces of a plurality of electronic components on the continuous mounting region of the sheet and forming interconnect structures for electrically coupling second main surfaces of the electronic components with the sheet. The second main surfaces oppose the first main surfaces. After the forming, structuring the sheet.
    Type: Grant
    Filed: April 7, 2020
    Date of Patent: March 1, 2022
    Assignee: Infineon Technologies AG
    Inventors: Thorsten Meyer, Thomas Behrens, Andreas Grassmann, Martin Gruber, Thorsten Scharf
  • Patent number: 11262197
    Abstract: An optical module includes: a carrier; an optical element disposed on the upper side of the carrier; and a housing disposed on the upper side of the carrier, the housing defining an aperture exposing at least a portion of the optical element, an outer sidewall of the housing including at least one singulation portion disposed on the upper side of the carrier, wherein the singulation portion of the housing is a first portion of the housing, and wherein the housing further includes a second portion and a surface of the singulation portion of the housing is rougher than a surface of the second portion of the housing.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: March 1, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Ying-Chung Chen, Hsun-Wei Chan, Lu-Ming Lai, Kuang-Hsiung Chen
  • Patent number: 11257768
    Abstract: The object is to provide a technique that can prevent cracks from appearing in an undesirable portion in a resin. A semiconductor device includes an electronic circuit including a semiconductor element, a metal electrode directly connected to the electronic circuit, and an encapsulation resin. The encapsulation resin encapsulates the electronic circuit and the metal electrode. An end portion of the metal electrode on a surface opposite to a surface facing the electronic circuit is acute-shaped, and an end portion of the metal electrode on the surface facing the electronic circuit is arc-shaped or obtuse-shaped.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: February 22, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventor: Yuji Imoto
  • Patent number: 11257730
    Abstract: An electronic component module includes an electronic component, a resin structure, a wiring portion, and a shield portion. The resin structure covers a second main surface and at least a portion of a side surface of the electronic component. The wiring portion is electrically connected to the electronic component. The shield portion includes a first conductor layer and a second conductor layer. The first conductor layer is spaced away from the electronic component between the electronic component and the resin structure, and has electrical conductivity. The second conductor layer is spaced away from the wiring portion between the wiring portion and the resin structure, and has electrical conductivity. In the shield portion, the first conductor layer and the second conductor layer are integrated.
    Type: Grant
    Filed: February 3, 2020
    Date of Patent: February 22, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Takashi Iwamoto
  • Patent number: 11239138
    Abstract: Methods of packaging semiconductor devices and packaged semiconductor devices are disclosed. In some embodiments, a method of packaging a semiconductor device includes coupling through-vias to an insulating material, each of the through-vias having a first width. Dies are also coupled to the insulating material. A portion of the insulating material is removed proximate each of the through-vias. The portion of the insulating material proximate each of the through-vias removed has a second width, the second width being less than the first width.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: February 1, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Li-Hui Cheng, Po-Hao Tsai, Jing-Cheng Lin
  • Patent number: 11235328
    Abstract: An apparatus includes a polymer base layer having a surface. A die that includes a fluid manipulation surface that is substantially coplanar with the surface of the polymer base layer. The die includes a control electrode to generate an electric field to perform microfluidic manipulation of fluid across the fluid manipulation surface of the die.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: February 1, 2022
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Michael W. Cumbie, Viktor Shkolnikov, Chien-Hua Chen
  • Patent number: 11217499
    Abstract: A semiconductor package structure includes a substrate; a first die on the substrate, wherein an active surface of the first die is facing away from the substrate; a second die on the active surface of the first die, electrically connected to the first die through a plurality of conductive terminals; and a sealing structure on the active surface of the first die, surrounding the plurality of conductive terminals and abutting the second die thereby forming a cavity between the first die and the second die. A method for manufacturing the semiconductor package structure is also provided.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: January 4, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chi Sheng Tseng, Lu-Ming Lai, Hui-Chung Liu
  • Patent number: 11213690
    Abstract: A multi-chip modular wafer level package of a high voltage unit for an implantable cardiac defibrillator includes one or more high voltage (HV) component chips encapsulated with other components thereof in a polymer mold compound of a single reconstituted wafer, wherein all interconnect segments are preferably located on a single side of the wafer. To electrically couple a contact surface of each HV chip, located on a side of the chip opposite the interconnect side of the wafer, the reconstituted wafer may include conductive through polymer vias; alternately, either wire bonds or layers of conductive polymer are formed to couple the aforementioned contact surface to the corresponding interconnect, prior to encapsulation of the HV chips. In some cases one or more of the components encapsulated in the reconstituted wafer of the package are reconstituted chips.
    Type: Grant
    Filed: June 15, 2012
    Date of Patent: January 4, 2022
    Assignee: Medtronic, Inc.
    Inventors: Mark R. Boone, Mohsen Askarinya, Randolph E. Crutchfield, Erik J. Herrmann, Mark S. Ricotta, Lejun Wang
  • Patent number: 11211346
    Abstract: A semiconductor device has a top metal layer, a first passivation layer over the top metal layer, a first redistribution layer over the first passivation layer, a first polymer layer, and a first conductive via extending through the first polymer layer. The first polymer layer is in physical contact with the first passivation layer.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: December 28, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Tin-Hao Kuo, Chung-Shi Liu, Hao-Yi Tsai
  • Patent number: 11211371
    Abstract: In an embodiment, a structure includes: a graphics processor device; a passive device coupled to the graphics processor device, the passive device being directly face-to-face bonded to the graphics processor device; a shared memory device coupled to the graphics processor device, the shared memory device being directly face-to-face bonded to the graphics processor device; a central processor device coupled to the shared memory device, the central processor device being directly back-to-back bonded to the shared memory device, the central processor device and the graphics processor device each having active devices of a smaller technology node than the shared memory device; and a redistribution structure coupled to the central processor device, the shared memory device, the passive device, and the graphics processor device.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: December 28, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Hua Yu, Wei Ling Chang, Chuei-Tang Wang, Chieh-Yen Chen
  • Patent number: 11205769
    Abstract: A method of manufacturing a display panel includes preparing a work substrate that includes a mother substrate that has a plurality of cell areas, a light emitting element layer formed in each of the cell areas, and an encapsulation layer formed on each cell area, disposing a plurality of protective films in the cell areas, respectively, that cover the light emitting element layer and the encapsulation layer, cutting the work substrate along cutting lines at an outer side of the protective films of each cell area to form a preliminary display panel, grinding side surfaces of the preliminary display panel, and removing the protective films from each ground preliminary display panel to form the display panel.
    Type: Grant
    Filed: April 22, 2020
    Date of Patent: December 21, 2021
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Younghoon Lee, Youngji Kim, Yiseul Um, Wonje Jo, Young Seo Choi, Dongwon Han
  • Patent number: 11171109
    Abstract: Semiconductor device packages may include a first semiconductor device over a substrate and a second semiconductor device over the first semiconductor device. An active surface of the second semiconductor device may face away from the substrate. Electrical interconnections may extend from bond pads of the second semiconductor device, along surfaces of the second semiconductor device, first semiconductor device, and substrate to pads of routing members of the substrate. The electrical interconnections may include conductors in contact with the bond pads and the routing members and a dielectric material interposed between the conductors and the first semiconductor device, the second semiconductor device and the substrate between the bond pads and the pad of the routing members. An encapsulant distinct from the dielectric material may cover the electrical interconnections, the first semiconductor device, the second semiconductor device, and an upper surface of the substrate.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: November 9, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Po Chih Yang, Yu Jen Chen, Po Chen Kuo, Shih Wei Liang
  • Patent number: 11171074
    Abstract: A heat sink board according to an embodiment of the present invention includes a heat sink layer, an insulated layer formed on the heat sink layer, and a metal layer formed on the insulated layer, wherein both end parts of the heat sink layer and both end parts of the insulated layer are respectively projected further than the both end parts of the metal layer.
    Type: Grant
    Filed: July 8, 2020
    Date of Patent: November 9, 2021
    Assignee: JMJ Korea Co., Ltd.
    Inventors: Yun Hwa Choi, Jeonghun Cho
  • Patent number: 11158640
    Abstract: An apparatus comprising first and second interconnections spaced apart from one another, an interlayer insulating material over the first and second interconnections, first and second contacts in the interlayer insulating material and spaced apart from one another, third and fourth interconnections over the interlayer insulating material and spaced apart from one another, and compensation capacitors in a capacitor region. The third interconnections are coupled with the first interconnections through the first contacts and the fourth interconnections are coupled with the second interconnections through the second contacts. The compensation capacitors comprise lower electrodes over the interlayer insulating material, dielectric materials over the lower electrodes, and upper electrodes over the dielectric materials. The lower electrodes comprise edge portions in contact with the second contacts.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: October 26, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Shigeru Sugioka, Keizo Kawakita
  • Patent number: 11152605
    Abstract: Method for producing a positive electrode for a solid-state lithium microbattery comprising the following successive steps: supplying of a substrate made of ceramic, glass or silicon, locally covered with a metal layer, depositing of a cathodic layer made of a positive electrode material, for example made of mixed lithium oxide, the cathodic layer having a thickness greater than 1 ?m, a first portion of the cathodic layer covering the substrate and a second portion of the cathodic layer covering the metal layer, intended to form the positive electrode, carrying out of a heat treatment at a temperature greater than or equal to 400° C., on the cathodic layer, in such a way as to crystallise the second portion of the cathodic layer in order to form a positive electrode, and in such a way as to delaminate the first portion of the cathodic layer.
    Type: Grant
    Filed: February 14, 2019
    Date of Patent: October 19, 2021
    Assignee: COMMISSARIAT À L'ÉNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVES
    Inventors: Messaoud Bedjaoui, Johnny Amiran, Nicolas Lopez
  • Patent number: 11133289
    Abstract: A semiconductor package includes a first integrated circuit structure, a second integrated circuit structure, a plurality of conductive bumps, an encapsulating material, and a redistribution structure. The first integrated circuit structure includes an active surface having a plurality of contact pads, a back surface opposite to the active surface, and a plurality of through vias extending through the first integrated circuit structure and connecting the active surface and the back surface. The second integrated circuit structure is disposed on the back surface of the first integrated circuit structure. The conductive bumps are disposed between the first integrated circuit structure and the second integrated circuit structure, and electrically connecting the plurality of through vias and the second integrated circuit structure. The encapsulating material at least encapsulates the second integrated circuit structure.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: September 28, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Fu Tsai, Shih-Ting Lin, Szu-Wei Lu, Ying-Ching Shih