Abstract: A multilayer electronic component includes a body including a dielectric layer and internal electrodes alternately stacked with the dielectric layer interposed therebetween; and an external electrode disposed on the body and connected to the internal electrodes. One of the internal electrodes includes Ni, and a lattice constant of Ni included in the one of the internal electrodes satisfies a range of 3.53 ? to 3.72 ?.

Abstract: A base element for switching a magnetization state of a nanomagnet includes a heavy-metal nanostrip having a surface. The heavy-metal nanostrip includes at least a first layer including a heavy metal and a second layer which includes a different heavy-metal. A ferromagnetic nanomagnet is disposed adjacent to the surface. The ferromagnetic nanomagnet includes a shape having a long axis and a short axis, the ferromagnetic nanomagnet having both a perpendicular-to-the-plane anisotropy Hkz and an in-plane anisotropy Hkx and the ferromagnetic nanomagnet having a first magnetization equilibrium state and a second magnetization equilibrium state. The first magnetization equilibrium state or the second magnetization equilibrium state is settable by a flow of electrical charge through the heavy-metal nanostrip. A direction of the flow of electrical charge through the heavy-metal nanostrip includes an angle ? with respect to the short axis of the nanomagnet.

Abstract: One superconducting qubit device package disclosed herein includes a die having a first face and an opposing second face, and a package substrate having a first face and an opposing second face. The die includes a quantum device including a plurality of superconducting qubits and a plurality of resonators on the first face of the die, and a plurality of conductive pathways coupled between conductive contacts at the first face of the die and associated ones of the plurality of superconducting qubits or of the plurality of resonators. The second face of the package substrate also includes conductive contacts. The device package further includes first level interconnects disposed between the first face of the die and the second face of the package substrate, coupling the conductive contacts at the first face of the die with associated conductive contacts at the second face of the package substrate.

Abstract: Provided is a method that can manufacture a glass material having excellent homogeneity by containerless levitation. With a block (12) of glass raw material held levitated above a forming surface (10a) of a forming die (10) by jetting gas through a gas jet hole (10b) opening on the forming surface (10a), the block (12) of glass raw material is heated and melted by irradiation with laser beam, thus obtaining a molten glass, and the molten glass is then cooled to obtain a glass material. Control gas is jetted to the block (12) of glass raw material along a direction different from a direction of jetting of the levitation gas for use in levitating the block (12) of glass raw material or the molten glass.

Abstract: Techniques facilitating dynamic control of ZZ interactions for quantum computing devices. In one example, a quantum coupling device can comprise a biasing component that is operatively coupled to first and second qubits via respective first and second drive lines. The biasing component can facilitate dynamic control of ZZ interactions between the first and second qubits using off-resonant microwave signals applied via the respective first and second drive lines.

Abstract: This disclosure relates to fabrication of step edges to fabricate Josephson junctions. A method comprises forming a layer of resist over the surface. The layer of resist comprises openings to expose a selected area of the surface, thereby forming two walls in the layer of resist on a perimeter of the selected area. The resist and the substrate are exposed to an ion beam, thereby etching the resist and the exposed areas of the surface. While exposing the resist and the substrate to the ion beam, the substrate is gradually rotated about an axis normal to the surface to thereby form two step edges at the respective two walls. Further, superconducting material is deposited onto the substrate in a meandering shape to form a path that crosses the two step edges multiple times and to form a Josephson junction each time the path crosses the step edges.

Abstract: A hybrid template assisted selective epitaxy (HTASE) process is described comprising the steps of: depositing a template oxide layer on top of a silicon fin; opening a via in a selected portion of the template oxide to expose a portion of the encapsulated silicon fin and subsequently growing a nitride superconductor layer on top of the exposed silicon fin thereby forming a hybrid encapsulation of the silicon fin; performing a back-etch of the silicon fin to remove a portion (e.g., 5 nm-20 um) of the silicon fin; growing a layer formed from a group III/group V compound within an area where the silicon fin was removed via the back-etch; and if needed, removing the template oxide layer.

Abstract: This disclosure describes various examples of spintronic temperature sensors. The example temperature sensors may be discrete or used to adaptively control operation of a component such as an integrated circuit (IC). In one example, an electronic device comprises a spintronic component configured such that the conductance of the spintronic component is based on sensed temperature. In one example, circuitry coupled to the spintronic component is configured to generate an electrical signal indicative of the sensed temperature based on the conductance of the spintronic component.

Abstract: A surface emitting quantum cascade laser includes an active layer and a first semiconductor layer. The active layer includes a plurality of quantum well layers and is capable of emitting laser light by intersubband transition. The first surface includes an internal region and an outer peripheral region. Grating pitch of the first pits is m times grating pitch of the second pits. The outer peripheral region surrounds the internal region. A first planar shape of an opening end of the first pit is asymmetric with respect to a line passing through barycenter of the first planar shape and is parallel to at least one side of the first two-dimensional grating. A second planar shape of an opening end of the second pit is symmetric with respect to each of lines passing through barycenter of the second planar shape and is parallel to either side of the second two-dimensional grating.

Abstract: A surface emitting quantum cascade laser includes an active layer and a first semiconductor layer. The active layer includes a plurality of quantum well layers and is capable of emitting laser light by intersubband transition. The first surface includes an internal region and an outer peripheral region. Grating pitch of the first pits is m times grating pitch of the second pits. The outer peripheral region surrounds the internal region. A first planar shape of an opening end of the first pit is asymmetric with respect to a line passing through barycenter of the first planar shape and is parallel to at least one side of the first two-dimensional grating. A second planar shape of an opening end of the second pit is symmetric with respect to each of lines passing through barycenter of the second planar shape and is parallel to either side of the second two-dimensional grating.

Abstract: The present disclosure relates to a device and method for forming efficient quantum devices, in particular quantum devices that have not been contaminated in ex-situ processes. In particular the presently disclosed method can be applied for manufacturing of a Josephson junction which is an element in a tunable superconducting qubit.

Abstract: The invention relates to a method for producing a composite comprising a high-temperature superconductor (HTS) layer based on rare earth metal-barium-copper oxide on a substrate with defined biaxial texture, having the following steps: applying a first HTS coating solution to the substrate, drying the first HTS coating solution to produce a first film, pyrolyzing the first film to produce a first pyrolyzed sublayer, removing an interfacial layer on the upper side of the first pyrolyzed sublayer to produce a first pyrolyzed sublayer with reduced layer thickness, applying a second HTS coating solution to the first pyrolyzed sublayer with reduced layer thickness, drying the second HTS coating solution to produce a second film, pyrolyzing the second film to produce a second pyrolyzed sublayer, optionally forming one or more further pyrolyzed sublayers on the second pyrolyzed sublayer, and crystallizing the overall layer formed from the pyrolyzed sublayers to complete the HTS layer, wherein the removal of the inte

Abstract: Quantum circuits and associated methods use Repeat-Until-Success (RUS) circuits to perform approximate multiplication and approximate squaring of input values supplied as rotations encoded on ancilla qubits. So-called gearbox and programmable ancilla circuits are coupled to encode even or odd products of input values as a rotation of a target qubit. In other examples, quantum RUS circuits provide target qubit rotations that are associated with reciprocals using series expansion representations.

Abstract: A technique relates to reducing qubits required on a quantum computer. A Fermionic system is characterized in terms of a Hamiltonian. The Fermionic system includes Fermions and Fermionic modes with a total number of 2M Fermionic modes. The Hamiltonian has a parity symmetry encoded by spin up and spin down parity operators. Fermionic modes are sorted such that the first half of 2M modes corresponds to spin up and the second half of 2M modes corresponds to spin down. The Hamiltonian and the parity operators are transformed utilizing a Fermion to qubit mapping that transforms parity operators to a first single qubit Pauli operator on a qubit M and a second single qubit Pauli operator on a qubit 2M. The qubit M having been operated on by the first single qubit Pauli operator and the qubit 2M having been operated on by the second single qubit Pauli operator are removed.

Abstract: A method is provided of forming a superconductor device interconnect structure. The method includes forming a first high temperature dielectric layer overlying a substrate, forming a base electrode in the first high temperature dielectric layer with the base electrode having a top surface aligned with the top surface of the first high temperature dielectric layer, and depositing a second high temperature dielectric layer over the first high temperature dielectric layer and the base electrode. The method further comprises forming a first contact through the second dielectric layer to a first end of the base electrode, forming a Josephson junction (JJ) overlying and in contact with the first contact, and forming a second contact through the second dielectric layer to a second end of the base electrode.

Abstract: A method of making an MgO barrier layer for a TMR sensor, the method including depositing a first Mg layer in a first chamber, depositing a second Mg layer on the first Mg layer using a reactive oxide deposition process in the presence of oxygen in the first chamber or in a second chamber different than the first chamber, depositing a third Mg layer on the second MgO layer in either the first chamber, the second chamber, or a third chamber, and annealing the first layer, the second layer, and the third layer to form an MgO barrier layer.

Abstract: A simple, economical method of producing nanowire arrays is described. The method produces high density arrays having nanowires with diameters below 10 nm and does not require templating, catalysts, or surface pre/post-treatment. The disclosed methods and systems can be used, for example, for optoelectronic devices and photovoltaic cells, Li-ion batteries, chemical/bio sensors and transistors.

Abstract: Methods and systems transform a given single-qubit quantum circuit expressed in a first quantum-gate basis into a quantum-circuit expressed in a second, discrete, quantum-gate basis. The discrete quantum-gate basis comprises standard, implementable quantum gates. The given single-qubit quantum circuit is expressed as a normal representation. The normal representation is generally compressed, in length, with respect to equivalent non-normalized representations. The method and systems additionally can map normal representations to canonical-form representations, which are generally further compressed, in length, with respect to normal representations.

Abstract: Methods are provided of forming a Josephson junction (JJ) quantum bit (qubit). In one embodiment, the method comprises forming a JJ trilayer on a substrate. The JJ trilayer is comprised of a dielectric layer sandwiched between a bottom superconductor material layer and a top superconductor material layer. The method further comprises performing a thermal hardening process on the JJ trilayer to control diffusion of the dielectric layer into the bottom superconductor material layer and the top superconductor material layer, and etching openings in the JJ trilayer to form one or more JJ qubits.

Abstract: A transversely-coupled distributed feedback laser diode, which can be processed without overgrowth, is disclosed. The laser is made from an epitaxial heterostructure including a core layer located between two cladding layers, a cap layer, and at least one Al-rich layer. The lateral waveguide is formed by selective oxidation of the Al-rich layer. A surface corrugated grating is formed above the waveguide. The heteroepitaxial structure is designed so that the core layer is placed in close proximity to the top of the laser structure to provide a required overlap between the light and the grating. In order to avoid inadmissible optical losses, there is no metallization above the waveguide. Instead, the metal contacts are offset at some distance, so that the current has to spread in the cap layer before vertical injection into the core layer.

Abstract: A semiconductor device includes a gate trench across an active region of a semiconductor substrate, a gate structure filling the gate trench, and source/drain regions formed in the active region at respective sides of the gate structure. The gate structure includes a sequentially stacked gate electrode and insulating capping pattern, and a gate dielectric layer between the gate electrode and the active region. The gate electrode is located at a lower level than an upper surface of the active region and includes a barrier conductive pattern and a gate conductive pattern. The gate conductive pattern includes a first part having a first width and a second part having a second width greater than the first width. The barrier conductive pattern is interposed between the first part of the gate conductive pattern and the gate dielectric layer.

Abstract: A topological qubit wire hosts Majorana zero-energy modes and includes a superconductor, which may be an s-wave superconductor, and a quasi-1D nanowire, which may be a semi-conductor. The Majorana zero-energy modes are localized at ends of the quasi-1D nanowire, which may be sized and shaped to provide occupancy of a few transverse modes in a first direction and occupancy of a few transverse modes in a second direction. In some instances, the occupancy in the first direction may be greater than or equal to 3, and the occupancy in the second direction may be 1.

Abstract: A method for increasing the integration level of superconducting electronic circuits, comprising fabricating a series of planarized electrically conductive layers patterned into wiring, separated by planarized insulating layers, with vias communicating between the conductive layers. Contrary to the standard sequence of patterning from the bottom up, the pattern of vias in at least one insulating layer is formed prior to the pattern of wiring in the underlying conductive layer. This enables a reduction in the number of planarization steps, leading to a fabrication process which is faster and more reliable. In a preferred embodiment, the superconductor is niobium and the insulator is silicon dioxide. This method can provide 10 or more wiring layers in a complex integrated circuit, and is compatible with non-planarized circuits placed above the planarized wiring layers.

Abstract: Various techniques and apparatus permit fabrication of superconductive circuits. A niobium/aluminum oxide/niobium trilayer may be formed and individual Josephson Junctions (JJs) formed. A protective cap may protect a JJ during fabrication. A hybrid dielectric may be formed. A superconductive integrated circuit may be formed using a subtractive patterning and/or additive patterning. A superconducting metal layer may be deposited by electroplating and/or polished by chemical-mechanical planarization. The thickness of an inner layer dielectric may be controlled by a deposition process. A substrate may include a base of silicon and top layer including aluminum oxide. Depositing of superconducting metal layer may be stopped or paused to allow cooling before completion. Multiple layers may be aligned by patterning an alignment marker in a superconducting metal layer.

Abstract: A quantum computing device magnetic memory is described. The quantum computing device magnetic memory is coupled with a quantum processor including at least one quantum device corresponding to at least one qubit. The quantum computing device magnetic memory includes magnetic storage cells coupled with the quantum device(s) and bit lines coupled to the magnetic storage cells. Each of the magnetic storage cells includes at least one magnetic junction. The magnetic junction(s) include a reference layer, a nonmagnetic spacer layer, and a free layer. The nonmagnetic spacer layer is between the reference layer and the free layer. The magnetic junction(s) are configured to allow the free layer to be switched between stable magnetic states. The magnetic junction(s) are configured such that the free layer has a nonzero initial writing spin transfer torque in an absence of thermal fluctuations.

Abstract: An electronic component comprising a Josephson junction and a method for producing the same are proposed. The component comprises a substrate having at least one step edge in the surface thereof and a layer made of a high-temperature superconducting material disposed thereon, wherein this layer, at the step edge, has a grain boundary that forms the one or two weak links of the Josephson junction. On both sides of the step edge, the a and/or b crystal axes in the plane of the high-temperature superconducting layer are oriented perpendicularly to the grain boundary to within a deviation of no more than 10°, as a result of a texturing of the substrate and/or at least one buffer layer disposed between the substrate and the high-temperature superconducting layer. This can be technologically implemented, for example, by growing on the HTS layer by way of graphoepitaxy.

Abstract: Various techniques and apparatus permit fabrication of superconductive circuits and structures, for instance Josephson junctions, which may, for example be useful in quantum computers. For instance, a low magnetic flux noise trilayer structure may be fabricated having a dielectric structure or layer interposed between two elements or layers capable of superconducting. A superconducting via may directly overlie a Josephson junction. A structure, for instance a Josephson junction, may be carried on a planarized dielectric layer. A fin may be employed to remove heat from the structure. A via capable of superconducting may have a width that is less than about 1 micrometer. The structure may be coupled to a resistor, for example by vias and/or a strap contact connector.

Abstract: An improved PMA STT MTJ storage element, and a method for forming it, are described. By inserting a suitable oxide layer between the storage and cap layers, improved PMA properties are obtained, increasing the potential for a larger Eb/kT thermal factor as well as a larger MR. Another important advantage is better compatibility with high processing temperatures, potentially facilitating integration with CMOS.

Abstract: Various embodiments of light emitting devices with high quantum efficiencies are described herein. In one embodiment, a light emitting device includes a first contact, a second contact spaced apart from the first contact, and a first active region between the first and second contacts. The first active region is configured to produce a first emission via electroluminescence when a voltage is applied between the first and second contacts, and the first emission having a first center wavelength. The light emitting device also includes a second active region spaced apart from the first active region. The second active region is configured to absorb at least a portion of the first emission and produce a second emission via photoluminescence, and the second emission having a second center wavelength longer than the first center wavelength.

Abstract: A mechanism is provided for a spin torque transfer random access memory device. A tunnel barrier is disposed on a reference layer, and a free layer is disposed on the tunnel barrier. The free layer includes an iron layer as a top part of the free layer. A metal oxide layer is disposed on the iron layer, and a cap layer is disposed on the metal oxide layer.

Abstract: A nitride semiconductor structure and a semiconductor light emitting device including the same are revealed. The nitride semiconductor structure includes a light emitting layer disposed between a n-type semiconductor layer and a p-type semiconductor layer, and a hole supply layer disposed between the light emitting layer and the p-type semiconductor layer. The hole supply layer is made from material InxGa1-xN (0<x<1) and is doped with a Group IV-A element at a concentration ranging from 1017 to 1020 cm?3. By being doped with the Group IV-A element, the concentration of holes is increased and inactivation caused by Mg—H bonds is reduced. Thus Mg is activated as acceptors and the light emitting efficiency is further increased.

Abstract: A spin-current switched magnetic memory element includes a plurality of magnetic layers, at least one of the plurality of magnetic layers having a perpendicular magnetic anisotropy component and including a current-switchable magnetic moment, and at least one barrier layer formed adjacent to the plurality of magnetic layers. The plurality of magnetic layers includes at least one composite layer.

Abstract: A integrated circuit and methods for fabricating the circuit are provided. The circuit integrates at least one circuit element formed from a material that is superconducting at temperatures less than one hundred milliKelvin and at least one resistor connected to the circuit element. The resistor is formed from an alloy of transition metals that is resistive at temperatures less than one hundred milliKelvin.

Abstract: A qubit system includes a substrate layer, a qubit circuit suspended above the substrate layer and fine structure disposed between the qubit circuit and the substrate layer.

Abstract: A method for fabricating a chip surface base includes preparing a first substrate, preparing a plurality of vias in the first substrate, depositing metal fillings into the plurality of vias, preparing a second substrate, bonding the first and second substrates and exposing the metal fillings. A method for fabricating a chip surface base includes preparing a first and second substrate, depositing a metal on at least one of the first and second substrates, bonding the first and second substrates, preparing a plurality of vias in the first substrate, depositing metal fillings into the plurality of vias and exposing the metal fillings. A chip surface base device includes a first substrate, a second substrate, a metal layer disposed between the first and second substrates and a plurality vias disposed on the first substrate.

Abstract: A coplanar waveguide device includes a coplanar waveguide structure disposed on a substrate, at least one qubit coupled to the coplanar waveguide structure and an add-on chip having a metallized trench, and disposed over the substrate.

Abstract: Superconductive interconnection structures providing continuous, uninterrupted superconducting signal paths between a superconducting chip and a superconducting chip carrier are described. The superconductive interconnection structures employ superconducting solder bumps and pillars of Under Bump Metal (“UBM”). The superconductive interconnection structures are employed in a two-stage solder bumping process in which the superconducting chip is first bonded to a testing module for screening and then bonded to a chip packaging module for operation. Either the testing module or the chip packaging module, or both, may include a multi-chip module for carrying multiple superconducting chips simultaneously.

Abstract: Computing bus devices that enable quantum information to be coherently transferred between topological and conventional qubits are disclosed. A concrete realization of such a topological quantum bus acting between a topological qubit in a Majorana wire network and a conventional semiconductor double quantum dot qubit is described. The disclosed device measures the joint (fermion) parity of the two different qubits by using the Aharonov-Casher effect in conjunction with an ancillary superconducting flux qubit that facilitates the measurement. Such a parity measurement, together with the ability to apply Hadamard gates to the two qubits, allows for the production of states in which the topological and conventional qubits are maximally entangled, and for teleporting quantum states between the topological and conventional quantum systems.

Abstract: A STT-RAM MTJ that minimizes spin-transfer magnetization switching current (Jc) is disclosed. The MTJ has a MgO tunnel barrier layer formed with a natural oxidation process to achieve a low RA (10 ohm-um2) and a Fe or Fe/CoFeB/Fe free layer which provides a lower intrinsic damping constant than a CoFeB free layer. A Fe, FeB, or Fe/CoFeB/Fe free layer when formed with a MgO tunnel barrier (radical oxidation process) and a CoFeB AP1 pinned layer in a MRAM MTJ stack annealed at 360° C. provides a high dR/R (TMR)>100% and a substantial improvement in read margin with a TMR/Rp_cov=20. High speed measurement of 100 nm×200 nm oval STT-RAM MTJs has shown a Jc0 for switching a Fe free layer is one half that for switching an amorphous Co40Fe40B20 free layer. A Fe/CoFeB/Fe free layer configuration allows the Hc value to be increased for STT-RAM applications.

Abstract: Several embodiments of a novel technique for limiting transmission of fault current are disclosed. Current power distribution systems typically have an impedance, or reactor, on the output of the network equipment to limit current in the case of a fault condition. A low resistance switch, which changes its resistance in the presence of high current, is connected in parallel with this reactor. Thus, in normal operation, the current from the power generator bypasses the reactor, thereby minimizing power loss. However, in the presence of a fault, the resistance of the switch increases, forcing the current to pass through the reactor, thereby limiting the fault current.

Abstract: Compactly-integrated electronic structures and associated systems and methods are provided. Certain embodiments relate to the ability to integrate nanowire-based detectors with optical components.

Abstract: A superconducting nanowire single photon detector (SN-SPD) microelectronic circuit is described which has higher quantum efficiency and signal-to-noise than any SN-SPD's known in the art. The material and configuration of the microelectronic circuit eliminates the polarization dependence and shows improved signal-to-noise over SN-SPD microelectronic circuits known in the art. The higher efficiency, polarization independence, and high signal-to-noise is achieved by vertically stacking two tungsten-silicide (TS) SN-SPDs and electrically connecting them in parallel. This structure forms a multilayer superconducting nanowire avalanche photo-detector (SNAP). A single photon detection device employing the multilayer (SNAP) microelectronic circuit demonstrates a peak system detection efficiency of 87.7% and a polarization dependence of less than 2%. This represents nearly an order of magnitude improvement in both system detection efficiency and reduction of polarization dependence compared to conventional SNSPDs.

Abstract: An improved microfabrication technique for Josephson junctions in superconducting integrated circuits, based on the use of a double-layer lithographic mask for partial anodization of the side-walls and base electrode of the junctions. The top layer of the mask is a resist material, and the bottom layer is a dielectric material chosen so to maximize adhesion between the resist and the underlying superconducting layer, be etch-compatible with the underlying superconducting layer, and be insoluble in the resist and anodization processing chemistries. The superconductor is preferably niobium, under a silicon dioxide layer, with a conventional photoresist or electron-beam resist as the top layer. This combination results in a substantial increase in the fabrication yield of high-density superconducting integrated circuits, increase in junction uniformity and reduction in defect density. A dry etch more compatible with microlithography may be employed.

Abstract: In accordance with aspects of the invention, a method of forming a metal-insulator-metal stack is provided. The method includes forming a first conducting layer, forming a resistivity-switching carbon-based material above the first conducting layer, and forming a second conducting layer above the carbon-based material, wherein the carbon-based material has a thickness of not more than ten atomic layers. Other aspects are also described.

Abstract: This invention concerns an electronic device for the control and readout of the electron or hole spin of a single dopant in silicon. The device comprises a silicon substrate in which there are one or more ohmic contact regions. An insulating region on top of the substrate. First and second barrier gates spaced apart to isolate a small region of charges to form an island of a Single Electron Transistor (SET). A third gate over-lying both the first and second barrier gates, but insulated from them, the third gate being able to generate a gate-induced charge layer (GICL) in the beneath it. A fourth gate in close proximity to a single dopant atom, the dopant atom being encapsulated in the substrate outside the region of the GICL but close enough to allow spin-dependent charge tunnelling between the dopant atom and the SET island under the control of gate potentials, mainly the fourth gate.

Abstract: An implementation of a single qubit phase gate for use in a quantum information processing scheme based on the ?=5/2 fractional quantum Hall (FQH) state is disclosed. Using sack geometry, a qubit consisting of two ?-quasiparticles, which may be isolated on respective antidots, may be separated by a constriction from the bulk of a two-dimensional electron gas in the ?=5/2 FQH state. An edge quasiparticle may induce a phase gate on the qubit. The number of quasiparticles that are allowed to traverse the edge path defines which gate is induced. For example, if a certain number of quasiparticles are allowed to traverse the path, then a ?/8 gate may be effected.

Abstract: Methods are provided of forming a Josephson junction (JJ) quantum bit (qubit). In one embodiment, the method comprises forming a JJ trilayer on a substrate. The JJ trilayer is comprised of a dielectric layer sandwiched between a bottom superconductor material layer and a top superconductor material layer. The method further comprises performing a thermal hardening process on the JJ trilayer to control diffusion of the dielectric layer into the bottom superconductor material layer and the top superconductor material layer, and etching openings in the JJ trilayer to form one or more JJ qubits.

Abstract: A quantum bit computing architecture includes a plurality of single spin memory donor atoms embedded in a semiconductor layer, a plurality of quantum dots arranged with the semiconductor layer and aligned with the donor atoms, wherein a first voltage applied across at least one pair of the aligned quantum dot and donor atom controls a donor-quantum dot coupling. A method of performing quantum computing in a scalable architecture quantum computing apparatus includes arranging a pattern of single spin memory donor atoms in a semiconductor layer, forming a plurality of quantum dots arranged with the semiconductor layer and aligned with the donor atoms, applying a first voltage across at least one aligned pair of a quantum dot and donor atom to control a donor-quantum dot coupling, and applying a second voltage between one or more quantum dots to control a Heisenberg exchange J coupling between quantum dots and to cause transport of a single spin polarized electron between quantum dots.

Abstract: An improved microfabrication technique for Josephson junctions in superconducting integrated circuits, based on the use of a double-layer lithographic mask for partial anodization of the side-walls and base electrode of the junctions. The top layer of the mask is a resist material, and the bottom layer is a dielectric material chosen so to maximize adhesion between the resist and the underlying superconducting layer, be etch-compatible with the underlying superconducting layer, and be insoluble in the resist and anodization processing chemistries. The superconductor is preferably niobium, under a silicon dioxide layer, with a conventional photoresist or electron-beam resist as the top layer. This combination results in a substantial increase in the fabrication yield of high-density superconducting integrated circuits, increase in junction uniformity and reduction in defect density. A dry etch more compatible with microlithography may be employed.

Abstract: Disclosed is to supply processing liquid having a predetermined flow rate and concentration to substrate processing units of a substrate processing apparatus with high accuracy. The substrate processing apparatus, which processes substrates in the substrate processing units using the processing liquid supplied from a processing liquid supply part, sequentially carries the substrates to the respective substrate processing units, and controls the processing start time such that if the flow rate of the processing liquid used in one of the substrate processing units is less than the control flow rate that is controllable at the processing liquid supply part, the substrates are carried to the plurality of substrate processing units until a flow rate of the processing liquid reaches the control flow rate that is controllable at the processing liquid supply part and then the processing liquid is used simultaneously in the plurality of the substrate processing units.