Having Magnetic Or Ferroelectric Component Patents (Class 438/3)
  • Patent number: 11502248
    Abstract: A ferroelectric component includes a first electrode, a tunnel barrier layer disposed on the first electrode to include a ferroelectric material, a tunneling control layer disposed on the tunnel barrier layer to control a tunneling width of electric charges passing through the tunnel barrier layer, and a second electrode disposed on the tunneling control layer.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: November 15, 2022
    Assignee: SK hynix Inc.
    Inventors: Jae Gil Lee, Hyangkeun Yoo, Jae Hyun Han
  • Patent number: 11502247
    Abstract: A method of manufacturing a magnetoresistive device may comprise forming a first magnetic region, an intermediate region, and a second magnetic region of a magnetoresistive stack above a via; removing at least a portion of the second magnetic region using a first etch; removing at least a portion of the intermediate region and at least a portion of the first magnetic region using a second etch; removing at least a portion of material redeposited on the magnetoresistive stack using a third etch; and rendering at least a portion of the redeposited material remaining on the magnetoresistive stack electrically non-conductive.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: November 15, 2022
    Assignee: Everspin Technologies, Inc.
    Inventors: Sanjeev Aggarwal, Shimon, Kerry Joseph Nagel
  • Patent number: 11482668
    Abstract: In some embodiments, the present disclosure relates to method of forming an integrated chip. The method includes forming a bottom electrode structure over one or more interconnect layers disposed within one or more stacked inter-level dielectric (ILD) layers over a substrate. The bottom electrode structure has an upper surface having a noble metal. A diffusion barrier film is formed over the bottom electrode structure. A data storage film is formed onto the diffusion barrier film, and a top electrode structure is over the data storage film. The top electrode structure, the data storage film, the diffusion barrier film, and the bottom electrode structure are patterned to define a memory device.
    Type: Grant
    Filed: January 6, 2021
    Date of Patent: October 25, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hai-Dang Trinh, Chii-Ming Wu, Hsing-Lien Lin, Fa-Shen Jiang
  • Patent number: 11475932
    Abstract: A storage element includes a layer structure including a storage layer having a direction of magnetization which changes according to information, a magnetization fixed layer having a fixed direction of magnetization, and an intermediate layer disposed therebetween, which intermediate layer contains a nonmagnetic material. The magnetization fixed layer has at least two ferromagnetic layers having a direction of magnetization tilted from a direction perpendicular to a film surface, which are laminated and magnetically coupled interposing a coupling layer therebetween. This configuration may effectively prevent divergence of magnetization reversal time due to directions of magnetization of the storage layer and the magnetization fixed layer being substantially parallel or antiparallel, reduce write errors, and enable writing operation in a short time.
    Type: Grant
    Filed: November 5, 2020
    Date of Patent: October 18, 2022
    Assignee: Sony Group Corporation
    Inventors: Yutaka Higo, Masanori Hosomi, Hiroyuki Ohmori, Kazuhiro Bessho, Tetsuya Asayama, Kazutaka Yamane, Hiroyuki Uchida
  • Patent number: 11456410
    Abstract: A magnetic memory device comprises a cylindrical core and a plurality of layers surrounding the core. The plurality of layers include a metallic buffer layer, a ferromagnetic storage layer, a barrier layer, and a ferromagnetic reference layer. The cylindrical core, the metallic buffer layer, the ferromagnetic storage layer, the barrier layer, and the ferromagnetic reference layer collectively form a magnetic tunnel junction. A magnetization of the ferromagnetic layer storage parallels an interface between the metallic buffer layer and ferromagnetic storage layer.
    Type: Grant
    Filed: June 4, 2020
    Date of Patent: September 27, 2022
    Assignee: Integrated Silicon Solution, (Cayman) Inc.
    Inventors: Marcin Gajek, Michail Tzoufras
  • Patent number: 11444162
    Abstract: A method includes performing a first etching process on a backside of a substrate to expose a dummy contact structure, performing a first deposition process to deposit a first dielectric layer around the dummy contract structure, performing a second deposition process to deposit an oxide layer on the first dielectric layer, removing the dummy contract structure to form a trench, depositing a sacrificial layer on sidewalls of the trench, depositing a second dielectric layer on the sacrificial layer, filling the trench with a conductive material, and removing the sacrificial layer to form an air spacer between the first dielectric layer and the second dielectric layer.
    Type: Grant
    Filed: January 27, 2021
    Date of Patent: September 13, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Ming Lee, Wei-Yang Lee
  • Patent number: 11443879
    Abstract: An integrated magnetic device has a magnetic core which includes layers of the magnetic material located in a trench in a dielectric layer. The magnetic material layers are flat and parallel to a bottom of the trench, and do not extend upward along sides of the trench. The integrated magnetic device is formed by forming layers of the magnetic material over the dielectric layer and extending into the trench. A protective layer is formed over the magnetic material layers. The magnetic material layers are removed from over the dielectric layer, leaving the magnetic material layers and a portion of the protective layer in the trench. The magnetic material layers along sides of the trench are subsequently removed. The magnetic material layers along the bottom of the trench provide the magnetic core.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: September 13, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Fuchao Wang, Yousong Zhang, Neal Thomas Murphy, Brian Zinn, Jonathan P. Davis
  • Patent number: 11430956
    Abstract: The present disclosure relates to a resistive random access memory (RRAM) device architecture, that includes a thin single layer of a conductive etch-stop layer between a lower metal interconnect and a bottom electrode of an RRAM cell. The conductive etch-stop layer provides simplicity in structure and the etch-selectivity of this layer provides protection to the underlying layers. The conductive etch stop layer can be etched using a dry or wet etch to land on the lower metal interconnect. In instances where the lower metal interconnect is copper, etching the conductive etch stop layer to expose the copper does not produce as much non-volatile copper etching by-products as in traditional methods. Compared to traditional methods, some embodiments of the disclosed techniques reduce the number of mask step and also reduce chemical mechanical polishing during the formation of the bottom electrode.
    Type: Grant
    Filed: September 21, 2019
    Date of Patent: August 30, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming Chyi Liu, Yuan-Tai Tseng, Chern-Yow Hsu, Shih-Chang Liu, Chia-Shiung Tsai
  • Patent number: 11424318
    Abstract: A method for fabricating a capacitor device includes providing a substrate; forming a first-layer electrode on the substrate; and forming a conductive layer on the first-layer electrode. The roughness of the first-layer electrode is a first roughness, the roughness of the conductive layer is a second roughness, and the second roughness is smaller than the first roughness. The method further includes forming a dielectric layer on the conductive layer; and forming a second-layer electrode on the dielectric layer. According to the disclosed method and capacitor device, by forming the conductive layer on the first-layer electrode, the roughness of the bottom electrode of the capacitor device is reduced, which effectively reduces the presence of protrusions on the surface of the bottom electrode. Therefore, the breakdown electric voltage of the capacitor device may be improved, and leakage current may be avoided. As such, the reliability of the capacitor device may be improved.
    Type: Grant
    Filed: August 12, 2019
    Date of Patent: August 23, 2022
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Lianfeng Hu, Youcun Hu, Ming Yang, Duohui Bei, Baibing Ni
  • Patent number: 11417517
    Abstract: A method of forming a high-K dielectric cap layer on a semiconductor structure formed on a substrate includes depositing the high-K dielectric cap layer on the semiconductor structure, depositing a sacrificial silicon cap layer on the high-K dielectric cap layer, performing a post cap anneal process to harden and densify the as-deposited high-K dielectric cap layer, and removing the sacrificial silicon cap layer.
    Type: Grant
    Filed: November 18, 2020
    Date of Patent: August 16, 2022
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Srinivas Gandikota, Yixiong Yang, Jacqueline Samantha Wrench, Yong Yang, Steven C. H. Hung
  • Patent number: 11417832
    Abstract: The present disclosure provides a semiconductor structure, including a substrate, including a first region and a second region adjacent to the first region, a magnetic tunnel junction (MTJ) over the first region, a spacer on a sidewall of the MTJ, a hard mask over the MTJ, a first dielectric layer laterally surrounding the spacer and the hard mask, a top electrode over the hard mask, and an etch stop stack laterally surrounding the top electrode.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: August 16, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yu-Feng Yin, Tai-Yen Peng, An-Shen Chang, Han-Ting Tsai, Qiang Fu, Chung-Te Lin
  • Patent number: 11411116
    Abstract: The disclosed technology generally relates to ferroelectric materials and semiconductor devices, and more particularly to semiconductor memory devices incorporating doped polar materials. In one aspect, a semiconductor device comprises a capacitor which in turn comprises a polar layer comprising a base polar material doped with a dopant. The base polar material includes one or more metal elements and one or both of oxygen or nitrogen. The dopant comprises a metal element that is different from the one or more metal elements and is present at a concentration such that a ferroelectric switching voltage of the capacitor is different from that of the capacitor having the base polar material without being doped with the dopant by more than about 100 mV. The capacitor stack additionally comprises first and second crystalline conductive oxide electrodes on opposing sides of the polar layer.
    Type: Grant
    Filed: July 2, 2021
    Date of Patent: August 9, 2022
    Assignee: Kepler Computing Inc.
    Inventors: Ramesh Ramamoorthy, Sasikanth Manipatruni, Gaurav Thareja
  • Patent number: 11398263
    Abstract: A semiconductor structure includes an electrode, a ferroelectric material adjacent the electrode, the ferroelectric material comprising an oxide of at least one of hafnium and zirconium, the ferroelectric material doped with bismuth, and another electrode adjacent the ferroelectric material on an opposite side thereof from the first electrode. Related semiconductor structures, memory cells, semiconductor devices, electronic systems, and related methods are disclosed.
    Type: Grant
    Filed: July 15, 2020
    Date of Patent: July 26, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Albert Liao, Wayne I. Kinney, Yi Fang Lee, Manzar Siddik
  • Patent number: 11387406
    Abstract: In an embodiment, a method includes: forming a first inter-metal dielectric (IMD) layer over a semiconductor substrate; forming a bottom electrode layer over the first IMD layer; forming a magnetic tunnel junction (MTJ) film stack over the bottom electrode layer; forming a first top electrode layer over the MTJ film stack; forming a protective mask covering a first region of the first top electrode layer, a second region of the first top electrode layer being uncovered by the protective mask; forming a second top electrode layer over the protective mask and the first top electrode layer; and patterning the second top electrode layer, the first top electrode layer, the MTJ film stack, the bottom electrode layer, and the first IMD layer with an ion beam etching (IBE) process to form a MRAM cell, where the protective mask is etched during the IBE process.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: July 12, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tai-Yen Peng, Hui-Hsien Wei, Han-Ting Lin, Sin-Yi Yang, Yu-Shu Chen, An-Shen Chang, Qiang Fu, Chen-Jung Wang
  • Patent number: 11380472
    Abstract: Various embodiments include, for example, a magnetic-dielectric film-based inductor that can be embedded in an electronic package for use as an integrated voltage-regulator, multiple conductive regions to provide electrical interconnects to the magnetic-dielectric-based inductor from other devices, multiple conductive pillars that are electrically coupled to and formed over at least some of the conductive regions, and a magnetic-dielectric layer formed over at least some of conductive regions and conductive pillars. The magnetic-dielectric layer is formed by a multi-layer formation technique having multiple dielectric-material layers and multiple magnetic-material layers. Each of the magnetic-material layers is interspersed with at least one of the dielectric-material layers. Other devices, apparatuses, and methods are described.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: July 5, 2022
    Assignee: Intel Corporation
    Inventors: Srinivas V. Pietambaram, Kristof Darmawikarta, Rahul N. Manepalli
  • Patent number: 11374165
    Abstract: A process sequence is provided to provide an ultra-smooth (0.2 nm or less) bottom electrode surface for depositing magnetic tunnel junctions thereon. In one embodiment, the sequence includes forming a bottom electrode pad through bulk layer deposition followed by patterning and etching. Oxide is then deposited over the formed bottom electrode pads and polished back to expose the bottom electrode pads. A bottom electrode buff layer is then deposited thereover following a pre-clean operation. The bottom electrode buff layer is then exposed to a chemical mechanical polishing process to improve surface roughness. An magnetic tunnel junction deposition is then performed over the bottom electrode buff layer.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: June 28, 2022
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Lin Xue, Sajjad Amin Hassan, Mahendra Pakala, Jaesoo Ahn
  • Patent number: 11342343
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a source/drain structure, a metal gate structure, a ferroelectric layer, a spacer and a metal layer. The source/drain structure is disposed over the substrate. The metal gate structure is disposed over the substrate and between the source/drain structure. The ferroelectric layer is disposed over the metal gate structure and the source/drain structure. The spacer is disposed over the ferroelectric layer. The metal layer is disposed over the ferroelectric layer and surrounded by the spacer. A method for manufacturing a semiconductor structure is also provided.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: May 24, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chih-Yu Chang, Sai-Hooi Yeong, Yu-Ming Lin, Chih-Hao Wang
  • Patent number: 11329050
    Abstract: A semiconductor memory device includes a substrate having a memory cell region where a plurality of active regions are defined; a word line having a stack structure of a lower word line layer and an upper word line layer and extending over the plurality of active regions in a first horizontal direction, and a buried insulation layer on the word line; a bit line structure arranged on the plurality of active regions, extending in a second horizontal direction perpendicular to the first horizontal direction, and having a bit line; and a word line contact plug electrically connected to the lower word line layer by penetrating the buried insulation layer and the upper word line layer and having a plug extension in an upper portion of the word line contact plug, the plug extension having a greater horizontal width than a lower portion of the word line contact plug.
    Type: Grant
    Filed: August 14, 2020
    Date of Patent: May 10, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyejin Seong, Dongsoo Woo, Wonchul Lee
  • Patent number: 11329216
    Abstract: A semiconductor device includes a semiconductor substrate, a bottom electrode, a magnetic tunneling junction (MTJ), a top electrode, and a residue. The bottom electrode is disposed over the semiconductor substrate. The MTJ is disposed over the bottom electrode. The top electrode is disposed over the MTJ layer. Sidewalls of the bottom electrode, the MTJ, and the top electrode are vertically aligned with each other. The residue of the MTJ is located on the sidewall of the bottom electrode.
    Type: Grant
    Filed: April 13, 2020
    Date of Patent: May 10, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsi-Wen Tien, Wei-Hao Liao, Pin-Ren Dai, Chih-Wei Lu, Chung-Ju Lee
  • Patent number: 11329218
    Abstract: A metal hard mask layer is deposited on a MTJ stack on a substrate. A hybrid hard mask is formed on the metal hard mask layer, comprising a plurality of spin-on carbon layers alternating with a plurality of spin-on silicon layers wherein a topmost layer of the hybrid hard mask is a silicon layer. A photo resist pattern is formed on the hybrid hard mask. First, the topmost silicon layer of the hybrid hard mask is etched where is it not covered by the photo resist pattern using a first etching chemistry. Second, the hybrid hard mask is etched where it is not covered by the photo resist pattern wherein the photoresist pattern is etched away using a second etch chemistry. Thereafter, the metal hard mask and MTJ stack are etched where they are not covered by the hybrid hard mask to form a MTJ device and overlying top electrode.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: May 10, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi Yang, Yu-Jen Wang
  • Patent number: 11296146
    Abstract: According to an embodiment, a magnetoresistive memory device includes a first conductor with a first surface. A first structure on the first surface of the first conductor includes a first ferromagnetic layer. An insulating layer is on the first structure. A second structure on the insulating layer includes a second ferromagnetic layer. A second conductor is in contact with the first surface of the first conductor and a side surface of the first structure. A first insulator on the second conductor covers a side surface of the insulating layer, and is in contact with the side surface of the first structure and a side surface of the second structure. A third conductor on the first insulator is in contact with the side surface of the second structure.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: April 5, 2022
    Assignee: KIOXIA CORPORATION
    Inventor: Shuichi Tsubata
  • Patent number: 11289607
    Abstract: The disclosed technology generally relates to ferroelectric materials and semiconductor devices, and more particularly to semiconductor memory devices incorporating doped polar materials. In one aspect, a semiconductor device comprises a capacitor, which in turn comprises a polar layer comprising a crystalline base polar material doped with a dopant. The base polar material includes one or more metal elements and one or both of oxygen or nitrogen, wherein the dopant comprises a metal element that is different from the one or more metal elements and is present at a concentration such that a ferroelectric switching voltage of the capacitor is different from that of the capacitor having the base polar material without being doped with the dopant by more than about 100 mV.
    Type: Grant
    Filed: June 24, 2021
    Date of Patent: March 29, 2022
    Assignee: Kepler Computing Inc.
    Inventors: Ramesh Ramamoorthy, Sasikanth Manipatruni, Gaurav Thareja
  • Patent number: 11289603
    Abstract: A semiconductor device and method of manufacture are provided which utilizes metallic seeds to help crystallize a ferroelectric layer. In an embodiment a metal layer and a ferroelectric layer are formed adjacent to each other and then the metal layer is diffused into the ferroelectric layer. Once in place, a crystallization process is performed which utilizes the material of the metal layer as seed crystals.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: March 29, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bo-Feng Young, Sai-Hooi Yeong, Chi On Chui
  • Patent number: 11264566
    Abstract: A perpendicular magnetic tunnel junction is disclosed wherein a metal insertion (MIS) layer is formed within a free layer (FL), a partially oxidized Hk enhancing layer is on the FL, and a nitride capping layer having a buffer layer/nitride layer (NL) is on the Hk enhancing layer to provide an improved coercivity (Hc)/switching current (Jc) ratio for spintronic applications. Magnetoresistive ratio is maintained above 100%, resistance×area (RA) product is below 5 ohm/?m2, and thermal stability to 400° C. is realized. The FL comprises two or more sub-layers, and the MIS layer may be formed within at least one sub-layer or between sub-layers. The buffer layer is used to prevent oxygen diffusion to the NL, and nitrogen diffusion from the NL to the FL. FL thickness is from 11 Angstroms to 25 Angstroms while MIS layer thickness is preferably from 0.5 Angstroms to 4 Angstroms.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: March 1, 2022
    Assignee: Headway Technologies, Inc.
    Inventors: Santiago Serrano Guisan, Luc Thomas, Jodi Mari Iwata, Guenole Jan, Ru-Ying Tong
  • Patent number: 11258006
    Abstract: Provided are a magnetic memory element in which an improvement in properties, such as an improvement in coercive properties or a reduction in a leak current, can be attained, a method for producing the same, and a magnetic memory. The magnetic memory element, includes: a columnar stack ST in which a reference layer FX having a fixed magnetization direction, a barrier layer TL including a non-magnetic body, and a recording layer FR having a reversible magnetization direction are stacked in this order; and an insulating film which contains nitrogen and is provided to cover a lateral surface of the columnar stack, in which in one or both of the recording layer and the barrier layer, a nitrogen concentration is 7×1030 atoms/m2 or more in a position of 2 nm inside from an outer circumferential end of the columnar stack.
    Type: Grant
    Filed: August 18, 2020
    Date of Patent: February 22, 2022
    Assignee: TOHOKU UNIVERSITY
    Inventors: Tetsuo Endoh, Masaaki Niwa, Hiroaki Honjo, Hideo Sato, Shoji Ikeda, Toshinari Watanabe
  • Patent number: 11251360
    Abstract: A magnetic tunnel junction (MTJ) stack structure having an enhanced write performance and thermal stability (i.e., retention) is provided which can be used as an element/component of a spin-transfer torque (STT) MRAM device. The improved write performance, particularly the write error rate slope as a function of write voltage (Vfrc) which is essential in defining the overdrive voltage needed to successfully write a bit at low write error floors, is provided by a MTJ stack structure in which a zirconium (Zr) cap layer is inserted between a MTJ capping layer and an etch stop layer.
    Type: Grant
    Filed: February 6, 2020
    Date of Patent: February 15, 2022
    Assignee: International Business Machines Corporation
    Inventor: Matthias Georg Gottwald
  • Patent number: 11250899
    Abstract: A 1S-1T ferroelectric memory cell is provided that include a transistor and a two-terminal selector device. The transistor exhibits a low conductive state and a high conductive state (channel resistance), depending on drive voltage. The two-terminal selector device exhibits one of an ON-state and an OFF-state depending upon whether the transistor is in its low conductive state or its high conductive state. The transistor may be, for instance, a ferroelectric gate vertical transistor. Modulation of a polarization state of ferroelectric material of the vertical transistor may be utilized to switch the state of the selector device. The memory cell may thus selectively be operated in one of an ON-state and an OFF-state depending upon whether the selector device is in its ON-state or OFF-state.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: February 15, 2022
    Assignee: Intel Corporation
    Inventors: Abhishek A. Sharma, Brian S. Doyle, Ravi Pillarisetty, Prashant Majhi, Elijah V. Karpov
  • Patent number: 11245069
    Abstract: Embodiments of the disclosure provide methods and apparatus for fabricating magnetic tunnel junction (MTJ) structures on a substrate in for spin-transfer-torque magnetoresistive random access memory (STT-MRAM) applications. In one embodiment, the method includes patterning a film stack having a tunneling barrier layer disposed between a magnetic reference layer and a magnetic storage layer disposed on a substrate to remove a portion of the film stack from the substrate until an upper surface of the substrate is exposed, forming a sidewall passivation layer on sidewalls of the patterned film stack and subsequently performing a thermal annealing process to the film stack.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: February 8, 2022
    Assignee: Applied Materials, Inc.
    Inventors: Lin Xue, Jaesoo Ahn, Mahendra Pakala, Chi Hong Ching, Rongjun Wang
  • Patent number: 11239184
    Abstract: The present disclosure provides a package substrate and method of manufacturing the same. The package substrate includes a substrate, an electronic component and a conductive trace. The electronic component is disposed in the substrate, and the electronic component includes a magnetic layer and a conductive wire. The conductive wire includes a first section embedded in the magnetic layer, and a second section connected to the first section and thinner than the first section. A first upper surface of the first section is covered by the magnetic layer, a second upper surface of the second section is lower than the first upper surface, and the magnetic layer includes a first recess disposed in the upper surface and exposing the second upper surface of the second section. The first conductive trace is in the first recess and electrically connected to the second upper surface of the second section of the conductive wire.
    Type: Grant
    Filed: June 11, 2020
    Date of Patent: February 1, 2022
    Assignee: ADVANCED SEMICONDUTOR ENGINEERING, INC.
    Inventors: Wu Chou Hsu, Chih-Cheng Lee, Min-Yao Chen, Hsing Kuo Tien
  • Patent number: 11239413
    Abstract: A spin-orbit-torque (SOT) magnetic device includes a bottom metal layer, a first magnetic layer, as a magnetic free layer, disposed over the bottom metal layer, a spacer layer disposed over the first magnetic layer, and a second magnetic layer disposed over the spacer layer. The first magnetic layer includes a lower magnetic layer, a middle layer made of non-magnetic layer and an upper magnetic layer.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: February 1, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shy-Jay Lin, Mingyuan Song
  • Patent number: 11239412
    Abstract: A semiconductor structure includes an electrode element with an upper surface. The upper surface includes at least one convex curved portion.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: February 1, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Chun Chen, Ya-Sheng Feng, Chiu-Jung Chiu
  • Patent number: 11217288
    Abstract: According to one embodiment, a magnetic device includes: a first magnetic material provided above a substrate; a second magnetic material provided between the substrate and the first magnetic material; a nonmagnetic material provided between the first magnetic material and the second magnetic material; a first layer provided between the substrate and the second magnetic material and including an amorphous layer; and a second layer provided between the amorphous layer and the second magnetic material and including a crystal layer.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: January 4, 2022
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Kazuya Sawada, Young Min Eeh, Tadaaki Oikawa, Kenichi Yoshino, Eiji Kitagawa, Taiga Isoda
  • Patent number: 11217745
    Abstract: According to one embodiment, a method for manufacturing a magnetoresistive memory device includes forming a first layer stack on a substrate. A second layer stack including a first ferromagnet is formed on the first layer stack. A mask including a first portion and an opening is formed above the second layer stack. The second layer stack is etched with an ion beam that travels through the opening. The first layer stack is etched by reactive ion etching through the opening.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: January 4, 2022
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yuichi Ito, Kouji Matsuo
  • Patent number: 11211522
    Abstract: A method of transferring semiconductor devices from a first substrate to a second substrate, including providing the semiconductor devices which are between the first substrate and the second substrate. The semiconductor devices include a first semiconductor device and a second semiconductor device, and the first semiconductor device and the second semiconductor device have a first gap between thereof. The first semiconductor device and the second semiconductor device are moved from the first substrate by a picking unit. The picking unit, the first semiconductor device, and the second semiconductor device are moved close to the second substrate. The picking unit has a space apart from the second substrate. The first semiconductor device and the second semiconductor device are transferred from the picking unit to the second substrate. The he first semiconductor device and the second semiconductor device on the second substrate have a second gap between thereof. The first gap and the second gap are different.
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: December 28, 2021
    Assignee: EPISTAR CORPORATION
    Inventors: Hao-Min Ku, You-Hsien Chang, Shih-I Chen, Fu-Chun Tsai, Hsin-Chih Chiu
  • Patent number: 11195993
    Abstract: Encapsulation topography-assisted techniques for forming self-aligned top contacts in MRAM devices are provided. In one aspect, a method for forming an MRAM device includes: forming MTJs on interconnects embedded in a first dielectric; depositing an encapsulation layer over the MTJs; burying the MTJs in a second dielectric; patterning a trench in the second dielectric over the MTJs exposing the encapsulation layer over tops of the MTJs which creates a topography at the trench bottom; forming a metal line in the trench over the topography; recessing the metal line which breaks up the metal line into segments separated by exposed peaks of the encapsulation layer; recessing the exposed peaks of the encapsulation layer to form recesses at the tops of the MTJs; and forming self-aligned contacts in the recesses. An MRAM device is also provided.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: December 7, 2021
    Assignee: International Business Machines Corporation
    Inventors: Michael Rizzolo, Nicholas Anthony Lanzillo, Benjamin D. Briggs, Lawrence A. Clevenger
  • Patent number: 11189785
    Abstract: A method of manufacturing a magnetoresistive stack/structure comprising (a) etching through a second magnetic region to (i) provide sidewalls of the second magnetic region and (ii) expose a surface of a dielectric layer, (b) depositing a first encapsulation layer on the sidewalls of the second magnetic region and over a surface of the dielectric layer. (c) thereafter: (i) etching the first encapsulation layer which is disposed over the dielectric layer using a first etch process, and (ii) etching re-deposited material using a second etch process, wherein, after such etching, a portion of the first encapsulation layer remains on the sidewalls of the second magnetic region, (d) etching (i) through the dielectric layer to form a tunnel barrier and provide sidewalls thereof and (ii) etching the first magnetic region to provide sidewalls thereof, and (e) depositing a second encapsulation layer on the sidewalls of the tunnel barrier and first magnetic region.
    Type: Grant
    Filed: April 10, 2020
    Date of Patent: November 30, 2021
    Assignee: Everspin Technologies, Inc.
    Inventors: Sarin A. Deshpande, Kerry Joseph Nagel, Chaitanya Mudivarthi, Sanjeev Aggarwal
  • Patent number: 11183627
    Abstract: Some embodiments relate to a memory device. The memory device includes a memory cell overlying a substrate, the memory cell includes a data storage structure disposed between a lower electrode and an upper electrode. An upper interconnect wire overlying the upper electrode. A first inter-level dielectric (ILD) layer surrounding the memory cell and the upper interconnect wire. A second ILD layer overlying the first ILD layer and surrounding the upper interconnect wire. A sidewall spacer laterally surrounding the memory cell. The sidewall spacer has a first sidewall abutting the first ILD layer and a second sidewall abutting the second ILD layer.
    Type: Grant
    Filed: January 2, 2020
    Date of Patent: November 23, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Chau Chen, Cheng-Tai Hsiao, Cheng-Yuan Tsai, Hsun-Chung Kuang
  • Patent number: 11171285
    Abstract: Provided is a non-ferromagnetic spacing composite layer, comprising first, second and third spacing layers stacked in sequence. The first and third spacing layers are each made of Re, Rh, Ir, W, Mo, Ta, or Nb, and the second spacing layer is made of Ru. The second spacing layer has a thickness of equal to or more than 0.18 nm, and the non-ferromagnetic spacing composite layer has a total thickness of 0.6 nm to 1 nm. Also, provided are a method of preparing the non-ferromagnetic spacing composite layer, a synthetic antiferromagnetic laminated structure, and an MRAM. The synthetic antiferromagnetic laminated structure can maintain a certain coupling strength and the RKKY indirect interaction after thermal treatment, thereby keeping the recording function of MRAM.
    Type: Grant
    Filed: December 4, 2020
    Date of Patent: November 9, 2021
    Assignee: SOLAR APPLIED MATERIALS TECHNOLOGY CORP.
    Inventors: Chih-Huang Lai, Chun-Liang Yang, Yi-Huan Chung, Wei-Chih Huang, Chih-Wen Tang, Hui-Wen Cheng
  • Patent number: 11170834
    Abstract: A memory cell comprises a capacitor comprising a first capacitor electrode having laterally-spaced walls, a second capacitor electrode comprising a portion above the first capacitor electrode, and capacitor insulator material between the second capacitor electrode and the first capacitor electrode. The capacitor comprises an intrinsic current leakage path from one of the first and second capacitor electrodes to the other through the capacitor insulator material. A parallel current leakage path is between the second capacitor electrode and the first capacitor electrode. The parallel current leakage path is circuit-parallel with the intrinsic current leakage path, of lower total resistance than the intrinsic current leakage path, and comprises leaker material that is everywhere laterally-outward of laterally-innermost surfaces of the laterally-spaced walls of the first capacitor electrode. Other embodiments, including methods, are disclosed.
    Type: Grant
    Filed: July 10, 2019
    Date of Patent: November 9, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Michael Mutch, Ashonita A. Chavan, Sameer Chhajed, Beth R. Cook, Kamal Kumar Muthukrishnan, Durai Vishak Nirmal Ramaswamy, Lance Williamson
  • Patent number: 11165017
    Abstract: A replacement bottom electrode structure process is provided in which a patterned stack containing a MTJ pillar and a top electrode structure is fabricated and passivated on a sacrificial dielectric material plug that is embedded in a dielectric capping layer. The sacrificial dielectric material plug is then removed and replaced with a bottom electrode structure. The replacement bottom electrode structure process of the present application allows the MTJ patterning to be misalignment tolerate and fully eliminates the potential yield loss from the bottom electrode structure.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: November 2, 2021
    Assignee: International Business Machines Corporation
    Inventors: Pouya Hashemi, Takashi Ando, Dimitri Houssameddine, Alexander Reznicek, Jingyun Zhang, Choonghyun Lee
  • Patent number: 11164976
    Abstract: The disclosed technology generally relates to ferroelectric materials and semiconductor devices, and more particularly to semiconductor memory devices incorporating doped polar materials. In one aspect, a semiconductor device comprises a capacitor which in turn comprises a polar layer comprising a base polar material doped with a dopant. The base polar material includes one or more metal elements and one or both of oxygen or nitrogen. The dopant comprises a metal element that is different from the one or more metal elements and is present at a concentration such that a ferroelectric switching voltage of the capacitor is different from that of the capacitor having the base polar material without being doped with the dopant by more than about 100 mV. The capacitor stack additionally comprises first and second crystalline conductive oxide electrodes on opposing sides of the polar layer.
    Type: Grant
    Filed: April 7, 2020
    Date of Patent: November 2, 2021
    Assignee: Kepler Computing Inc.
    Inventors: Ramesh Ramamoorthy, Sasikanth Manipatruni, Gaurav Thareja
  • Patent number: 11164936
    Abstract: A first-layer insulating film having a barrier property against a determined element contained in a ferroelectric capacitor as well as an oxygen permeability, a hydrogen permeability, and a water permeability is formed over a surface of the ferroelectric capacitor formed over a substrate. After that, heat treatment is performed in an oxidizing atmosphere. After the heat treatment, a second insulating film having a hydrogen permeability and a water permeability lower than those of the first-layer insulating film respectively is formed over a surface of the first-layer insulating film in a non-reducing atmosphere. A third-layer insulating film is formed over a surface of the second-layer insulating film. By doing so, degradation of a ferroelectric film under and after the formation of a semiconductor device having the ferroelectric capacitor is suppressed and deterioration in the characteristics of the ferroelectric capacitor is suppressed.
    Type: Grant
    Filed: January 3, 2020
    Date of Patent: November 2, 2021
    Assignee: FUJITSU SEMICONDUCTOR MEMORY SOLUTION LIMITED
    Inventors: Youichi Okita, Wensheng Wang, Kazuaki Takai
  • Patent number: 11152563
    Abstract: A dielectric material structure is formed laterally adjacent to a bottom portion of a bottom electrode metal-containing portion that extends upward from an electrically conductive structure that is embedded in an interconnect dielectric material layer. The physically exposed top portion of the bottom electrode metal-containing portion is then trimmed to provide a bottom electrode of unitary construction (i.e., a single piece) that has a lower portion having a first diameter and an upper portion that has a second diameter that is greater than the first diameter. The presence of the dielectric material structure prevents tilting and/or bowing of the resultant bottom electrode. Thus, a stable bottom electrode is provided.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: October 19, 2021
    Assignee: International Business Machines Corporation
    Inventors: Bruce B. Doris, Eileen A. Galligan, Nathan P. Marchack, Pouya Hashemi
  • Patent number: 11145808
    Abstract: Embodiments of the disclosure provide methods and apparatus for fabricating magnetic tunnel junction (MTJ) structures on a substrate for MRAM applications. In one embodiment, a method for forming a magnetic tunnel junction (MTJ) device structure includes performing a patterning process by an ion beam etching process in a processing chamber to pattern a film stack disposed on a substrate, wherein the film stack comprises a reference layer, a tunneling barrier layer and a free layer disposed on the tunneling barrier, and determining an end point for the patterning process.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: October 12, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Jong Mun Kim, Minrui Yu, Chando Park, Mang-Mang Ling, Jaesoo Ahn, Chentsau Chris Ying, Srinivas D. Nemani, Mahendra Pakala, Ellie Y. Yieh
  • Patent number: 11139239
    Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) including an interconnect structure overlying a substrate. The interconnect structure has a plurality of metal layers overlying over the substrate. A first dielectric layer overlies an uppermost surface of the interconnect structure. The first dielectric layer has opposing sidewalls defining a trench. A first magnetic layer is disposed within the trench and conformally extends along the opposing sidewalls. Conductive wires are disposed within the trench and overlie the first magnetic layer. A second magnetic layer overlies the first magnetic layer and the conductive wires. The second magnetic layer laterally extends from over a first sidewall of the opposing sidewalls to a second sidewall of the opposing sidewalls.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: October 5, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Wen Hsu, Jiech-Fun Lu, Kai Tzeng, Wei-Li Huang
  • Patent number: 11139202
    Abstract: Integrated chips and methods of forming the same include forming upper dummy lines over lower conductive lines. The lower conductive lines are recessed to form conductive vias between the lower conductive lines and the upper dummy lines. The upper dummy lines are replaced with upper conductive lines that contact the conductive vias.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: October 5, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chanro Park, Koichi Motoyama, Kenneth C. K. Cheng, Chih-Chao Yang
  • Patent number: 11139011
    Abstract: A method for forming a semiconductor structure is disclosed. A substrate having a logic device region and a memory device region is provided. A first dielectric layer is formed on the substrate. Plural memory stack structures are formed on the first dielectric layer on the memory device region. An insulating layer is formed and conformally covers the memory stack structures and the first dielectric layer. An etching back process is performed to remove a portion of the insulating layer without exposing any portion of the memory stack structures. After the etching back process, a second dielectric layer is formed on the insulating layer and completely fills the spaces between the memory stack structures.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: October 5, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Yu-Ping Wang, Chen-Yi Weng, Chin-Yang Hsieh, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, I-Ming Tseng, Jing-Yin Jhang, Chien-Ting Lin
  • Patent number: 11133460
    Abstract: Embodiments of the disclosure provide methods and apparatus for fabricating magnetic tunnel junction (MTJ) structures on a substrate in for spin-transfer-torque magnetoresistive random access memory (STT-MRAM) applications. In one example, a film stack utilized to form a magnetic tunnel junction structure on a substrate includes a pinned layer disposed on a substrate, wherein the pinned layer comprises multiple layers including at least one or more of a Co containing layer, Pt containing layer, Ta containing layer, an Ru containing layer, an optional structure decoupling layer disposed on the pinned magnetic layer, a magnetic reference layer disposed on the optional structure decoupling layer, a tunneling barrier layer disposed on the magnetic reference layer, a magnetic storage layer disposed on the tunneling barrier layer, and a capping layer disposed on the magnetic storage layer.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: September 28, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Lin Xue, Jaesoo Ahn, Mahendra Pakala, Chi Hong Ching, Rongjun Wang
  • Patent number: 11133028
    Abstract: A magnetoresistance effect element has a first ferromagnetic metal layer, a second ferromagnetic metal layer, and a tunnel barrier layer that is sandwiched between the first and second ferromagnetic metal layers, the tunnel barrier layer is expressed by a chemical formula of AB2Ox, and has a spinel structure in which cations are arranged in a disordered manner, A represents a divalent cation that is either Mg or Zn, and B represents a trivalent cation that includes a plurality of elements selected from the group consisting of Al, Ga, and In.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: September 28, 2021
    Assignee: TDK CORPORATION
    Inventor: Tomoyuki Sasaki
  • Patent number: 11127788
    Abstract: A semiconductor device is provided. The semiconductor device has a semiconductor layer including a source/drain region, a first magnetic layer over the semiconductor layer, and a first dielectric layer over the source/drain region and adjacent the first magnetic layer. The semiconductor device has a metal structure extending through the first dielectric layer, a second magnetic layer over the metal structure, and a second dielectric layer over the first magnetic layer and adjacent the first dielectric layer.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: September 21, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Baohua Niu, Da-Shou Chen