Having Magnetic Or Ferroelectric Component Patents (Class 438/3)
  • Patent number: 10446741
    Abstract: A method for etching a magnetic tunneling junction (MTJ) structure is described. A stack of MTJ layers on a bottom electrode on a wafer is provided. A metal hard mask layer is provided on the MTJ stack. A stack of multiple dielectric hard masks is formed on the metal hard mask wherein each successive dielectric hard mask has etch selectivity with respect to its underlying and overlying layers. The dielectric hard mask layers are etched in turn selectively with respect to their underlying and overlying layers wherein each successive pattern size is smaller than the preceding pattern size. The MTJ stack is etched selectively with respect to the bottommost combination dielectric and metal hard mask pattern to form a MTJ device having a MTJ pattern size smaller than a bottommost pattern size.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: October 15, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi Yang, Yu-Jen Wang, Jesmin Haq, Tom Zhong
  • Patent number: 10446742
    Abstract: A method for manufacturing a magnetic memory element array. A plurality of magnetic memory elements are formed on a substrate, and a dielectric fill layer such as SiO2 or SiNx is deposited over the magnetic memory element pillars. An ion milling is then performed at a high angle (at least 70 degrees) relative normal to remove topographic dielectric features from areas over the magnetic memory elements. Optionally, additional ion milling processes can be performed at increasing angles relative to normal until the dielectric material has been removed from the areas over the magnetic memory elements.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: October 15, 2019
    Assignee: SPIN MEMORY, INC.
    Inventors: Marcin Gajek, Eric Michael Ryan, Mustafa Pinarbasi
  • Patent number: 10431735
    Abstract: An electronic device including a semiconductor memory. The semiconductor memory may include a variable resistance element exhibiting two different states for storing data; and an upper layer disposed over the variable resistance element, and wherein the upper layer may have a stepped or sloped profile and be located to serve as a part of a hard mask to pattern the variable resistance element.
    Type: Grant
    Filed: February 2, 2018
    Date of Patent: October 1, 2019
    Assignee: SK hynix Inc.
    Inventor: Ki-Won Nam
  • Patent number: 10424725
    Abstract: A spintronics element including a ferromagnetic layer containing boron, and a diffusion stopper film covering a side face of the ferromagnetic layer partially or entirely, the side face in direct contact with diffusion stopper film, so as to prevent out-diffusion of the boron contained in the ferromagnetic layer. The diffusion stopper film contains boron at a concentration higher than a concentration of the boron in a portion of the ferromagnetic layer where the ferromagnetic layer contacts the diffusion stopper film.
    Type: Grant
    Filed: June 20, 2018
    Date of Patent: September 24, 2019
    Assignee: TOHOKU UNIVERSITY
    Inventors: Soshi Sato, Masaaki Niwa, Hiroaki Honjo, Shoji Ikeda, Hideo Sato, Hideo Ohno, Tetsuo Endoh
  • Patent number: 10424726
    Abstract: A method for improving photo resist adhesion to an underlying hard mask layer. The method includes a cleaning step that includes applying tetramethylammonium hydroxide (TMAH) to coat a hard mask layer of a wafer. The method further includes puddle developing the wafer for a first desired amount of time, and rinsing the wafer in running water for a second desired amount of time. The method further includes spin drying the wafer, and baking the wafer for a third desired amount of time. The method concludes with the proceeding of subsequent photolithographic processes on the wafer.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: September 24, 2019
    Assignee: Spin Memory, Inc.
    Inventors: Elizabeth Dobisz, Pradeep Manandhar
  • Patent number: 10396274
    Abstract: A method of manufacturing a spintronics element from laminated layers. The method includes (a) forming a plurality of laminated layers in manufacturing equipment, (b) forming a wafer in the manufacturing equipment, including applying a protection layer directly on a non-magnetic uppermost layer of the laminated layers so that the protection layer prevents alteration of characteristics of the uppermost layer, and (c) exposing the wafer, outside of the manufacturing equipment, to an atmosphere that includes H2O having a partial pressure in the atmosphere equal to or larger than 10?4 Pa.
    Type: Grant
    Filed: March 8, 2016
    Date of Patent: August 27, 2019
    Assignee: TOHOKU UNIVERSITY
    Inventors: Soshi Sato, Masaaki Niwa, Hiroaki Honjo, Shoji Ikeda, Hideo Ohno, Tetsuo Endo
  • Patent number: 10377978
    Abstract: According to the present invention, it is possible to provide a cleaning solution which removes a dry etching residue and photoresist on a surface of a semiconductor element having a low dielectric constant film (a low-k film) and at least one material selected from between a material that contains 10 atom % or more of titanium and a material that contains 10 atom % or more of tungsten, wherein the cleaning solution contains: 0.002-50 mass % of at least one type of oxidizing agent selected from among a peroxide, perchloric acid, and a perchlorate salt; 0.000001-5 mass % of an alkaline earth metal compound; and water.
    Type: Grant
    Filed: October 2, 2015
    Date of Patent: August 13, 2019
    Assignee: MITSUBISHI GAS CHEMICAL COMPANY, INC.
    Inventors: Toshiyuki Oie, Kenji Shimada
  • Patent number: 10374052
    Abstract: A semiconductor device with reduce capacitance coupling effect which can reduce the overall parasitic capacitances is disclosed. The semiconductor device includes a gate sidewall spacer with a negative capacitance dielectric layer with and without a dielectric layer. The semiconductor device may also include a plurality of interlevel dielectric (ILD) with a layer of negative capacitance dielectric layer followed by a dielectric layer disposed in-between metal lines in any ILD and combinations. The negative capacitance dielectric layer includes a ferroelectric material which has calculated and selected thicknesses with desired negative capacitance to provide optimal total overlap capacitance in the circuit component which aims to reduce the overall capacitance coupling effect.
    Type: Grant
    Filed: October 12, 2017
    Date of Patent: August 6, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Shyue Seng Tan, Kiok Boone Elgin Quek, Eng Huat Toh
  • Patent number: 10374005
    Abstract: Methods of forming a MTJ dummy fill gradient across near-active-MRAM-cell periphery and far-outside-MRAM logic regions and the resulting device are provided. Embodiments include providing an embedded MRAM layout with near-active-MRAM-cell periphery logic and far-outside-MRAM logic regions; forming a MTJ structure within the layout based on minimum space and distance rules relative to a first metal layer, a second metal layer, and/or both the first and second metal layers; forming a high-density MTJ dummy structure in the near-active-MRAM-cell periphery logic region based on second minimum space and distance rules relative to a first metal layer, a second metal layer, and/or both the first metal layer and the second metal layer; and forming a low-density MTJ dummy structure in the far-outside-MRAM logic region based on third minimum space and distance rules relative to a first metal layer, a second metal layer, and/or both the first metal layer and the second metal layer.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: August 6, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Pinghui Li, Haiqing Zhou, Liying Zhang, Wanbing Yi, Ming Zhu, Danny Pak-Chum Shum, Darin Chan
  • Patent number: 10367139
    Abstract: A method of manufacturing a Magnetic Tunnel Junction (MTJ) device including pillar contacts coupling the free magnetic layer of MTJ pillars to a top contact. The pillar contacts are electrically isolated from one or more other portions of the MTJ pillar by one or more self-aligned sidewall insulators. The MTJ device further including one of a static magnetic compensation layer or an exchange spring layer in the MTJ pillar.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: July 30, 2019
    Assignee: Spin Memory, Inc.
    Inventors: Thomas Boone, Pradeep Manandhar, Manfred Schabes, Bartlomiej Kardasz, Mustafa Pinarbasi
  • Patent number: 10355198
    Abstract: A memory device includes an MTJ structure and a first metal residue. The MTJ structure includes a top surface having a first width, a bottom surface having a second width greater than the first width, and a stepped sidewall structure between the top surface and the bottom surface. The stepped sidewall structure includes a first sidewall, a second sidewall, and an intermediary surface connecting the first sidewall to the second sidewall. The first metal residue is in contact with the first sidewall and not in contact with the second sidewall.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: July 16, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Hao Liao, Chih-Wei Lu, Hsi-Wen Tien, Pin-Ren Dai, Chung-Ju Lee
  • Patent number: 10347819
    Abstract: Methods of manufacturing a semiconductor device include forming a conductive layer on a substrate, forming an air gap or other cavity between the conductive layer and the substrate, and patterning the conductive layer to expose the air gap. The methods may further include forming conductive pillars between the substrate and the conductive layer. The air gap may be positioned between the conductive pillars.
    Type: Grant
    Filed: November 1, 2016
    Date of Patent: July 9, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jongchul Park, Byoungjae Bae, Inho Kim, Shin Kwon, Eunsun Noh, Insun Park, Sangmin Lee
  • Patent number: 10333063
    Abstract: According to one embodiment, a method includes forming an etch-stop layer above a substrate, forming a matrix layer above the etch-stop layer, forming a set of pillars above the matrix layer, the set of pillars having a predefined spacing therebetween along a plane in an element width direction and an element depth direction, the plane being normal to a film thickness direction, forming a functionalization layer above the pillars, along sides of the pillars, and above the matrix layer, forming first diblock copolymer layers above the functionalization layer, the first diblock copolymer layers self-segregating into a first polymer and a second polymer in a first pattern, removing the first polymer from the first diblock copolymer layers to create a first mask layer, and removing portions of the matrix layer to expose portions of the etch-stop layer positioned therebelow and create a second pattern in the matrix layer.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: June 25, 2019
    Assignee: SPIN MEMORY, INC.
    Inventors: Kuk-Hwan Kim, Dafna Beery, Amitay Levi, Andrew J. Walker
  • Patent number: 10297658
    Abstract: A system that incorporates teachings of the subject disclosure may include, for example, a thin film capacitor having a substrate, a first electrode layer on the substrate, a first dielectric layer on the first electrode layer where the first dielectric layer has a columnar-oriented grain structure, a group of second dielectric layers stacked on the first dielectric layer where each of the group of second dielectric layers has a randomly-oriented grain structure, and a second electrode layer on the group of second dielectric layers. Other embodiments are disclosed.
    Type: Grant
    Filed: June 16, 2016
    Date of Patent: May 21, 2019
    Assignee: BLACKBERRY LIMITED
    Inventors: Marina Zelner, Andrew Vladimir Claude Cervin, Edward Horne
  • Patent number: 10285659
    Abstract: Imaging methods and imaging systems are provided. Methods and systems of the subject invention can include the use of nanoparticles (for example, nanophosphors) within a sample to be imaged. X-ray engraving can be performed and/or X-ray excitation can be used to provide energy to the sample. Stimulation with infrared light, such as near-infrared (NIR) light, and/or optical multiplexing can be used to acquire tomographic data of the sample.
    Type: Grant
    Filed: December 8, 2014
    Date of Patent: May 14, 2019
    Assignee: Rensselaer Polytechnic Institute
    Inventors: Ge Wang, Wenxiang Cong, Chao Wang, Fenglin Liu
  • Patent number: 10256187
    Abstract: A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate; a winding structure formed on a top side the semiconductor substrate, wherein the winding structure comprises one or more metal lines winding with respect to a center of the winding structure; and a backside metal formed under a backside of the semiconductor substrate; wherein a hollow slot is formed within the backside metal, and a projection of the winding structure is within the hollow slot.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: April 9, 2019
    Assignee: WIN Semiconductors Corp.
    Inventors: Jui-Chieh Chiu, Chih-Wen Huang, You-Cheng Lai
  • Patent number: 10256395
    Abstract: An embodiment includes an apparatus comprising: a magnetic tunnel junction (MTJ), between first and second electrodes, comprising a dielectric layer between fixed and free layers; a dielectric film directly contacting sidewalls of the first electrode; and a metallic layer coupled to the sidewalls via the dielectric film; wherein (a) a vertical axis intersects the first and second electrodes and the MTJ but not the metallic layer, (b) a first horizontal axis intersects the metallic layer, the dielectric film, and the first electrode; and (c) a second horizontal axis, between the first horizontal axis and the MTJ, intersects the dielectric film and the first electrode but not the capping layer. Other embodiments are described herein.
    Type: Grant
    Filed: June 19, 2015
    Date of Patent: April 9, 2019
    Assignee: Intel Corporation
    Inventors: Daniel R. Lamborn, Oleg Golonzka, Christopher J. Wiegand, Philip E. Heil, M D Tofizur Rahman, Rebecca J. Castellano, Tarun Bansal
  • Patent number: 10256398
    Abstract: Spin transfer torque magnetic random access memory structures, integrated circuits, and methods for fabricating integrated circuits and/or memory cells are provided. An exemplary method for fabricating integrated circuit includes forming a bottom electrode and forming a fixed layer disposed over the bottom electrode. The fixed layer includes a hard layer disposed over a base layer. The base layer includes a seed layer of nickel (Ni) and chromium (Cr) and has a thickness of less than about 100 Angstrom (A). The method further includes forming at least a first tunnel barrier layer over the hard layer, forming a storage layer over the first tunnel barrier layer, and forming a top electrode over the storage layer.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: April 9, 2019
    Assignee: Globalfoundries Singapore Pte. Ltd.
    Inventor: Taiebeh Tahmasebi
  • Patent number: 10222350
    Abstract: A high sensitivity force gauge using a magnetic PDL trap system is provided. In one aspect, a force gauge includes: a PDL trap having a pair of dipole line magnets and a diamagnetic rod levitating above the dipole line magnets; an actuator with an extension bar adjacent to the PDL trap; a first object of interest attached to the diamagnetic rod; and a second object of interest attached to the extension bar, wherein the actuator is configured to move the second object of interest toward or away from the PDL trap via the extension bar. A method for force measurement using the present force gauge is also provided.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: March 5, 2019
    Assignee: International Business Machines Corporation
    Inventor: Oki Gunawan
  • Patent number: 10217933
    Abstract: A method according to an exemplary embodiment includes: (a) etching an upper magnetic layer by plasma generated within a processing container, the etching of the upper magnetic layer being terminated on a surface of an insulating layer; (b) removing a deposit formed on a surface of the mask and the upper magnetic layer by etching the upper magnetic layer, by the plasma generated within the processing container; and (c) etching the insulating layer by the plasma generated within the processing container. In the step of removing the deposit, the support structure that holds a processing target is inclined and rotated, and a pulse-modulated DC voltage as a bias voltage for ion attraction is applied to the support structure.
    Type: Grant
    Filed: October 8, 2015
    Date of Patent: February 26, 2019
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Eiichi Nishimura, Mitsunori Ohata
  • Patent number: 10211146
    Abstract: A semiconductor device may include a transistor gate in a device layer; an interconnect layer over the device layer; and an air gap extending through the interconnect layer to contact an upper surface of the transistor gate. The air gap provides a mechanism to reduce both on-resistance and off-capacitance for applications using SOI substrates such as radio frequency switches.
    Type: Grant
    Filed: May 12, 2016
    Date of Patent: February 19, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Zhong-Xiang He, Mark D. Jaffe, Randy L. Wolf, Alvin J. Joseph, Brett T. Cucci, Anthony K. Stamper
  • Patent number: 10205089
    Abstract: This technology provides an electronic device and a method of fabricating the same. An electronic device in accordance with an implementation of this document includes semiconductor memory, and the semiconductor memory includes an interlayer dielectric layer formed over a substrate and having a contact hole; a lower contact filled in a part of the contact hole; and a variable resistance element which is disposed over and coupled to the lower contact, and has a first part filled in the contact hole and a second part disposed over the first part and protruding over the interlayer dielectric layer, wherein the first part includes a first metal which has a higher electron affinity than a component included in the second part, and an oxide of the first metal is an insulating material.
    Type: Grant
    Filed: June 3, 2014
    Date of Patent: February 12, 2019
    Assignee: SK hynix Inc.
    Inventors: Jae-Hong Kim, Min-Suk Lee
  • Patent number: 10199264
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to self-aligned interconnect structures and methods of manufacture. The structure includes an interconnect structure which is self-aligned with an upper level via metallization, and both the interconnect structure and the upper level via metallization are composed of a Pt group material.
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: February 5, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Xunyuan Zhang, Roderick A. Augur, Hoon Kim
  • Patent number: 10181407
    Abstract: This method for manufacturing a niobate-system ferroelectric thin-film device includes: a lower electrode film formation step of forming a lower electrode film on a substrate; a ferroelectric thin film formation step of forming a niobate-system ferroelectric thin film on the lower electrode film; an etch mask pattern formation step of forming an etch mask in a desired pattern on the niobate-system ferroelectric thin film, the etch mask being an amorphous fluororesin film laminated via a noble metal film; and a ferroelectric thin film etching step of shaping the niobate-system ferroelectric thin film into a desired fine pattern by wet etching using an etchant comprising: a chelating agent; an aqueous alkaline solution containing an aqueous ammonia solution; and an aqueous hydrogen peroxide solution.
    Type: Grant
    Filed: March 17, 2016
    Date of Patent: January 15, 2019
    Assignee: SUMITOMO CHEMICAL COMPANY, LIMITED
    Inventors: Fumimasa Horikiri, Kenji Shibata, Kazutoshi Watanabe, Kazufumi Suenaga, Masaki Noguchi, Kenji Kuroiwa
  • Patent number: 10170696
    Abstract: Materials are disclosed that are used as seed layers in the formation of MRAM elements. In particular, a MnN layer oriented in the (001) direction is grown over a substrate. A magnetic layer overlying and in contact with the MnN layer forms part of a magnetic tunnel junction, in which the magnetic layer includes a Heusler compound that includes Mn. The magnetic tunnel junction includes the magnetic layer, a tunnel barrier overlying the magnetic layer, and a first (magnetic) electrode overlying the tunnel barrier. A second electrode is in contact with the MnN layer.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: January 1, 2019
    Assignees: International Business Machines Corporation, Samsung Electronics Co., Ltd.
    Inventors: Jaewoo Jeong, Stuart S. P. Parkin, Mahesh G. Samant
  • Patent number: 10157706
    Abstract: An inductor structure is provided. The inductor structure includes a first dielectric layer formed over a substrate and a magnetic layer formed over the first dielectric layer. The magnetic layer has a planar top surface, a planar bottom surface, a protruding portion surrounding the planar top surface, and the protruding portion is higher than the planar top surface.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: December 18, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yuan-Tai Tseng, Ming-Chyi Liu, Chung-Yen Chou, Chia-Shiung Tsai
  • Patent number: 10153427
    Abstract: A process flow for forming magnetic tunnel junctions (MTJs) with minimal sidewall residue and reduced low tail population is disclosed wherein a pattern is first formed in a hard mask that is an uppermost MTJ layer. Thereafter, the hard mask pattern is etch transferred through the underlying MTJ layers including a reference layer/tunnel barrier/free layer stack. The etch transfer may be completed in a single RIE step based on a first flow rate of O2 and a second flow rate of an oxidant such as CH3OH where the CH3OH/O2 ratio is at least 7.5:1. The RIE may also include a flow rate of a noble gas. In other embodiments, a chemical treatment with an oxidant such as CH3OH, and a volatilization at 50° C. to 450° C. may follow an etch transfer through the MTJ stack when the ion beam etch or plasma etch involves noble gas ions.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: December 11, 2018
    Assignee: Headway Technologies, Inc.
    Inventors: Dongna Shen, Yu-Jen Wang
  • Patent number: 10141068
    Abstract: A magnetic element capable of generating and erasing a skyrmion, including a magnet shaped as a thin layer and including a structure surrounded by a nonmagnetic material; a current path provided surrounding an end region including an end portion of the magnet, on one surface of the magnet; and a skyrmion sensor that detects the generation and erasing of the skyrmion. With Wm being width of the magnet and hm being height of the magnet, a size of the magnet, with the skyrmion of a diameter ? being generated, is such that 2?>Wm>?/2 and 2?>hm>?/2. With W being width of the end region in a direction parallel to the end portion of the magnet and h being height of the end region in a direction perpendicular to the end portion of the magnet, the end region is such that ??W>?/4 and 2?>h>?/2.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: November 27, 2018
    Assignee: RIKEN
    Inventors: Naoto Nagaosa, Wataru Koshibae, Junichi Iwasaki, Masashi Kawasaki, Yoshinori Tokura, Yoshio Kaneko
  • Patent number: 10128306
    Abstract: A light-emitting diode package including a body and leads. The body comprising a mounting surface. The light emitting diode package also includes a light emitting diode chip including a substrate and a plurality of light emitting cells disposed on the substrate and positioned to be spaced apart from each other, each of the plurality of light emitting cells comprising an active layer disposed between a first conductive-type semiconductor layer and a second conductive-type semiconductor layer. The light emitting diode package also includes a phosphor member disposed on the light-emitting diode chip and a distributed Bragg reflector disposed on the substrate and between the plurality of light emitting cells.
    Type: Grant
    Filed: January 9, 2017
    Date of Patent: November 13, 2018
    Assignee: Seoul Viosys Co., Ltd.
    Inventors: Sum Geun Lee, Sang Ki Jin, Jin Cheol Shin, Jong Kyu Kim, So Ra Lee, Chung Hoon Lee
  • Patent number: 10121958
    Abstract: An object is to prevent a short failure in magnetic tunnel junction and thereby suppress a semiconductor device having a magnetic memory cell from having deteriorated reliability. First, a data reference layer and a cap layer are patterned. After formation of an oxygen-free first insulating film on their side walls, a base layer, a data recording layer, and a tunnel barrier layer are patterned. During patterning of the base layer, data recording layer, and tunnel barrier layer, adhesion of a metal substance of the data reference layer and the cap layer to the side wall of the tunnel barrier layer can be prevented because the data reference layer and the cap layer are covered by the first insulating film.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: November 6, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Takashi Tonegawa, Keiji Sakamoto
  • Patent number: 10115893
    Abstract: A method of manufacturing a data storage device may include forming a magnetic tunnel junction layer on a substrate, irradiating a first ion beam on the magnetic tunnel junction layer to form magnetic tunnel junction patterns separated from each other, irradiating a second ion beam on the magnetic tunnel junction layer, and irradiating a third ion beam on the magnetic tunnel junction layer. The first ion beam may be irradiated at a first incident angle. The second ion beam may be irradiated at a second incident angle that may be smaller than the first incident angle. The third ion beam may be irradiated to form sidewall insulating patterns on sidewalls of the magnetic tunnel junction patterns based on re-depositing materials separated by the third ion beam on the sidewalls of the magnetic tunnel junction patterns.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: October 30, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jongchul Park, Sang-Kuk Kim
  • Patent number: 10098231
    Abstract: An integrated electronic assembly including a first electronic component defining a receptacle and at least a second electronic component wherein at least a portion of the second electronic component is disposed in the receptacle of the first electronic component, and a method for conserving space in a circuit or on a printed circuit board by integrating a plurality of electronic components so that the plurality of electronic components collectively take up a smaller amount of space on a substrate than the plurality of electronic components would if the plurality of electronic components were not integrated.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: October 9, 2018
    Assignee: Coilcraft, Incorporated
    Inventor: Stephen Michael Sedio
  • Patent number: 10090462
    Abstract: Electronic apparatus, systems, and methods can include a resistive memory cell having a structured as an operably variable resistance region between two electrodes and a metallic barrier disposed in a region between the dielectric and one of the two electrodes. The metallic barrier can have a structure and a material composition to provide oxygen diffusivity above a first threshold during program or erase operations of the resistive memory cell and oxygen diffusivity below a second threshold during a retention state of the resistive memory cell. Additional apparatus, systems, and methods are disclosed.
    Type: Grant
    Filed: December 7, 2015
    Date of Patent: October 2, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Durai Vishak Nirmal Ramaswamy, Lei Bi, Beth R. Cook, Dale W. Collins
  • Patent number: 10084016
    Abstract: A method of fabricating a memory device is disclosed. In one aspect, the method comprises patterning a first conductive line extending in a first direction. The method additionally includes forming a free-standing pillar of a memory cell stack on the first conductive line after patterning the first conductive line. Forming the free-standing pillar includes depositing a memory cell stack comprising a selector material and a storage material over the conductive line and patterning the memory cell stack to form the free-standing pillar. The method further includes patterning a second conductive line on the pillar after patterning the memory cell stack, the second conductive line extending in a second direction crossing the first direction.
    Type: Grant
    Filed: November 21, 2013
    Date of Patent: September 25, 2018
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Ombretta Donghi, Marcello Ravasio, Samuele Sciarrillo, Roberto Somaschini
  • Patent number: 10068984
    Abstract: A semiconductor device and method of manufacturing same are described. A first hafnium oxide (HfO2) layer is formed on a substrate. A titanium (Ti) layer is formed over the first hafnium oxide layer. A second hafnium oxide layer is formed over the titanium layer. The composite device structure is thermally annealed to produce a high-k dielectric structure having a hafnium titanium oxide (HfxTi1-xO2) layer interposed between the first hafnium oxide layer and the second hafnium oxide layer.
    Type: Grant
    Filed: September 1, 2016
    Date of Patent: September 4, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: I-Chen Huang, Yi-Ju Hsu, Chi-Wen Liu, Kuang-Hsin Chen, Yung-Hsien Wu, Chin-Yu Chen
  • Patent number: 10062837
    Abstract: A composition for cleaning a magnetic pattern, a method of manufacturing a magnetic memory device, a method of forming a magnetic pattern, and a magnetic memory device, the composition including a glycol ether-based organic solvent; a decomposing agent that includes an aliphatic amine; and at least one of a chelating agent, or a cleaning accelerator that includes an organic alkaline compound, wherein the composition is devoid of water.
    Type: Grant
    Filed: September 8, 2016
    Date of Patent: August 28, 2018
    Assignees: SAMSUNG ELECTRONICS CO., LTD., SAMYOUNG PURE CHEMICALS CO., LTD.
    Inventors: Ho-Young Kim, Jin-Hye Bae, Hoon Han, Won-Jun Lee, Chang-Kyu Lee, Geun-Joo Baek, Jung-Ig Jeon
  • Patent number: 10062839
    Abstract: A magnetoresistive-based device and method of manufacturing a magnetoresistive-based device using one or more hard masks. The process of manufacture, in one embodiment, includes patterning a mask, after patterning the mask, etching (a) through a first layer of electrically conductive material to form an electrically conductive electrode and (b) through a third layer of ferromagnetic material to provide sidewalls of the second synthetic antiferromagnetic structure. The process further includes providing insulating material on or over the sidewalls of the second synthetic antiferromagnetic structure and, thereafter, etching through (a) a second tunnel barrier layer to provide sidewalls thereof, (b) a second layer of ferromagnetic material to provide sidewalls thereof, (c) a first tunnel barrier layer to provide sidewalls thereof, and (d) a first layer of ferromagnetic material to provide sidewalls of the first synthetic antiferromagnetic structure.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: August 28, 2018
    Assignee: Everspin Technologies, Inc.
    Inventors: Sarin A. Deshpande, Sanjeev Aggarwal, Kerry Joseph Nagel
  • Patent number: 10061205
    Abstract: A reflective optical element, in particular for a microlithographic projection exposure apparatus has a substrate (101), a reflection layer system (110) and a defect structure (120) of channel-shaped defects (121) which extend inward from the optical effective surface (100a), or from an interface oriented toward the substrate as far as the reflection layer system, and permit egress of hydrogen from the reflection layer system. The channel-shaped defects (121) increase a diffusion coefficient that is characteristic for the egress of the hydrogen from the reflection layer system (110) by at least 20%, in comparison to a similar layer construction without these channel-shaped defects.
    Type: Grant
    Filed: February 15, 2017
    Date of Patent: August 28, 2018
    Assignee: Carl Zeiss SMT GmbH
    Inventors: Dirk Heinrich Ehm, Moritz Becker, Irene Ament, Gisela Von Blanckenhagen, Joern Weber
  • Patent number: 10056543
    Abstract: In a method of manufacturing an MRAM device, a memory unit including a lower electrode, an MTJ structure and an upper electrode sequentially stacked is formed on a substrate. A protective layer structure including a capping layer, a sacrificial layer and an etch stop layer sequentially stacked is formed on the substrate to cover the memory unit. An insulating interlayer is formed on the protective layer structure. The insulating interlayer is formed to form an opening exposing the protective layer structure. The exposed protective layer structure is partially removed to expose the upper electrode. A wiring is formed on the exposed upper electrode to fill the opening.
    Type: Grant
    Filed: May 4, 2016
    Date of Patent: August 21, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Hoon Bak, Myoung-Su Son, Jae-Chul Shim, Gwan-Hyeob Koh, Yoon-Jong Song
  • Patent number: 10043871
    Abstract: Structure or device comprises a AlxGa1-xN or InyGa1-yN layer or substrate, a rare earth nitride epitaxial layer, and an AlzGa1-zN epitaxial interlayer between the rare earth nitride epitaxial layer and the AlxGa1-xN or InyGa1-yN layer or substrate. The interlayer is in direct contact with the rare earth nitride epitaxial layer and the AlxGa1-xN or InyGa1-yN layer or substrate.
    Type: Grant
    Filed: April 6, 2017
    Date of Patent: August 7, 2018
    Assignee: ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE (EPFL)
    Inventors: Franck Natali, Stéphane Ange Vézian
  • Patent number: 10025192
    Abstract: A composition for removing photoresist, including an alkyl ammonium fluoride salt in an amount ranging from about 0.5 weight percent to about 10 weight percent, based on a total weight of the composition; an organic sulfonic acid in an amount ranging from about 1 weight percent to about 20 weight percent, based on the total weight of the composition; and a lactone-based solvent in an amount ranging from about 70 weight percent to about 98.5 weight percent, based on the total weight of the composition.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: July 17, 2018
    Assignees: SAMSUNG ELECTRONICS CO., LTD., DONGWOO FINE-CHEM
    Inventors: Jung-Min Oh, Mi-Hyun Park, Hyo-San Lee, Ji-Hoon Jeong, Yong-Sun Ko, In-Gi Kim, Na-Rim Kim, Sang-Tae Kim, Seong-Min Kim, Kyong-Ho Lee
  • Patent number: 9991457
    Abstract: A method for preparing photoactive perovskite materials. The method comprises the step of preparing a lead halide precursor ink. Preparing a lead halide precursor ink comprises the steps of: introducing a lead halide into a vessel, introducing a first solvent to the vessel, and contacting the lead halide with the first solvent to dissolve the lead halide. The method further comprises depositing the lead halide precursor ink onto a substrate, drying the lead halide precursor ink to form a thin film, annealing the thin film, and rinsing the thin film with a second solvent and a salt.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: June 5, 2018
    Assignee: HEE Solar, L.L.C.
    Inventors: Michael D. Irwin, Jerred A. Chute, Vivek V. Dhas
  • Patent number: 9991870
    Abstract: A surface acoustic wave (SAW) resonator includes a piezoelectric layer disposed over a substrate, and a plurality of electrodes disposed over the first surface of the piezoelectric layer. A layer is disposed between the substrate and the piezoelectric layer. A silicon layer disposed between a first surface of the layer and a second surface of the piezoelectric layer. A first surface of the silicon layer has a smoothness sufficient to foster atomic bonding between the first surface of the silicon layer and the second surface of the piezoelectric layer.
    Type: Grant
    Filed: January 28, 2016
    Date of Patent: June 5, 2018
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Stephen Roy Gilbert, Richard C. Ruby
  • Patent number: 9988715
    Abstract: Methods of fabricating magnetic devices are described herein. Methods involve exposing a magnetic film, such as a CoFeB film, to a reducing agent before, during, or after depositing a metal oxide film using atomic layer deposition or chemical vapor deposition. Some methods include exposing the magnetic film in cycles involving exposure to a reducing agent, exposure to a magnesium-containing precursor, and exposure to an oxidant. Methods are suitable for depositing a magnesium oxide layer on a CoFeB layer to form part of a magnetic tunnel junction.
    Type: Grant
    Filed: November 6, 2015
    Date of Patent: June 5, 2018
    Assignee: LAM RESEARCH CORPORATION
    Inventors: Katie Lynn Nardi, Nerissa Sue Draeger
  • Patent number: 9991442
    Abstract: A method for manufacturing a magnetic memory device includes forming a magnetic tunnel junction layer that includes a first magnetic layer, a tunnel barrier layer, and a second magnetic layer sequentially stacked on a substrate. First line mask patterns are formed extending in a first direction and spaced apart from each other in a second direction crossing the first direction. The magnetic tunnel junction layer is etched by a first ion-beam etch process using the first line mask patterns as an etch mask to form preliminary magnetic tunnel junctions. Second line mask patterns are formed extending in the second direction and spaced apart from each other in the first direction. The preliminary magnetic tunnel junctions are etched by a second ion-beam process using the second line mask patterns as an etch mask to form magnetic tunnel junctions.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: June 5, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Jongchul Park
  • Patent number: 9984889
    Abstract: A method may include providing a surface feature on a substrate, the surface feature comprising a feature shape a feature location, and a dimension along a first direction within a substrate plane; depositing a layer comprising a layer material on the surface feature; and directing ions in an ion exposure at an angle of incidence toward the substrate, the angle of incidence forming a non-zero angle with respect to a perpendicular to the substrate plane, wherein the ion exposure comprises the ions and reactive neutral species, the ion exposure reactively etching the layer material, wherein the ions impact a first portion of the surface feature and do not impact a second portion of the surface feature, and wherein an altered surface feature is generated, the altered surface feature differing from the surface feature in at least one of: the dimension along the first direction, the feature shape, or the feature location.
    Type: Grant
    Filed: April 29, 2016
    Date of Patent: May 29, 2018
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Simon Ruffell, Huixiong Dai, Jun Lang, John Hautala
  • Patent number: 9985117
    Abstract: Described herein is a FinFET device in which epitaxial layers of semiconductor material are formed in the source/drain regions on dielectrically isolated fin portions. The fin portions are located within a dielectric layer that is deposited on a semiconductor substrate. Surfaces of the fin portions are oriented in the {100} lattice plane of the crystalline material of the fin portions, providing for good epitaxial growth. Further described are methods for forming the FinFET device.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: May 29, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Juntao Li
  • Patent number: 9947859
    Abstract: An electronic device that includes a first structure including a first magnetic layer, a second magnetic layer, and a tunnel barrier layer which is interposed between the first magnetic layer and the second magnetic layer; and a second structure disposed over the first structure, and including a magnetic correction layer for correcting a magnetic field of the first structure, wherein a width of a bottom surface of the second structure is larger than a width of a top surface of the first structure.
    Type: Grant
    Filed: December 3, 2014
    Date of Patent: April 17, 2018
    Assignees: SK Hynix Inc., TOSHIBA MEMORY CORPORATION
    Inventors: Cha-Deok Dong, Daisuke Watanabe, Kazuya Sawada, Young-Min Eeh, Koji Ueda, Toshihiko Nagase
  • Patent number: 9899535
    Abstract: To provide a transistor with stable electrical characteristics, a transistor with a low off-state current, a transistor with a high on-state current, a semiconductor device including the transistor, or a durable semiconductor device. The semiconductor device includes a first transistor using silicon, an aluminum oxide film over the first transistor, and a second transistor using an oxide semiconductor over the aluminum oxide film. The oxide semiconductor has a lower hydrogen concentration than silicon.
    Type: Grant
    Filed: October 13, 2016
    Date of Patent: February 20, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Tetsuhiro Tanaka, Hideomi Suzawa, Yasumasa Yamane, Yuhei Sato, Sachiaki Tezuka
  • Patent number: 9887350
    Abstract: A hard mask stack for etching a magnetic tunneling junction (MTJ) structure is described. An electrode layer is deposited on a stack of MTJ layers on a bottom electrode. A photoresist mask is formed on the electrode layer. The electrode layer is etched away where it is not covered by the photoresist mask to form a metal hard mask. The metal hard mask is passivated during or after etching to form a smooth hard mask profile. Thereafter, the photoresist mask is removed and the MTJ structure is etched using the metal hard mask wherein the metal hard mask remaining acts as a top electrode. The resulting MTJ device has smooth sidewalls and uniform device shape.
    Type: Grant
    Filed: May 31, 2015
    Date of Patent: February 6, 2018
    Assignee: Headway Technologies, Inc.
    Inventors: Dongna Shen, Yu-Jen Wang, Jesmin Haq