Having Magnetic Or Ferroelectric Component Patents (Class 438/3)
  • Patent number: 11189785
    Abstract: A method of manufacturing a magnetoresistive stack/structure comprising (a) etching through a second magnetic region to (i) provide sidewalls of the second magnetic region and (ii) expose a surface of a dielectric layer, (b) depositing a first encapsulation layer on the sidewalls of the second magnetic region and over a surface of the dielectric layer. (c) thereafter: (i) etching the first encapsulation layer which is disposed over the dielectric layer using a first etch process, and (ii) etching re-deposited material using a second etch process, wherein, after such etching, a portion of the first encapsulation layer remains on the sidewalls of the second magnetic region, (d) etching (i) through the dielectric layer to form a tunnel barrier and provide sidewalls thereof and (ii) etching the first magnetic region to provide sidewalls thereof, and (e) depositing a second encapsulation layer on the sidewalls of the tunnel barrier and first magnetic region.
    Type: Grant
    Filed: April 10, 2020
    Date of Patent: November 30, 2021
    Assignee: Everspin Technologies, Inc.
    Inventors: Sarin A. Deshpande, Kerry Joseph Nagel, Chaitanya Mudivarthi, Sanjeev Aggarwal
  • Patent number: 11183627
    Abstract: Some embodiments relate to a memory device. The memory device includes a memory cell overlying a substrate, the memory cell includes a data storage structure disposed between a lower electrode and an upper electrode. An upper interconnect wire overlying the upper electrode. A first inter-level dielectric (ILD) layer surrounding the memory cell and the upper interconnect wire. A second ILD layer overlying the first ILD layer and surrounding the upper interconnect wire. A sidewall spacer laterally surrounding the memory cell. The sidewall spacer has a first sidewall abutting the first ILD layer and a second sidewall abutting the second ILD layer.
    Type: Grant
    Filed: January 2, 2020
    Date of Patent: November 23, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Chau Chen, Cheng-Tai Hsiao, Cheng-Yuan Tsai, Hsun-Chung Kuang
  • Patent number: 11170834
    Abstract: A memory cell comprises a capacitor comprising a first capacitor electrode having laterally-spaced walls, a second capacitor electrode comprising a portion above the first capacitor electrode, and capacitor insulator material between the second capacitor electrode and the first capacitor electrode. The capacitor comprises an intrinsic current leakage path from one of the first and second capacitor electrodes to the other through the capacitor insulator material. A parallel current leakage path is between the second capacitor electrode and the first capacitor electrode. The parallel current leakage path is circuit-parallel with the intrinsic current leakage path, of lower total resistance than the intrinsic current leakage path, and comprises leaker material that is everywhere laterally-outward of laterally-innermost surfaces of the laterally-spaced walls of the first capacitor electrode. Other embodiments, including methods, are disclosed.
    Type: Grant
    Filed: July 10, 2019
    Date of Patent: November 9, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Michael Mutch, Ashonita A. Chavan, Sameer Chhajed, Beth R. Cook, Kamal Kumar Muthukrishnan, Durai Vishak Nirmal Ramaswamy, Lance Williamson
  • Patent number: 11171285
    Abstract: Provided is a non-ferromagnetic spacing composite layer, comprising first, second and third spacing layers stacked in sequence. The first and third spacing layers are each made of Re, Rh, Ir, W, Mo, Ta, or Nb, and the second spacing layer is made of Ru. The second spacing layer has a thickness of equal to or more than 0.18 nm, and the non-ferromagnetic spacing composite layer has a total thickness of 0.6 nm to 1 nm. Also, provided are a method of preparing the non-ferromagnetic spacing composite layer, a synthetic antiferromagnetic laminated structure, and an MRAM. The synthetic antiferromagnetic laminated structure can maintain a certain coupling strength and the RKKY indirect interaction after thermal treatment, thereby keeping the recording function of MRAM.
    Type: Grant
    Filed: December 4, 2020
    Date of Patent: November 9, 2021
    Assignee: SOLAR APPLIED MATERIALS TECHNOLOGY CORP.
    Inventors: Chih-Huang Lai, Chun-Liang Yang, Yi-Huan Chung, Wei-Chih Huang, Chih-Wen Tang, Hui-Wen Cheng
  • Patent number: 11164976
    Abstract: The disclosed technology generally relates to ferroelectric materials and semiconductor devices, and more particularly to semiconductor memory devices incorporating doped polar materials. In one aspect, a semiconductor device comprises a capacitor which in turn comprises a polar layer comprising a base polar material doped with a dopant. The base polar material includes one or more metal elements and one or both of oxygen or nitrogen. The dopant comprises a metal element that is different from the one or more metal elements and is present at a concentration such that a ferroelectric switching voltage of the capacitor is different from that of the capacitor having the base polar material without being doped with the dopant by more than about 100 mV. The capacitor stack additionally comprises first and second crystalline conductive oxide electrodes on opposing sides of the polar layer.
    Type: Grant
    Filed: April 7, 2020
    Date of Patent: November 2, 2021
    Assignee: Kepler Computing Inc.
    Inventors: Ramesh Ramamoorthy, Sasikanth Manipatruni, Gaurav Thareja
  • Patent number: 11164936
    Abstract: A first-layer insulating film having a barrier property against a determined element contained in a ferroelectric capacitor as well as an oxygen permeability, a hydrogen permeability, and a water permeability is formed over a surface of the ferroelectric capacitor formed over a substrate. After that, heat treatment is performed in an oxidizing atmosphere. After the heat treatment, a second insulating film having a hydrogen permeability and a water permeability lower than those of the first-layer insulating film respectively is formed over a surface of the first-layer insulating film in a non-reducing atmosphere. A third-layer insulating film is formed over a surface of the second-layer insulating film. By doing so, degradation of a ferroelectric film under and after the formation of a semiconductor device having the ferroelectric capacitor is suppressed and deterioration in the characteristics of the ferroelectric capacitor is suppressed.
    Type: Grant
    Filed: January 3, 2020
    Date of Patent: November 2, 2021
    Assignee: FUJITSU SEMICONDUCTOR MEMORY SOLUTION LIMITED
    Inventors: Youichi Okita, Wensheng Wang, Kazuaki Takai
  • Patent number: 11165017
    Abstract: A replacement bottom electrode structure process is provided in which a patterned stack containing a MTJ pillar and a top electrode structure is fabricated and passivated on a sacrificial dielectric material plug that is embedded in a dielectric capping layer. The sacrificial dielectric material plug is then removed and replaced with a bottom electrode structure. The replacement bottom electrode structure process of the present application allows the MTJ patterning to be misalignment tolerate and fully eliminates the potential yield loss from the bottom electrode structure.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: November 2, 2021
    Assignee: International Business Machines Corporation
    Inventors: Pouya Hashemi, Takashi Ando, Dimitri Houssameddine, Alexander Reznicek, Jingyun Zhang, Choonghyun Lee
  • Patent number: 11152563
    Abstract: A dielectric material structure is formed laterally adjacent to a bottom portion of a bottom electrode metal-containing portion that extends upward from an electrically conductive structure that is embedded in an interconnect dielectric material layer. The physically exposed top portion of the bottom electrode metal-containing portion is then trimmed to provide a bottom electrode of unitary construction (i.e., a single piece) that has a lower portion having a first diameter and an upper portion that has a second diameter that is greater than the first diameter. The presence of the dielectric material structure prevents tilting and/or bowing of the resultant bottom electrode. Thus, a stable bottom electrode is provided.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: October 19, 2021
    Assignee: International Business Machines Corporation
    Inventors: Bruce B. Doris, Eileen A. Galligan, Nathan P. Marchack, Pouya Hashemi
  • Patent number: 11145808
    Abstract: Embodiments of the disclosure provide methods and apparatus for fabricating magnetic tunnel junction (MTJ) structures on a substrate for MRAM applications. In one embodiment, a method for forming a magnetic tunnel junction (MTJ) device structure includes performing a patterning process by an ion beam etching process in a processing chamber to pattern a film stack disposed on a substrate, wherein the film stack comprises a reference layer, a tunneling barrier layer and a free layer disposed on the tunneling barrier, and determining an end point for the patterning process.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: October 12, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Jong Mun Kim, Minrui Yu, Chando Park, Mang-Mang Ling, Jaesoo Ahn, Chentsau Chris Ying, Srinivas D. Nemani, Mahendra Pakala, Ellie Y. Yieh
  • Patent number: 11139011
    Abstract: A method for forming a semiconductor structure is disclosed. A substrate having a logic device region and a memory device region is provided. A first dielectric layer is formed on the substrate. Plural memory stack structures are formed on the first dielectric layer on the memory device region. An insulating layer is formed and conformally covers the memory stack structures and the first dielectric layer. An etching back process is performed to remove a portion of the insulating layer without exposing any portion of the memory stack structures. After the etching back process, a second dielectric layer is formed on the insulating layer and completely fills the spaces between the memory stack structures.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: October 5, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Yu-Ping Wang, Chen-Yi Weng, Chin-Yang Hsieh, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, I-Ming Tseng, Jing-Yin Jhang, Chien-Ting Lin
  • Patent number: 11139202
    Abstract: Integrated chips and methods of forming the same include forming upper dummy lines over lower conductive lines. The lower conductive lines are recessed to form conductive vias between the lower conductive lines and the upper dummy lines. The upper dummy lines are replaced with upper conductive lines that contact the conductive vias.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: October 5, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chanro Park, Koichi Motoyama, Kenneth C. K. Cheng, Chih-Chao Yang
  • Patent number: 11139239
    Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) including an interconnect structure overlying a substrate. The interconnect structure has a plurality of metal layers overlying over the substrate. A first dielectric layer overlies an uppermost surface of the interconnect structure. The first dielectric layer has opposing sidewalls defining a trench. A first magnetic layer is disposed within the trench and conformally extends along the opposing sidewalls. Conductive wires are disposed within the trench and overlie the first magnetic layer. A second magnetic layer overlies the first magnetic layer and the conductive wires. The second magnetic layer laterally extends from over a first sidewall of the opposing sidewalls to a second sidewall of the opposing sidewalls.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: October 5, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Wen Hsu, Jiech-Fun Lu, Kai Tzeng, Wei-Li Huang
  • Patent number: 11133028
    Abstract: A magnetoresistance effect element has a first ferromagnetic metal layer, a second ferromagnetic metal layer, and a tunnel barrier layer that is sandwiched between the first and second ferromagnetic metal layers, the tunnel barrier layer is expressed by a chemical formula of AB2Ox, and has a spinel structure in which cations are arranged in a disordered manner, A represents a divalent cation that is either Mg or Zn, and B represents a trivalent cation that includes a plurality of elements selected from the group consisting of Al, Ga, and In.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: September 28, 2021
    Assignee: TDK CORPORATION
    Inventor: Tomoyuki Sasaki
  • Patent number: 11133460
    Abstract: Embodiments of the disclosure provide methods and apparatus for fabricating magnetic tunnel junction (MTJ) structures on a substrate in for spin-transfer-torque magnetoresistive random access memory (STT-MRAM) applications. In one example, a film stack utilized to form a magnetic tunnel junction structure on a substrate includes a pinned layer disposed on a substrate, wherein the pinned layer comprises multiple layers including at least one or more of a Co containing layer, Pt containing layer, Ta containing layer, an Ru containing layer, an optional structure decoupling layer disposed on the pinned magnetic layer, a magnetic reference layer disposed on the optional structure decoupling layer, a tunneling barrier layer disposed on the magnetic reference layer, a magnetic storage layer disposed on the tunneling barrier layer, and a capping layer disposed on the magnetic storage layer.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: September 28, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Lin Xue, Jaesoo Ahn, Mahendra Pakala, Chi Hong Ching, Rongjun Wang
  • Patent number: 11127788
    Abstract: A semiconductor device is provided. The semiconductor device has a semiconductor layer including a source/drain region, a first magnetic layer over the semiconductor layer, and a first dielectric layer over the source/drain region and adjacent the first magnetic layer. The semiconductor device has a metal structure extending through the first dielectric layer, a second magnetic layer over the metal structure, and a second dielectric layer over the first magnetic layer and adjacent the first dielectric layer.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: September 21, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Baohua Niu, Da-Shou Chen
  • Patent number: 11124746
    Abstract: The disclosure generally relates to a composition and process for cleaning residue and/or contaminants from microelectronic devices having said residue and contaminants thereon. The residue may include post-CMP, post-etch, and/or post-ash residue. The compositions and methods are particularly advantageous when cleaning a microelectronic surface comprising copper, low-k dielectric materials, and barrier materials comprising at least one of tantalum-containing material, cobalt-containing material, tantalum-containing, tungsten-containing, and ruthenium-containing material.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: September 21, 2021
    Assignee: ENTEGRIS, INC.
    Inventors: Daniela White, Michael White, Jun Liu, Elizabeth Thomas
  • Patent number: 11127420
    Abstract: Certain embodiments are directed to a spin torque oscillator (STO) device in a microwave assisted magnetic recording (MAMR) device. The magnetic recording head includes a seed layer, a spin polarization layer over the seed layer, a spacer layer over the spin polarization layer, and a field generation layer is over the spacer layer. In one embodiment, the seed layer comprises a tantalum alloy layer. In another embodiment, the seed layer comprises a template layer and a damping reduction layer over the template layer. In yet another embodiment, the seed layer comprises a texture reset layer, a template layer on the texture reset layer, and a damping reduction layer on the template layer.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: September 21, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: James Mac Freitag, Zheng Gao, Susumu Okamura, Brian York
  • Patent number: 11121266
    Abstract: The present invention relates to a voltage-controllable capacitor comprising a first electrode layer (4) composed of a non-ferroelectric material, said first electrode layer being applied on a substrate (6), a ferroelectric interlayer (3) having a thickness that is less than the thickness of the first electrode layer (4), and a second electrode layer (2) composed of a non-ferroelectric material. The ferroelectric interlayer (3) is arranged between the first electrode layer (4) and the second electrode layer (2).
    Type: Grant
    Filed: August 2, 2019
    Date of Patent: September 14, 2021
    Assignee: FRAUNHOFER-GESELLSCHAFT ZUR FOERDERUNG DER ANGEWANDTEN FORSCHUNG E.V.
    Inventors: Thomas Kaempfe, Patrick Polakowski, Konrad Seidel
  • Patent number: 11121307
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate; forming a first top electrode on the first MTJ and a second top electrode on the second MTJ; forming a cap layer on the first MTJ and the second MTJ; forming a passivation layer on the cap layer; removing part of the passivation layer to form a recess between the first MTJ and the second MTJ; forming an anti-reflective layer on the passivation layer and filling the recess; and removing the anti-reflective layer, the passivation layer, and the cap layer to form a first contact hole.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: September 14, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Wei Kuo, Chia-Chang Hsu, Yu-Tsung Lai, Jiunn-Hsiung Liao
  • Patent number: 11114606
    Abstract: A harden gap fill dielectric material that has improved chemical and physical properties is formed laterally adjacent to a multilayered magnetic tunnel junction (MTJ) pillar and a top electrode structure of a memory structure. The harden gap fill dielectric material can be formed by introducing, via ion implantation, a bond breaking additive into an as deposited gap fill dielectric material layer and thereafter curing the gap fill dielectric material layer containing the bond breaking additive. The curing includes UV curing alone, or UV curing in combination with laser annealing. The curing employed in the present application does not negatively impact the MTJ pillar or top electrode structure.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: September 7, 2021
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Devika Sil, Oleg Gluschenkov, Yasir Sulehria
  • Patent number: 11114613
    Abstract: The disclosed technology generally relates to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. Line stacks are formed, including a storage material line disposed over lower a conductive line. Upper conductive lines are formed over and crossing the line stacks, exposing portions of the line stacks between adjacent upper conductive lines. After forming the upper conductive lines, storage elements are formed at intersections between the lower conductive lines and the upper conductive lines by removing storage materials from exposed portions of the line stacks, such that each storage element is laterally surrounded by spaces. A continuous sealing material laterally surrounds each of the storage elements.
    Type: Grant
    Filed: May 4, 2020
    Date of Patent: September 7, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Fabio Pellizzer, Innocenzo Tortorelli, Andrea Ghetti
  • Patent number: 11107794
    Abstract: A multi-wafer stack structure and fabricating method thereof are disclosed. In the multi-wafer stack structure, the first interconnection layer is electrically connected to the second metal layer and the first metal layer via the first opening, the second interconnection layer is electrically connected to the first interconnection layer via the second openings, the third interconnection layer is electrically connected to the third metal layer via the third openings, and the second interconnection layer is in contact with the third interconnection layer, so that there is no need to reserve the wire pressure welding space between the wafers and a silicon substrate is eliminated, the overall device thickness of the multi-wafer stack package is reduced. Moreover, the design processing of the silicon substrate and a plurality of common pads on the silicon substrate is eliminated, thereby reducing the parasitic capacitance and power loss, and increasing the transmission speed.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: August 31, 2021
    Assignee: WUHAN XINXIN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Changlin Zhao, Tianjian Liu
  • Patent number: 11101365
    Abstract: Example methods for fabricating a semiconductor device and example semiconductor devices are disclosed. An example method may include forming a sacrificial gate structure on a substrate, and the sacrificial gate structure may include a first portion and a second portion. The method may further include, removing the first portion of the sacrificial gate structure and forming an oxide film by oxidizing an upper surface of the second portion of the sacrificial gate structure after removing the first portion of the sacrificial gate structure. The method may additionally include, forming a trench on the substrate by removing the oxide film and the second portion of the sacrificial gate structure; and forming a gate electrode that fills the trench.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: August 24, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young Cheon Jeong, YongKuk Jeong, Jin Hyuk Jeong, Tae Gyun Kim
  • Patent number: 11094882
    Abstract: A method of manufacturing a memory device includes forming a transistor on a substrate, forming a lower interlayer insulating layer covering the transistor, forming a hydrogen supply layer on the lower interlayer insulating layer, forming a hydrogen blocking layer on the hydrogen supply layer, annealing the transistor, the lower interlayer insulating layer, and the hydrogen supply layer, forming a memory cell on the hydrogen blocking layer after the annealing, and forming an upper interlayer insulating layer surrounding the memory cell and having a third average hydrogen concentration less than the second average hydrogen concentration.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: August 17, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung-hyun Cho, Song-yi Kim, Masayuki Terai
  • Patent number: 11088321
    Abstract: A via connection is provided through a dielectric layer to a bottom electrode. A MTJ stack is deposited on the dielectric layer and via connection. A top electrode is deposited on the MTJ stack. A selective hard mask and then a dielectric hard mask are deposited on the top electrode. The dielectric and selective hard masks are patterned and etched. The dielectric and selective hard masks and the top electrode are etched wherein the dielectric hard mask is removed. The top electrode is trimmed using IBE at an angle of 70 to 90 degrees. The selective hard mask, top electrode, and MTJ stack are etched to form a MTJ device wherein over etching into the dielectric layer surrounding the via connection is performed and re-deposition material is formed on sidewalls of the dielectric layer underlying the MTJ device and not on sidewalls of a barrier layer of the MTJ device.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: August 10, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi Yang, Dongna Shen, Yu-Jen Wang
  • Patent number: 11081642
    Abstract: A MTJ stack is deposited on a bottom electrode. A metal hard mask is deposited on the MTJ stack and a dielectric mask is deposited on the metal hard mask. A photoresist pattern is formed on the dielectric mask, having a critical dimension of more than about 65 nm. The dielectric and metal hard masks are etched wherein the photoresist pattern is removed. The dielectric and metal hard masks are trimmed to reduce their critical dimension to 10-60 nm and to reduce sidewall surface roughness. The dielectric and metal hard masks and the MTJ stack are etched wherein the dielectric mask is removed and a MTJ device is formed having a small critical dimension of 10-60 nm, and having further reduced sidewall surface roughness.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: August 3, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Dongna Shen, Yi Yang, Jesmin Haq, Yu-Jen Wang
  • Patent number: 11063207
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a substrate having a magnetic tunneling junction (MTJ) region and a logic region; forming a MTJ on the MTJ region; forming a top electrode on the MTJ; forming an inter-metal dielectric (IMD) layer around the MTJ; removing the IMD layer directly on the top electrode to form a recess; forming a first hard mask on the IMD layer and into the recess; removing the first hard mask and the IMD layer on the logic region to form a contact hole; and forming a metal layer in the recess and the contact hole to form a connecting structure on the top electrode and a metal interconnection on the logic region.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: July 13, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Po-Kai Hsu, Chen-Yi Weng, Jing-Yin Jhang, Yu-Ping Wang, Hung-Yueh Chen
  • Patent number: 11050012
    Abstract: In some embodiments, the present disclosure relates to a method for forming a microelectromechanical system (MEMS) device, including depositing a first electrode layer over a first piezoelectric layer. A hard mask layer is then deposited over the first electrode layer. A photoresist mask is formed on the hard mask layer with a first-electrode pattern. Using the photoresist mask, a first etch is performed into the hard mask layer to transfer the first-electrode pattern to the hard mask layer. The photoresist mask is then removed. A second etch is performed using the hard mask layer to transfer the first-electrode pattern to the first electrode layer, and the hard mask layer is removed.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: June 29, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Ren Wang, Hung-Hua Lin, Yuan-Chih Hsieh
  • Patent number: 11037873
    Abstract: A barrier or “crackstop” that is configured to conduct electrical signals. These configurations may form a wall around integrated, active circuitry of a semiconductor die. This wall may include a conductor that follows a three-dimensional pathway from one side to the other side of the wall. This pathway may have sections that overlap, or double-back, so that portions of the conductor overlap along their individual length. These sections prevent crack propagation internal to the wall.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: June 15, 2021
    Assignee: MARVELL GOVERNMENT SOLUTIONS, LLC.
    Inventors: Nicholas A. Polomoff, Igor Arsovski, Mark W. Kuemerle
  • Patent number: 11024537
    Abstract: Methods and apparatus for forming an interconnect, including: depositing a first barrier layer upon a top surface of a via and a top surface of a trench; filling the via with a first metal, wherein the first metal completely fills the via and forms a metal layer within the trench; etching the metal layer within the trench to expose dielectric sidewalls of the trench, a top surface of the via, and a dielectric bottom of the trench; depositing a second barrier layer upon the dielectric sidewalls, top surface of the via, and the dielectric bottom of the trench; and filling the trench with a second metal different than the first metal.
    Type: Grant
    Filed: October 10, 2019
    Date of Patent: June 1, 2021
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Roey Shaviv, Ismail Emesh, Xikun Wang
  • Patent number: 11018293
    Abstract: A magnetoresistance effect element has a first ferromagnetic metal layer, a second ferromagnetic metal layer, and a tunnel barrier layer that is sandwiched between the first and second ferromagnetic metal layers, and a tunnel barrier layer that is sandwiched between the first and second ferromagnetic metal layers, the tunnel barrier layer is expressed by a composition formula of AB2Ox (0<x?4), and has a spinel structure in which cations are arranged in a disordered manner, the tunnel barrier layer has a lattice-matched portion and a lattice-mismatched portion, A is a divalent cation of plural non-magnetic elements, B is an aluminum ion, and in the composition formula, the number of the divalent cation is smaller than half the number of the aluminum ion.
    Type: Grant
    Filed: January 10, 2020
    Date of Patent: May 25, 2021
    Assignee: TDK CORPORATION
    Inventor: Tomoyuki Sasaki
  • Patent number: 10991758
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a bottom electrode via (BEVA) in a dielectric layer, a recap layer on the BEVA, a bottom electrode on the recap layer, and a magnetic tunneling junction (MTJ) layer over the recap layer and vertically aligning with the BEVA. The BEVA includes a lining layer over a bottom and a sidewall of a trench of the BEVA and a copper layer over the lining layer, filling the trench of the BEVA. The copper layer has a dimpled structure with a top surface lower than a top surface of the dielectric layer. The recap layer overlaps a top surface of the lining layer, an entire top surface of the copper layer, and a portion of the dielectric stack adjacent to the lining layer.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: April 27, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Harry-Hak-Lay Chuang, Kuei-Hung Shen, Hsun-Chung Kuang, Cheng-Yuan Tsai, Ru-Liang Lee
  • Patent number: 10937950
    Abstract: The present disclosure provides a semiconductor structure including a first electrode via, a first electrode on the first electrode via, a magnetic tunneling junction (MTJ) over the first electrode, a second electrode over the MTJ, a first dielectric layer on a top surface of the first electrode via, a second dielectric layer over the first electrode, the MTJ, the second electrode, and the first dielectric layer. A sidewall of the MTJ is in contact with the second dielectric layer.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: March 2, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chern-Yow Hsu, Shih-Chang Liu
  • Patent number: 10937956
    Abstract: A magnetoresistive random access memory (MRAM) structure includes a bottom electrode structure. A magnetic tunnel junction (MTJ) element is over the bottom electrode structure. The MTJ element includes an anti-ferromagnetic material layer. A ferromagnetic pinned layer is over the anti-ferromagnetic material layer. A tunneling layer is over the ferromagnetic pinned layer. A ferromagnetic free layer is over the tunneling layer. The ferromagnetic free layer has a first portion and a demagnetized second portion. The MRAM also includes a top electrode structure over the first portion.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: March 2, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chern-Yow Hsu, Wei-Hang Huang, Shih-Chang Liu, Chia-Shiung Tsai
  • Patent number: 10937828
    Abstract: Fabricating a magnetoresistive random access memory (MRAM) device includes receiving a wafer structure having a first inter-layer dielectric (ILD) layer and a metal material disposed within the first ILD layer. A second ILD layer is deposited upon a top surface of the first ILD layer and the metal material. A trench is formed within the second ILD layer extending to the top surface of the metal material. A plurality of magnetic stack layers of a magnetic stack and an electrode layer are deposited within the trench. Portions of each of the magnetic stack layers of the magnetic stack and the electrode layer are removed to form a v-shaped magnetic tunnel junction (MTJ) in contact with the metal material.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: March 2, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Pouya Hashemi, Matthias Georg Gottwald, Alexander Reznicek, Chandrasekharan Kothandaraman
  • Patent number: 10923581
    Abstract: A method for manufacturing a semiconductor structure including forming a first type semiconductor layer. The method also includes forming a semiconductor interlayer over the first type semiconductor layer. The method further includes forming a second type semiconductor layer over the semiconductor interlayer. The method further includes etching the first type semiconductor layer, the semiconductor interlayer, and the second type semiconductor layer to form a fin structure. The method further includes oxidizing the semiconductor interlayer.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: February 16, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Gerben Doornbos, Peter Ramvall, Matthias Passlack, Carlos H. Diaz
  • Patent number: 10920179
    Abstract: A cleaning solution that is used, inter alia, for removal of residue of a photoresist pattern or etching residue, and has exceptional anticorrosion properties with respect to silicon nitride; and a method for cleaning a substrate using the cleaning solution. In a cleaning solution containing a hydrofluoric acid and a solvent, a polymer that includes units derived from a compound of a specific structure having a carboxylic acid amide bond (—CO—N<) and an unsaturated double bond is blended as an anticorrosive agent. Polyvinylpyrrolidone is preferred as the polymer used as the anticorrosive agent.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: February 16, 2021
    Assignee: Tokyo Ohka Kogyo Co., Ltd.
    Inventors: Tatsuo Goto, Kenji Seki
  • Patent number: 10908177
    Abstract: A magnetic sensor includes a first bridge circuit including a plurality of magnetic field sensor elements, each configured to generate a sensor signal in response to the magnetic field impinging thereon. The first bridge circuit is configured to generate a first differential signal based on sensor signals generated by the plurality of magnetic field sensor elements. The plurality of magnetic field sensor elements include a first, second, and third group of sensor elements. The first group is arranged at center region of the magnetic sensor, the second group is arranged at a first side region of the magnetic sensor and are displaced a first distance from the first group, and the third group is arranged at a second side region of the magnetic sensor, opposite to the first side region, and is displaced a second distance from the first group that is substantially equal to the first distance.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: February 2, 2021
    Inventors: Simon Hainz, Johannes Guettinger
  • Patent number: 10910260
    Abstract: A method for manufacturing a semiconductor device includes forming a structure protruding from a substrate, forming a dielectric layer covering the structure, forming a dummy layer covering the dielectric layer, and performing a planarization process to completely remove the dummy layer. A material of the dummy layer has a slower removal rate to the planarization process than a material of the dielectric layer.
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: February 2, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Chieh Huang, Chin-Wei Liang, Feng-Jia Shiu, Hsia-Wei Chen, Jieh-Jang Chen, Ching-Sen Kuo
  • Patent number: 10908318
    Abstract: We describe a luminescent device (120, 130) comprising a substrate (102) and a film comprising perovskite crystals (122, 132) deposited on the substrate, wherein the film comprising perovskite crystals is encapsulated with a layer (124, 134)) or within a matrix (124, 134) of an insulating oxide or an insulating nitride.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: February 2, 2021
    Assignees: CAMBRIDGE ENTERPRISE LIMITED, KING ABDULAZIZ CITY FOR SCIENCE & TECHNOLOGY
    Inventors: Richard Henry Friend, Guangru Li, Dawei Di, Reza Saberi Moghaddam, Zhi Kuang Tan
  • Patent number: 10886379
    Abstract: To provide a semiconductor device having improved reliability. The semiconductor device has, on a SOI substrate thereof having a semiconductor substrate, an insulating layer, and a semiconductor layer, a gate insulating film having an insulating film and a high dielectric constant film. The high dielectric constant film has a higher dielectric constant than a silicon oxide film and includes a first metal and a second metal. In the high dielectric constant film, the ratio of the number of atoms of the first metal to the total number of atoms of the first metal and the second metal is equal to or more than 75%, and less than 100%.
    Type: Grant
    Filed: August 4, 2018
    Date of Patent: January 5, 2021
    Assignee: Renesas Electronics Corporation
    Inventor: Tetsuya Yoshida
  • Patent number: 10879455
    Abstract: Methods of fabricating MRAM devices are provided. The method includes forming an etch stop layer over a substrate, and depositing a bottom electrode layer on the etch stop layer. The method also includes patterning the bottom electrode layer to form a bottom electrode. The method further includes depositing a magnetic tunnel junction (MTJ) layer on the bottom electrode, and depositing a top electrode layer on the MTJ layer. In addition, the method includes patterning the top electrode layer to form a top electrode, and patterning the MTJ layer to form an MTJ structure.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: December 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsi-Wen Tien, Wei-Hao Liao, Pin-Ren Dai, Chih-Wei Lu, Chung-Ju Lee
  • Patent number: 10879064
    Abstract: Provided is a method for manufacturing a semiconductor device, the semiconductor device including a substrate, and an oxide semiconductor TFT that is supported by the substrate and includes an oxide semiconductor film as an active layer. The method includes: (A) preparing MO gas containing a first organometallic compound that contains In and a second organometallic compound that contains Zn; and (B) supplying gas containing the MO gas and oxygen to the substrate placed in a chamber under a condition in which the substrate is heated to 500° C. or lower, and growing an oxide semiconductor film containing In and Zn on the substrate using an MOCVD method. Step (B) is performed under a condition in which plasma is formed in the chamber.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: December 29, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Shinji Nakajima, Hirohiko Nishiki, Hirohide Mimura, Yuhichi Saitoh, Yujiro Takeda, Shogo Murashige, Izumi Ishida, Tohru Okabe
  • Patent number: 10868244
    Abstract: A method for etching a magnetic tunneling junction (MTJ) structure is described. A stack of MTJ layers on a bottom electrode on a wafer is provided. A metal hard mask layer is provided on the MTJ stack. A stack of multiple dielectric hard masks is formed on the metal hard mask wherein each successive dielectric hard mask has etch selectivity with respect to its underlying and overlying layers. The dielectric hard mask layers are etched in turn selectively with respect to their underlying and overlying layers wherein each successive pattern size is smaller than the preceding pattern size. The MTJ stack is etched selectively with respect to the bottommost combination dielectric and metal hard mask pattern to form a MTJ device having a MTJ pattern size smaller than a bottommost pattern size.
    Type: Grant
    Filed: October 14, 2019
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi Yang, Yu-Jen Wang, Jesmin Haq, Tom Zhong
  • Patent number: 10868236
    Abstract: A method for forming self aligned magnetic memory element pillars for Magnetic Random Access Memory. The method allows the magnetic memory element pillars to be arranged in staggered rows of memory elements at a pitch that is smaller than what is possible using photolithography alone. The method involves forming a spacer mask in the form of an array of connected rings arranged in a square pattern of non-staggered rows. A sacrificial mask material is deposited over the spacer mask and the spacer mask is then removed, leaving sacrificial mask material in the holes at the center of the rings and also in the spaces between the rings. A reactive ion processes is then performed to transfer the pattern of the sacrificial mask onto underlying hard mask layers. A material removal process can then be performed to define a plurality of memory element pillars.
    Type: Grant
    Filed: December 30, 2017
    Date of Patent: December 15, 2020
    Assignee: SPIN MEMORY, INC.
    Inventors: Prachi Shrivastava, Yuan-Tung Chin
  • Patent number: 10840437
    Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a magnetic tunnel junction (MTJ) region and an edge region, forming an first inter-metal dielectric (IMD) layer on the substrate, and then forming a first MTJ and a second MTJ on the first IMD layer, in which the first MTJ is disposed on the MTJ region while the second MTJ is disposed on the edge region. Next, a second IMD layer is formed on the first MTJ and the second MTJ.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: November 17, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Wen Hung, Yu-Ping Wang
  • Patent number: 10833250
    Abstract: In a method of manufacturing an MRAM device, a memory unit including a lower electrode, an MTJ structure and an upper electrode sequentially stacked is formed on a substrate. A protective layer structure including a capping layer, a sacrificial layer and an etch stop layer sequentially stacked is formed on the substrate to cover the memory unit. An insulating interlayer is formed on the protective layer structure. The insulating interlayer is formed to form an opening exposing the protective layer structure. The exposed protective layer structure is partially removed to expose the upper electrode. A wiring is formed on the exposed upper electrode to fill the opening.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: November 10, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Hoon Bak, Myoung-Su Son, Jae-Chul Shim, Gwan-Hyeob Koh, Yoon-Jong Song
  • Patent number: 10833256
    Abstract: A magnetic tunnel junction element includes, in a following stack order, an underlayer formed of a metal material, a fixed layer formed of a ferromagnetic body, a magnetic coupling layer formed of a nonmagnetic body, a reference layer formed of a ferromagnetic body, a barrier layer formed of a nonmagnetic body, and a recording layer formed of a ferromagnetic body, or alternatively, the magnetic tunnel junction element includes, in a following stack order, a recording layer formed of a ferromagnetic body, a barrier layer formed of a nonmagnetic body, a reference layer formed of a ferromagnetic body, a magnetic coupling layer formed of a nonmagnetic body, an underlayer formed of a metal material, and a fixed layer formed of a ferromagnetic body, wherein the fixed layer is formed and stacked after performing plasma treatment to a surface of the underlayer having been formed.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: November 10, 2020
    Assignee: TOHOKU UNIVERSITY
    Inventors: Hiroaki Honjo, Tetsuo Endoh, Shoji Ikeda, Hideo Sato, Hideo Ohno
  • Patent number: 10825889
    Abstract: A semiconductor device including a switching element on a substrate, a pad isolation layer on the switching element, a conductive pad passing through the pad isolation layer and connected to the switching element, an insulating pattern on the pad isolation layer and having a height greater than a horizontal width, a lower electrode on side surfaces of the insulating pattern on side surfaces of the insulating pattern and in contact with the conductive pad, a capacitor dielectric layer on the lower electrode and having a monocrystalline dielectric layer and a polycrystalline dielectric layer, the monocrystalline dielectric layer being relatively close to side surfaces of the insulating pattern compared to the polycrystalline dielectric layer an upper electrode on the capacitor dielectric layer may be provided.
    Type: Grant
    Filed: June 20, 2018
    Date of Patent: November 3, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang Yeol Kang, Kyu Ho Cho, Han Jin Lim, Cheol Seong Hwang
  • Patent number: 10804214
    Abstract: Integrated circuit structures configured with low loss transmission lines are disclosed. The structures are implemented with group III-nitride (III-N) semiconductor materials, and are well-suited for use in radio frequency (RF) applications where high frequency signal loss is a concern. The III-N materials are effectively used as a conductive ground shield between a transmission line and the underlying substrate, so as to significantly suppress electromagnetic field penetration at the substrate. In an embodiment, a group III-N polarization layer is provided over a gallium nitride layer, and an n-type doped layer of indium gallium nitride (InzGa1-zN) is provided over or adjacent to the polarization layer, wherein z is in the range of 0.0 to 1.0. In addition to providing transmission line ground shielding in some locations, the III-N materials can also be used to form one or more active and/or passive components (e.g., power amplifier, RF switch, RF filter, RF diode, etc).
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: October 13, 2020
    Assignee: Intel Corporation
    Inventors: Han Wui Then, Sansaptak Dasgupta, Marko Radosavljevic