Having Magnetic Or Ferroelectric Component Patents (Class 438/3)
  • Patent number: 11935846
    Abstract: An electronic device includes a substrate, a first insulating film on the substrate, a second insulating film on the first insulating film, first and second coils respectively in the first and second insulating films, first and second terminals, and first and second connection conductors. The first and second insulating films contact each other so that the first and second coils are magnetically coupled. The first insulating film includes a first non-contact portion not contacting the second insulating film. One of the first and second insulating films includes a second non-contact portion not contacting the first or second insulating film. The first terminal is provided on the first non-contact portion and electrically connected to the first coil. The second terminal is provided on the second non-contact portion and electrically connected to the second coil. The first and second connection conductors are connected to the first and second terminals, respectively.
    Type: Grant
    Filed: May 1, 2023
    Date of Patent: March 19, 2024
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Yoichiro Kurita, Takanobu Kamakura, Masayuki Sugiura, Yoshiaki Aizawa
  • Patent number: 11901177
    Abstract: A perovskite material that has a perovskite crystal lattice having a formula of CxMyXz, and alkyl polyammonium cations disposed within or at a surface of the perovskite crystal lattice; wherein x, y, and z, are real numbers; C comprises one or more cations selected from the group consisting of Group 1 metals, Group 2 metals, ammonium, formamidinium, guanidinium, and ethene tetramine; M comprises one or more metals each selected from the group consisting of Be, Mg, Ca, Sr, Ba, Fe, Cd, Co, Ni, Cu, Ag, Au, Hg, Sn, Ge, Ga, Pb, In, Tl, Sb, Bi, Ti, Zn, Cd, Hg, and Zr, and combinations thereof and X comprises one or more anions each selected from the group consisting of halides, pseudohalides, chalcogenides, and combinations thereof.
    Type: Grant
    Filed: January 23, 2023
    Date of Patent: February 13, 2024
    Assignee: CubicPV Inc.
    Inventors: Michael D. Irwin, Michael Holland, Nicholas Anderson
  • Patent number: 11856866
    Abstract: A device includes a semiconductor substrate, a bottom conductive line, a bottom electrode, a magnetic tunneling junction (MTJ), and a residue. The bottom conductive line is over the semiconductor substrate. The bottom electrode is over the bottom conductive line. The MTJ is over the bottom electrode. The residue of the MTJ is on the sidewall of the bottom electrode and is spaced apart from the bottom conductive line.
    Type: Grant
    Filed: May 9, 2022
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsi-Wen Tien, Wei-Hao Liao, Pin-Ren Dai, Chih-Wei Lu, Chung-Ju Lee
  • Patent number: 11848366
    Abstract: Provided are an electronic device including a dielectric layer having an adjusted crystal orientation and a method of manufacturing the electronic device. The electronic device includes a seed layer provided on a substrate and a dielectric layer provided on the seed layer. The seed layer includes crystal grains having aligned crystal orientations. The dielectric layer includes crystal grains having crystal orientations aligned in the same direction as the crystal orientations of the seed layer.
    Type: Grant
    Filed: September 7, 2021
    Date of Patent: December 19, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Taehwan Moon, Eunha Lee, Junghwa Kim, Hyangsook Lee, Sanghyun Jo, Jinseong Heo
  • Patent number: 11844285
    Abstract: A memory cell structure including a dielectric cap layer disposed over a substrate and a first dielectric layer disposed over the dielectric cap layer. The memory cell structure may further include a buffer layer disposed over the first dielectric layer, a connection via structure embedded in the buffer layer, the first dielectric layer, and the dielectric cap layer. The memory cell structure may further include may further include a bottom electrode disposed on the connection via structure and the buffer layer, and a magnetic tunnel junction (MTJ) memory cell including one or more MTJ layers disposed on the bottom electrode.
    Type: Grant
    Filed: October 19, 2020
    Date of Patent: December 12, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventor: Chern-Yow Hsu
  • Patent number: 11839086
    Abstract: Thin-film Ferroelectric field-effect transistor (FeFET) may be organized as 3-dimensional NOR memory string arrays. Each 3-dimensional NOR memory string array includes a row of active stack each including a predetermined number of active strips each provided one on top of another and each being spaced apart from another by an isolation layer. Each active strip may include a shared source layer and a shared drain layer shared by the FeFETs provided along the active strip. Data storage in the active strip is provided by ferroelectric elements that can individually electrically set into one of two polarization states. FeFETs on separate active strips may be configured for read, programming or erase operations in parallel.
    Type: Grant
    Filed: July 13, 2022
    Date of Patent: December 5, 2023
    Assignee: SUNRISE MEMORY CORPORATION
    Inventors: Christopher J. Petti, Vinod Purayath, George Samachisa, Wu-Yi Henry Chien, Eli Harari
  • Patent number: 11830818
    Abstract: An apparatus includes a first metal layer, a second metal layer and a dielectric material. The first metal layer has a first thickness and a second thickness less than the first thickness, and the first metal layer comprises a first interconnect having a first thickness. The dielectric material extends between the first and second metal layers and directly contacts the first and second metal layers. The dielectric material includes a via that extends through the dielectric material. A metal material of the via directly contacts the first interconnect and the second metal layer.
    Type: Grant
    Filed: February 1, 2022
    Date of Patent: November 28, 2023
    Assignee: Intel Corporation
    Inventors: Kinyip Phoa, Jui-Yen Lin, Nidhi Nidhi, Chia-Hong Jan
  • Patent number: 11810816
    Abstract: A semiconductor structure is provided. The semiconductor structure include a substrate and a first dielectric layer having at least one via over the substrate. The first dielectric layer includes a first portion having a first thickness and a second portion having a second thickness greater than the first thickness. The semiconductor structure further includes a second dielectric layer containing at least one first conductive line overlying the first portion of the first dielectric layer and at least one second conductive line overlying the second portion of the first dielectric layer. The at least one first conductive line includes a first conductive portion and a conductive cap, and the at least one second conductive line including a second conductive portion having a top surface coplanar with a top surface of the conductive cap.
    Type: Grant
    Filed: May 13, 2022
    Date of Patent: November 7, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Kang Fu, Ming-Han Lee
  • Patent number: 11778917
    Abstract: A method for fabricating semiconductor device includes the steps of forming a magnetic tunneling junction (MTJ) stack on a substrate, performing an etching process to remove the MTJ stack for forming a MTJ, performing a deposition process to form a polymer on a sidewall of the MTJ, and removing the polymer to form a rough surface on the sidewall of the MTJ. Preferably, the MTJ could include a pinned layer on the substrate, a barrier layer on the pinned layer, and a free layer on the barrier layer, in which the rough surface could appear on sidewall of the pinned layer, sidewall of the barrier layer, and/or sidewall of the free layer.
    Type: Grant
    Filed: August 4, 2020
    Date of Patent: October 3, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Wei Liu, Jia-Feng Fang, Chun-Hsien Lin
  • Patent number: 11758825
    Abstract: A magnetoresistive random access memory (MRAM) device and a method of manufacturing the same, the device including a substrate; a memory unit including a lower electrode, a magnetic tunnel junction (MTJ) structure, and an upper electrode sequentially stacked on the substrate; a passivation pattern on a sidewall of the memory unit; a via on the memory unit and contacting the upper electrode; and a wiring on the via and contacting the via, wherein a center portion of the upper electrode protrudes from a remaining portion of the upper electrode in a vertical direction substantially perpendicular to an upper surface of the substrate.
    Type: Grant
    Filed: January 3, 2022
    Date of Patent: September 12, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Baeseong Kwon
  • Patent number: 11705433
    Abstract: A semiconductor device includes a first semiconductor chip, an adhesive layer that is formed on the first semiconductor chip, and a second semiconductor chip that is arranged on the first semiconductor chip via the adhesive layer. The first semiconductor chip has a first semiconductor substrate and a first wiring layer. The first wiring layer has a first inductor and a first electrode pad. The first wiring layer is formed on the first semiconductor substrate. The second semiconductor chip has a second wiring layer and a second semiconductor substrate. The second wiring layer is formed on the first wiring layer via the adhesive layer. The second semiconductor substrate is formed on the second wiring layer, and has a first opening. In a plan view, the first electrode pad is formed so as not to overlap with the second semiconductor chip, and a second electrode pad overlaps with the first opening.
    Type: Grant
    Filed: July 20, 2021
    Date of Patent: July 18, 2023
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Yasutaka Nakashiba
  • Patent number: 11673334
    Abstract: A temperature controlled dispensing tool includes a mount and a temperature controlled module coupled to the mount. The temperature controlled module may include a barrel housing, a barrel insert, one or more heating element, one or more cooling element, one or more temperature sensors, and a control unit. The barrel insert is removably insertable into the barrel housing and configured to receive a material barrel. The one or more heating elements and the one or more cooling elements are in thermal communication with the barrel insert. The control unit is configured to determine a temperature of the temperature controlled module based on the signal of the one or more temperature sensors, and selectively operate the one or more heating elements and the one or more cooling elements thereby controlling a temperature of the temperature controlled module.
    Type: Grant
    Filed: June 19, 2020
    Date of Patent: June 13, 2023
    Assignee: Advanced Solutions Life Sciences, LLC
    Inventors: Scott Douglas Cambron, Dakota Waldecker
  • Patent number: 11670537
    Abstract: A method of manufacturing a semiconductor device, which has buried gate electrodes, includes: forming a plurality of gate trenches in a substrate having a plurality of active regions defined by a device isolation film, the plurality of gate trenches crossing the plurality of active regions and extending parallel to each other in a first horizontal direction; selectively forming a first gate insulating layer on an exposed surface of the substrate; forming a second gate insulating layer on exposed surfaces of both the first gate insulating layer and the device isolation film; and forming a plurality of gate insulating layers by partially removing the first gate insulating layer and the second gate insulating layer, and forming a plurality of buried gate electrodes.
    Type: Grant
    Filed: February 4, 2021
    Date of Patent: June 6, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Byung-jae Kang, Yun-jung Kim, Se-min Yang, Ki-bum Lee
  • Patent number: 11659770
    Abstract: In a method of manufacturing an MRAM device, first and second lower electrodes may be formed on first and second regions, respectively, of a substrate. First and second MTJ structures having different switching current densities from each other may be formed on the first and second lower electrodes, respectively. First and second upper electrodes may be formed on the first and second MTJ structures, respectively.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: May 23, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dae-Shik Kim, Jeong-Heon Park, Gwan-Hyeob Koh
  • Patent number: 11631802
    Abstract: A plurality of conductive via connections are fabricated on a substrate located at positions where MTJ devices are to be fabricated, wherein a width of each of the conductive via connections is smaller than or equivalent to a width of the MTJ devices. The conductive via connections are surrounded with a dielectric layer having a height sufficient to ensure that at the end of a main MTJ etch, an etch front remains in the dielectric layer surrounding the conductive via connections. Thereafter, a MTJ film stack is deposited on the plurality of conductive via connections surrounded by the dielectric layer. The MTJ film stack is etched using an ion beam etch process (IBE), etching through the MTJ film stack and into the dielectric layer surrounding the conductive via connections to form the MTJ devices wherein by etching into the dielectric layer, re-deposition on sidewalls of the MTJ devices is insulating.
    Type: Grant
    Filed: November 7, 2019
    Date of Patent: April 18, 2023
    Assignee: Headway Technologies, Inc.
    Inventors: Vignesh Sundar, Yi Yang, Dongna Shen, Zhongjian Teng, Jesmin Haq, Sahil Patel, Yu-Jen Wang, Tom Zhong
  • Patent number: 11621364
    Abstract: An isolation system and isolation device are disclosed. An illustrative isolation device is disclosed to include a transmitter circuit, a detector circuit, a first wire bond, and a second wire bond. The detector circuit is configured to generate a first current in accordance with a first signal. The first wire bond is configured to receive the first current from the transmitter circuit to generate a magnetic flux. The second wire bond is configured to receive the magnetic flux. An induced current in the second wire bond is then detected in the detector circuit. The detector circuit is configured to generate a reproduced first signal, as an output of the detector circuit.
    Type: Grant
    Filed: July 22, 2020
    Date of Patent: April 4, 2023
    Assignee: MPICS INNOVATIONS PTE. LTD
    Inventors: Kok Keong Richard Lum, Hong Sia Tan
  • Patent number: 11615981
    Abstract: According to one embodiment, an isolator includes first and second conductive members, and first second, and third insulating members. The first conductive member includes first, second, and third partial regions. The third partial region is between the first and second partial regions. The second conductive member is electrically connected to the first conductive member. The second conductive member includes fourth and fifth partial regions. The fourth partial region is between the third and fifth partial regions. The first insulating member includes first and second insulating regions. The fifth partial region is between the first and second insulating regions. The second insulating member includes third and fourth insulating regions. The fourth partial region is between the third and fourth insulating regions. The third insulating member includes first and second portions.
    Type: Grant
    Filed: March 4, 2021
    Date of Patent: March 28, 2023
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Tatsuhiro Oda, Tatsuya Ohguro
  • Patent number: 11581315
    Abstract: Self-aligned gate edge trigate and finFET devices and methods of fabricating self-aligned gate edge trigate and finFET devices are described. In an example, a semiconductor structure includes a plurality of semiconductor fins disposed above a substrate and protruding through an uppermost surface of a trench isolation region. A gate structure is disposed over the plurality of semiconductor fins. The gate structure defines a channel region in each of the plurality of semiconductor fins. Source and drain regions are on opposing ends of the channel regions of each of the plurality of semiconductor fins, at opposing sides of the gate structure. The semiconductor structure also includes a plurality of gate edge isolation structures. Individual ones of the plurality of gate edge isolation structures alternate with individual ones of the plurality of semiconductor fins.
    Type: Grant
    Filed: April 27, 2021
    Date of Patent: February 14, 2023
    Assignee: Intel Corporation
    Inventors: Szuya S. Liao, Biswajeet Guha, Tahir Ghani, Christopher N. Kenyon, Leonard P. Guler
  • Patent number: 11541597
    Abstract: A 3D printing tool and assembly for dispensing multiple materials includes a barrel holder assembly having at least two barrel orifices extending from a top end of the barrel holder assembly through to a bottom end of the barrel holder assembly, where at least one of the at least two barrel orifices is oriented at an angle from the vertical. A method for operating the 3D printing tool includes positioning a first material distribution barrel within a first barrel orifice, where a first barrel tip is disposed at a first end of the first material distribution barrel. The method further includes dispensing building material from the first material distribution barrel when the first material distribution barrel is substantially vertically oriented and a second material distribution barrel is oriented at an angle from the vertical.
    Type: Grant
    Filed: June 19, 2020
    Date of Patent: January 3, 2023
    Assignee: Advanced Solutions Life Sciences, LLC
    Inventors: Scott Douglas Cambron, Kyle Eli
  • Patent number: 11532435
    Abstract: A thin film capacitor for which electrode conductivity is high and electrode irregularities are unlikely to be generate even if the capacitor if heated up to 700° C. This thin film capacitor has a first electrode, a dielectric layer, and a second electrode. The dielectric layer contains an ABO2N-type oxynitride. The nitrogen concentration of the part of the dielectric layer that contacts the first electrode is no more than half the nitrogen concentration of the center part of the dielectric layer.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: December 20, 2022
    Assignee: TDK CORPORATION
    Inventors: Kumiko Yamazaki, Takeshi Shibahara, Junichi Yamazaki
  • Patent number: 11522013
    Abstract: A hybrid random access memory for a system-on-chip (SOC), including a semiconductor substrate with a MRAM region and a ReRAM region, a first dielectric layer on the semiconductor substrate, multiple ReRAM cells in the first dielectric layer on the ReRAM region, a second dielectric layer above the first dielectric layer, and multiple MRAM cells in the second dielectric layer on the MRAM region.
    Type: Grant
    Filed: September 27, 2020
    Date of Patent: December 6, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Po-Kai Hsu, Hui-Lin Wang, Ching-Hua Hsu, Yi-Yu Lin, Ju-Chun Fan, Hung-Yueh Chen
  • Patent number: 11522131
    Abstract: An illustrative device disclosed herein includes a bottom electrode, a conformal switching layer positioned above the bottom electrode and a top electrode positioned above the conformal switching layer. The top electrode includes a conformal layer of conductive material positioned above the conformal switching layer and a conductive material positioned above the conformal layer of conductive material.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: December 6, 2022
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE LTD
    Inventors: Curtis Chun-I Hsieh, Wanbing Yi, Benfu Lin, Cing Gie Lim, Wei-Hui Hsu, Juan Boon Tan
  • Patent number: 11502248
    Abstract: A ferroelectric component includes a first electrode, a tunnel barrier layer disposed on the first electrode to include a ferroelectric material, a tunneling control layer disposed on the tunnel barrier layer to control a tunneling width of electric charges passing through the tunnel barrier layer, and a second electrode disposed on the tunneling control layer.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: November 15, 2022
    Assignee: SK hynix Inc.
    Inventors: Jae Gil Lee, Hyangkeun Yoo, Jae Hyun Han
  • Patent number: 11502247
    Abstract: A method of manufacturing a magnetoresistive device may comprise forming a first magnetic region, an intermediate region, and a second magnetic region of a magnetoresistive stack above a via; removing at least a portion of the second magnetic region using a first etch; removing at least a portion of the intermediate region and at least a portion of the first magnetic region using a second etch; removing at least a portion of material redeposited on the magnetoresistive stack using a third etch; and rendering at least a portion of the redeposited material remaining on the magnetoresistive stack electrically non-conductive.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: November 15, 2022
    Assignee: Everspin Technologies, Inc.
    Inventors: Sanjeev Aggarwal, Shimon, Kerry Joseph Nagel
  • Patent number: 11482668
    Abstract: In some embodiments, the present disclosure relates to method of forming an integrated chip. The method includes forming a bottom electrode structure over one or more interconnect layers disposed within one or more stacked inter-level dielectric (ILD) layers over a substrate. The bottom electrode structure has an upper surface having a noble metal. A diffusion barrier film is formed over the bottom electrode structure. A data storage film is formed onto the diffusion barrier film, and a top electrode structure is over the data storage film. The top electrode structure, the data storage film, the diffusion barrier film, and the bottom electrode structure are patterned to define a memory device.
    Type: Grant
    Filed: January 6, 2021
    Date of Patent: October 25, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hai-Dang Trinh, Chii-Ming Wu, Hsing-Lien Lin, Fa-Shen Jiang
  • Patent number: 11475932
    Abstract: A storage element includes a layer structure including a storage layer having a direction of magnetization which changes according to information, a magnetization fixed layer having a fixed direction of magnetization, and an intermediate layer disposed therebetween, which intermediate layer contains a nonmagnetic material. The magnetization fixed layer has at least two ferromagnetic layers having a direction of magnetization tilted from a direction perpendicular to a film surface, which are laminated and magnetically coupled interposing a coupling layer therebetween. This configuration may effectively prevent divergence of magnetization reversal time due to directions of magnetization of the storage layer and the magnetization fixed layer being substantially parallel or antiparallel, reduce write errors, and enable writing operation in a short time.
    Type: Grant
    Filed: November 5, 2020
    Date of Patent: October 18, 2022
    Assignee: Sony Group Corporation
    Inventors: Yutaka Higo, Masanori Hosomi, Hiroyuki Ohmori, Kazuhiro Bessho, Tetsuya Asayama, Kazutaka Yamane, Hiroyuki Uchida
  • Patent number: 11456410
    Abstract: A magnetic memory device comprises a cylindrical core and a plurality of layers surrounding the core. The plurality of layers include a metallic buffer layer, a ferromagnetic storage layer, a barrier layer, and a ferromagnetic reference layer. The cylindrical core, the metallic buffer layer, the ferromagnetic storage layer, the barrier layer, and the ferromagnetic reference layer collectively form a magnetic tunnel junction. A magnetization of the ferromagnetic layer storage parallels an interface between the metallic buffer layer and ferromagnetic storage layer.
    Type: Grant
    Filed: June 4, 2020
    Date of Patent: September 27, 2022
    Assignee: Integrated Silicon Solution, (Cayman) Inc.
    Inventors: Marcin Gajek, Michail Tzoufras
  • Patent number: 11444162
    Abstract: A method includes performing a first etching process on a backside of a substrate to expose a dummy contact structure, performing a first deposition process to deposit a first dielectric layer around the dummy contract structure, performing a second deposition process to deposit an oxide layer on the first dielectric layer, removing the dummy contract structure to form a trench, depositing a sacrificial layer on sidewalls of the trench, depositing a second dielectric layer on the sacrificial layer, filling the trench with a conductive material, and removing the sacrificial layer to form an air spacer between the first dielectric layer and the second dielectric layer.
    Type: Grant
    Filed: January 27, 2021
    Date of Patent: September 13, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Ming Lee, Wei-Yang Lee
  • Patent number: 11443879
    Abstract: An integrated magnetic device has a magnetic core which includes layers of the magnetic material located in a trench in a dielectric layer. The magnetic material layers are flat and parallel to a bottom of the trench, and do not extend upward along sides of the trench. The integrated magnetic device is formed by forming layers of the magnetic material over the dielectric layer and extending into the trench. A protective layer is formed over the magnetic material layers. The magnetic material layers are removed from over the dielectric layer, leaving the magnetic material layers and a portion of the protective layer in the trench. The magnetic material layers along sides of the trench are subsequently removed. The magnetic material layers along the bottom of the trench provide the magnetic core.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: September 13, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Fuchao Wang, Yousong Zhang, Neal Thomas Murphy, Brian Zinn, Jonathan P. Davis
  • Patent number: 11430956
    Abstract: The present disclosure relates to a resistive random access memory (RRAM) device architecture, that includes a thin single layer of a conductive etch-stop layer between a lower metal interconnect and a bottom electrode of an RRAM cell. The conductive etch-stop layer provides simplicity in structure and the etch-selectivity of this layer provides protection to the underlying layers. The conductive etch stop layer can be etched using a dry or wet etch to land on the lower metal interconnect. In instances where the lower metal interconnect is copper, etching the conductive etch stop layer to expose the copper does not produce as much non-volatile copper etching by-products as in traditional methods. Compared to traditional methods, some embodiments of the disclosed techniques reduce the number of mask step and also reduce chemical mechanical polishing during the formation of the bottom electrode.
    Type: Grant
    Filed: September 21, 2019
    Date of Patent: August 30, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming Chyi Liu, Yuan-Tai Tseng, Chern-Yow Hsu, Shih-Chang Liu, Chia-Shiung Tsai
  • Patent number: 11424318
    Abstract: A method for fabricating a capacitor device includes providing a substrate; forming a first-layer electrode on the substrate; and forming a conductive layer on the first-layer electrode. The roughness of the first-layer electrode is a first roughness, the roughness of the conductive layer is a second roughness, and the second roughness is smaller than the first roughness. The method further includes forming a dielectric layer on the conductive layer; and forming a second-layer electrode on the dielectric layer. According to the disclosed method and capacitor device, by forming the conductive layer on the first-layer electrode, the roughness of the bottom electrode of the capacitor device is reduced, which effectively reduces the presence of protrusions on the surface of the bottom electrode. Therefore, the breakdown electric voltage of the capacitor device may be improved, and leakage current may be avoided. As such, the reliability of the capacitor device may be improved.
    Type: Grant
    Filed: August 12, 2019
    Date of Patent: August 23, 2022
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Lianfeng Hu, Youcun Hu, Ming Yang, Duohui Bei, Baibing Ni
  • Patent number: 11417517
    Abstract: A method of forming a high-K dielectric cap layer on a semiconductor structure formed on a substrate includes depositing the high-K dielectric cap layer on the semiconductor structure, depositing a sacrificial silicon cap layer on the high-K dielectric cap layer, performing a post cap anneal process to harden and densify the as-deposited high-K dielectric cap layer, and removing the sacrificial silicon cap layer.
    Type: Grant
    Filed: November 18, 2020
    Date of Patent: August 16, 2022
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Srinivas Gandikota, Yixiong Yang, Jacqueline Samantha Wrench, Yong Yang, Steven C. H. Hung
  • Patent number: 11417832
    Abstract: The present disclosure provides a semiconductor structure, including a substrate, including a first region and a second region adjacent to the first region, a magnetic tunnel junction (MTJ) over the first region, a spacer on a sidewall of the MTJ, a hard mask over the MTJ, a first dielectric layer laterally surrounding the spacer and the hard mask, a top electrode over the hard mask, and an etch stop stack laterally surrounding the top electrode.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: August 16, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yu-Feng Yin, Tai-Yen Peng, An-Shen Chang, Han-Ting Tsai, Qiang Fu, Chung-Te Lin
  • Patent number: 11411116
    Abstract: The disclosed technology generally relates to ferroelectric materials and semiconductor devices, and more particularly to semiconductor memory devices incorporating doped polar materials. In one aspect, a semiconductor device comprises a capacitor which in turn comprises a polar layer comprising a base polar material doped with a dopant. The base polar material includes one or more metal elements and one or both of oxygen or nitrogen. The dopant comprises a metal element that is different from the one or more metal elements and is present at a concentration such that a ferroelectric switching voltage of the capacitor is different from that of the capacitor having the base polar material without being doped with the dopant by more than about 100 mV. The capacitor stack additionally comprises first and second crystalline conductive oxide electrodes on opposing sides of the polar layer.
    Type: Grant
    Filed: July 2, 2021
    Date of Patent: August 9, 2022
    Assignee: Kepler Computing Inc.
    Inventors: Ramesh Ramamoorthy, Sasikanth Manipatruni, Gaurav Thareja
  • Patent number: 11398263
    Abstract: A semiconductor structure includes an electrode, a ferroelectric material adjacent the electrode, the ferroelectric material comprising an oxide of at least one of hafnium and zirconium, the ferroelectric material doped with bismuth, and another electrode adjacent the ferroelectric material on an opposite side thereof from the first electrode. Related semiconductor structures, memory cells, semiconductor devices, electronic systems, and related methods are disclosed.
    Type: Grant
    Filed: July 15, 2020
    Date of Patent: July 26, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Albert Liao, Wayne I. Kinney, Yi Fang Lee, Manzar Siddik
  • Patent number: 11387406
    Abstract: In an embodiment, a method includes: forming a first inter-metal dielectric (IMD) layer over a semiconductor substrate; forming a bottom electrode layer over the first IMD layer; forming a magnetic tunnel junction (MTJ) film stack over the bottom electrode layer; forming a first top electrode layer over the MTJ film stack; forming a protective mask covering a first region of the first top electrode layer, a second region of the first top electrode layer being uncovered by the protective mask; forming a second top electrode layer over the protective mask and the first top electrode layer; and patterning the second top electrode layer, the first top electrode layer, the MTJ film stack, the bottom electrode layer, and the first IMD layer with an ion beam etching (IBE) process to form a MRAM cell, where the protective mask is etched during the IBE process.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: July 12, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tai-Yen Peng, Hui-Hsien Wei, Han-Ting Lin, Sin-Yi Yang, Yu-Shu Chen, An-Shen Chang, Qiang Fu, Chen-Jung Wang
  • Patent number: 11380472
    Abstract: Various embodiments include, for example, a magnetic-dielectric film-based inductor that can be embedded in an electronic package for use as an integrated voltage-regulator, multiple conductive regions to provide electrical interconnects to the magnetic-dielectric-based inductor from other devices, multiple conductive pillars that are electrically coupled to and formed over at least some of the conductive regions, and a magnetic-dielectric layer formed over at least some of conductive regions and conductive pillars. The magnetic-dielectric layer is formed by a multi-layer formation technique having multiple dielectric-material layers and multiple magnetic-material layers. Each of the magnetic-material layers is interspersed with at least one of the dielectric-material layers. Other devices, apparatuses, and methods are described.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: July 5, 2022
    Assignee: Intel Corporation
    Inventors: Srinivas V. Pietambaram, Kristof Darmawikarta, Rahul N. Manepalli
  • Patent number: 11374165
    Abstract: A process sequence is provided to provide an ultra-smooth (0.2 nm or less) bottom electrode surface for depositing magnetic tunnel junctions thereon. In one embodiment, the sequence includes forming a bottom electrode pad through bulk layer deposition followed by patterning and etching. Oxide is then deposited over the formed bottom electrode pads and polished back to expose the bottom electrode pads. A bottom electrode buff layer is then deposited thereover following a pre-clean operation. The bottom electrode buff layer is then exposed to a chemical mechanical polishing process to improve surface roughness. An magnetic tunnel junction deposition is then performed over the bottom electrode buff layer.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: June 28, 2022
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Lin Xue, Sajjad Amin Hassan, Mahendra Pakala, Jaesoo Ahn
  • Patent number: 11342343
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a source/drain structure, a metal gate structure, a ferroelectric layer, a spacer and a metal layer. The source/drain structure is disposed over the substrate. The metal gate structure is disposed over the substrate and between the source/drain structure. The ferroelectric layer is disposed over the metal gate structure and the source/drain structure. The spacer is disposed over the ferroelectric layer. The metal layer is disposed over the ferroelectric layer and surrounded by the spacer. A method for manufacturing a semiconductor structure is also provided.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: May 24, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chih-Yu Chang, Sai-Hooi Yeong, Yu-Ming Lin, Chih-Hao Wang
  • Patent number: 11329216
    Abstract: A semiconductor device includes a semiconductor substrate, a bottom electrode, a magnetic tunneling junction (MTJ), a top electrode, and a residue. The bottom electrode is disposed over the semiconductor substrate. The MTJ is disposed over the bottom electrode. The top electrode is disposed over the MTJ layer. Sidewalls of the bottom electrode, the MTJ, and the top electrode are vertically aligned with each other. The residue of the MTJ is located on the sidewall of the bottom electrode.
    Type: Grant
    Filed: April 13, 2020
    Date of Patent: May 10, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsi-Wen Tien, Wei-Hao Liao, Pin-Ren Dai, Chih-Wei Lu, Chung-Ju Lee
  • Patent number: 11329218
    Abstract: A metal hard mask layer is deposited on a MTJ stack on a substrate. A hybrid hard mask is formed on the metal hard mask layer, comprising a plurality of spin-on carbon layers alternating with a plurality of spin-on silicon layers wherein a topmost layer of the hybrid hard mask is a silicon layer. A photo resist pattern is formed on the hybrid hard mask. First, the topmost silicon layer of the hybrid hard mask is etched where is it not covered by the photo resist pattern using a first etching chemistry. Second, the hybrid hard mask is etched where it is not covered by the photo resist pattern wherein the photoresist pattern is etched away using a second etch chemistry. Thereafter, the metal hard mask and MTJ stack are etched where they are not covered by the hybrid hard mask to form a MTJ device and overlying top electrode.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: May 10, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi Yang, Yu-Jen Wang
  • Patent number: 11329050
    Abstract: A semiconductor memory device includes a substrate having a memory cell region where a plurality of active regions are defined; a word line having a stack structure of a lower word line layer and an upper word line layer and extending over the plurality of active regions in a first horizontal direction, and a buried insulation layer on the word line; a bit line structure arranged on the plurality of active regions, extending in a second horizontal direction perpendicular to the first horizontal direction, and having a bit line; and a word line contact plug electrically connected to the lower word line layer by penetrating the buried insulation layer and the upper word line layer and having a plug extension in an upper portion of the word line contact plug, the plug extension having a greater horizontal width than a lower portion of the word line contact plug.
    Type: Grant
    Filed: August 14, 2020
    Date of Patent: May 10, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyejin Seong, Dongsoo Woo, Wonchul Lee
  • Patent number: 11296146
    Abstract: According to an embodiment, a magnetoresistive memory device includes a first conductor with a first surface. A first structure on the first surface of the first conductor includes a first ferromagnetic layer. An insulating layer is on the first structure. A second structure on the insulating layer includes a second ferromagnetic layer. A second conductor is in contact with the first surface of the first conductor and a side surface of the first structure. A first insulator on the second conductor covers a side surface of the insulating layer, and is in contact with the side surface of the first structure and a side surface of the second structure. A third conductor on the first insulator is in contact with the side surface of the second structure.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: April 5, 2022
    Assignee: KIOXIA CORPORATION
    Inventor: Shuichi Tsubata
  • Patent number: 11289607
    Abstract: The disclosed technology generally relates to ferroelectric materials and semiconductor devices, and more particularly to semiconductor memory devices incorporating doped polar materials. In one aspect, a semiconductor device comprises a capacitor, which in turn comprises a polar layer comprising a crystalline base polar material doped with a dopant. The base polar material includes one or more metal elements and one or both of oxygen or nitrogen, wherein the dopant comprises a metal element that is different from the one or more metal elements and is present at a concentration such that a ferroelectric switching voltage of the capacitor is different from that of the capacitor having the base polar material without being doped with the dopant by more than about 100 mV.
    Type: Grant
    Filed: June 24, 2021
    Date of Patent: March 29, 2022
    Assignee: Kepler Computing Inc.
    Inventors: Ramesh Ramamoorthy, Sasikanth Manipatruni, Gaurav Thareja
  • Patent number: 11289603
    Abstract: A semiconductor device and method of manufacture are provided which utilizes metallic seeds to help crystallize a ferroelectric layer. In an embodiment a metal layer and a ferroelectric layer are formed adjacent to each other and then the metal layer is diffused into the ferroelectric layer. Once in place, a crystallization process is performed which utilizes the material of the metal layer as seed crystals.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: March 29, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bo-Feng Young, Sai-Hooi Yeong, Chi On Chui
  • Patent number: 11264566
    Abstract: A perpendicular magnetic tunnel junction is disclosed wherein a metal insertion (MIS) layer is formed within a free layer (FL), a partially oxidized Hk enhancing layer is on the FL, and a nitride capping layer having a buffer layer/nitride layer (NL) is on the Hk enhancing layer to provide an improved coercivity (Hc)/switching current (Jc) ratio for spintronic applications. Magnetoresistive ratio is maintained above 100%, resistance×area (RA) product is below 5 ohm/?m2, and thermal stability to 400° C. is realized. The FL comprises two or more sub-layers, and the MIS layer may be formed within at least one sub-layer or between sub-layers. The buffer layer is used to prevent oxygen diffusion to the NL, and nitrogen diffusion from the NL to the FL. FL thickness is from 11 Angstroms to 25 Angstroms while MIS layer thickness is preferably from 0.5 Angstroms to 4 Angstroms.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: March 1, 2022
    Assignee: Headway Technologies, Inc.
    Inventors: Santiago Serrano Guisan, Luc Thomas, Jodi Mari Iwata, Guenole Jan, Ru-Ying Tong
  • Patent number: 11258006
    Abstract: Provided are a magnetic memory element in which an improvement in properties, such as an improvement in coercive properties or a reduction in a leak current, can be attained, a method for producing the same, and a magnetic memory. The magnetic memory element, includes: a columnar stack ST in which a reference layer FX having a fixed magnetization direction, a barrier layer TL including a non-magnetic body, and a recording layer FR having a reversible magnetization direction are stacked in this order; and an insulating film which contains nitrogen and is provided to cover a lateral surface of the columnar stack, in which in one or both of the recording layer and the barrier layer, a nitrogen concentration is 7×1030 atoms/m2 or more in a position of 2 nm inside from an outer circumferential end of the columnar stack.
    Type: Grant
    Filed: August 18, 2020
    Date of Patent: February 22, 2022
    Assignee: TOHOKU UNIVERSITY
    Inventors: Tetsuo Endoh, Masaaki Niwa, Hiroaki Honjo, Hideo Sato, Shoji Ikeda, Toshinari Watanabe
  • Patent number: 11251360
    Abstract: A magnetic tunnel junction (MTJ) stack structure having an enhanced write performance and thermal stability (i.e., retention) is provided which can be used as an element/component of a spin-transfer torque (STT) MRAM device. The improved write performance, particularly the write error rate slope as a function of write voltage (Vfrc) which is essential in defining the overdrive voltage needed to successfully write a bit at low write error floors, is provided by a MTJ stack structure in which a zirconium (Zr) cap layer is inserted between a MTJ capping layer and an etch stop layer.
    Type: Grant
    Filed: February 6, 2020
    Date of Patent: February 15, 2022
    Assignee: International Business Machines Corporation
    Inventor: Matthias Georg Gottwald
  • Patent number: 11250899
    Abstract: A 1S-1T ferroelectric memory cell is provided that include a transistor and a two-terminal selector device. The transistor exhibits a low conductive state and a high conductive state (channel resistance), depending on drive voltage. The two-terminal selector device exhibits one of an ON-state and an OFF-state depending upon whether the transistor is in its low conductive state or its high conductive state. The transistor may be, for instance, a ferroelectric gate vertical transistor. Modulation of a polarization state of ferroelectric material of the vertical transistor may be utilized to switch the state of the selector device. The memory cell may thus selectively be operated in one of an ON-state and an OFF-state depending upon whether the selector device is in its ON-state or OFF-state.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: February 15, 2022
    Assignee: Intel Corporation
    Inventors: Abhishek A. Sharma, Brian S. Doyle, Ravi Pillarisetty, Prashant Majhi, Elijah V. Karpov
  • Patent number: 11245069
    Abstract: Embodiments of the disclosure provide methods and apparatus for fabricating magnetic tunnel junction (MTJ) structures on a substrate in for spin-transfer-torque magnetoresistive random access memory (STT-MRAM) applications. In one embodiment, the method includes patterning a film stack having a tunneling barrier layer disposed between a magnetic reference layer and a magnetic storage layer disposed on a substrate to remove a portion of the film stack from the substrate until an upper surface of the substrate is exposed, forming a sidewall passivation layer on sidewalls of the patterned film stack and subsequently performing a thermal annealing process to the film stack.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: February 8, 2022
    Assignee: Applied Materials, Inc.
    Inventors: Lin Xue, Jaesoo Ahn, Mahendra Pakala, Chi Hong Ching, Rongjun Wang