Gettering Of Semiconductor Substrate Patents (Class 438/310)
  • Patent number: 9722016
    Abstract: Proton irradiation is performed a plurality of times from rear surface of an n-type semiconductor substrate, which is an n? drift layer, forming an n-type FS layer having lower resistance than the n-type semiconductor substrate in the rear surface of the n? drift layer. When the proton irradiation is performed a plurality of times, the next proton irradiation is performed to as to compensate for a reduction in mobility due to disorder which remains after the previous proton irradiation. In this case, the second or subsequent proton irradiation is performed at the position of the disorder which is formed by the previous proton irradiation. In this way, even after proton irradiation and a heat treatment, the disorder is reduced and it is possible to prevent deterioration of characteristics, such as increase in leakage current. It is possible to form an n-type FS layer including a high-concentration hydrogen-related donor layer.
    Type: Grant
    Filed: May 17, 2016
    Date of Patent: August 1, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Hiroshi Takishita, Takashi Yoshimura, Masayuki Miyazaki, Hidenao Kuribayashi
  • Patent number: 9476914
    Abstract: Recesses are formed on one surface of a substrate. A conductive film covers an inner surface of each of the recesses. This conductive film contacts a bump of a semiconductor device to be inspected and is electrically connected to the bump. It is therefore possible to prevent damages of the bump to be caused by contact of a probe pin.
    Type: Grant
    Filed: November 2, 2012
    Date of Patent: October 25, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Takeshi Shioga, Kazuaki Kurihara
  • Patent number: 9275910
    Abstract: Methods for forming a layer of semiconductor material and a semiconductor-on-insulator structure are provided. A substrate including one or more devices or features formed therein is provided. A seed layer is bonded to the substrate, where the seed layer includes a crystalline semiconductor structure. A first portion of the seed layer that is adjacent to an interface between the seed layer and the substrate is amorphized. A second portion of the seed layer that is not adjacent to the interface is not amorphized and maintains the crystalline semiconductor structure. Dopant implantation is performed to form an N-type conductivity region or a P-type conductivity region in the first portion of the seed layer. A solid-phase epitaxial growth process is performed to crystallize the first portion of the seed layer. The SPE growth process uses the crystalline semiconductor structure of the second portion of the seed layer as a crystal template.
    Type: Grant
    Filed: May 15, 2015
    Date of Patent: March 1, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventor: Jean-Pierre Colinge
  • Patent number: 9034717
    Abstract: Methods for forming a layer of semiconductor material and a semiconductor-on-insulator structure are provided. A substrate including one or more devices or features formed therein is provided. A seed layer is bonded to the substrate, where the seed layer includes a crystalline semiconductor structure. A first portion of the seed layer that is adjacent to an interface between the seed layer and the substrate is amorphized. A second portion of the seed layer that is not adjacent to the interface is not amorphized and maintains the crystalline semiconductor structure. Dopant implantation is performed to form an N-type conductivity region or a P-type conductivity region in the first portion of the seed layer. A solid-phase epitaxial growth process is performed to crystallize the first portion of the seed layer. The SPE growth process uses the crystalline semiconductor structure of the second portion of the seed layer as a crystal template.
    Type: Grant
    Filed: May 15, 2014
    Date of Patent: May 19, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventor: Jean-Pierre Colinge
  • Patent number: 8999864
    Abstract: A silicon wafer for preventing a void defect in a bulk region from becoming source of contamination and slip generation in a device process is provided. And a heat-treating method thereof for reducing crystal defects such as COP in a region near the wafer surface to be a device active region is provided. The silicon wafer has a surface region 1 which is a defect-free region and a bulk region 2 including void defect of a polyhedron whose basic shape is an octahedron in which a corner portion of the polyhedron is in the curved shape and an inner-wall oxide film the void defect is removed. The silicon wafer is provided by performing a heat-treating method in which gas to be supplied, inner pressure of spaces and a maximum achievable temperature are set to a predetermined value when subjecting the silicon wafer produced by a CZ method to RTP.
    Type: Grant
    Filed: May 28, 2010
    Date of Patent: April 7, 2015
    Assignee: Global Wafers Japan Co., Ltd.
    Inventors: Takeshi Senda, Hiromichi Isogai, Eiji Toyoda, Koji Araki, Tatsuhiko Aoki, Haruo Sudo, Koji Izunome, Susumu Maeda, Kazuhiko Kashima, Hiroyuki Saito
  • Patent number: 8865572
    Abstract: A system for manipulating dislocations on semiconductor devices, includes a moveable laser configured to generate a laser beam locally on a surface portion of the semiconductor body having a plurality of dislocations, the moveable laser being characterized as having a scan speed, the moveable laser manipulates the plurality of dislocations on the surface portion of the semiconductor body by adjusting the temperature and the scan speed of the laser beam.
    Type: Grant
    Filed: February 7, 2014
    Date of Patent: October 21, 2014
    Assignee: International Business Machines Corporation
    Inventors: Chung Woh Lai, Xiao Hu Liu, Anita Madan, Klaus W. Schwarz, J. Campbell Scott
  • Patent number: 8865571
    Abstract: A method for manipulating dislocations from a semiconductor device includes directing a light-emitting beam locally onto a surface portion of a semiconductor body that includes active regions of the semiconductor device and manipulating a plurality of dislocations located proximate to the surface portion of the semiconductor body utilizing the light-emitting beam. Manipulating the plurality of dislocations includes directly scanning the plurality of dislocations with the light-emitting beam to manipulate a location of each of the plurality of dislocations on the surface portion of the semiconductor body by adjusting a temperature of the surface portion of the semiconductor body corresponding to the plurality of dislocations and adjusting a scan speed of the a light-emitting beam.
    Type: Grant
    Filed: February 7, 2014
    Date of Patent: October 21, 2014
    Assignee: International Business Machines Corporation
    Inventors: Chung Woh Lai, Xiao Hu Liu, Anita Madan, Klaus W. Schwarz, J. Campbell Scott
  • Patent number: 8846500
    Abstract: At least one exemplary embodiment is directed to a method of forming a multilayered gettering structure that can be used to control wafer warpage.
    Type: Grant
    Filed: December 13, 2010
    Date of Patent: September 30, 2014
    Assignee: Semiconductor Components Industries, LLC
    Inventors: David Lysacek, Jana Vojtechovska, Lubomir Dornak, Petr Kostelnik, Lukas Valek, Petr Panek
  • Patent number: 8816419
    Abstract: Provided is a semiconductor device having a high switching speed. A semiconductor device is provided with an n-type epitaxial layer having a plurality of trenches arranged at prescribed intervals; an embedded electrode formed on an inner surface of the trench through a silicon oxide film to embed each trench; and a metal layer, which is capacitively coupled with the embedded electrode by being arranged above the embedded electrode through a silicon oxide film. In the semiconductor device, a region between the adjacent trenches operates as a channel (current path). A current flowing in the channel is interrupted by covering the region with a depletion layer formed at the periphery of the trenches, and the current is permitted to flow through the channel by eliminating the depletion layer at the periphery of the trenches.
    Type: Grant
    Filed: June 17, 2008
    Date of Patent: August 26, 2014
    Assignee: Rohm Co., Ltd.
    Inventor: Masaru Takaishi
  • Patent number: 8735859
    Abstract: A nonvolatile semiconductor memory device includes: a first interconnect; a second interconnect at a position opposing the first interconnect; and a variable resistance layer between the first interconnect and the second interconnect, the variable resistance layer being capable of reversibly changing between a first state and a second state by a voltage applied via the first interconnect and the second interconnect or a current supplied via the first interconnect and the second interconnect, the first state having a first resistivity, the second state having a second resistivity higher than the first resistivity. Wherein the variable resistance layer has a compound of carbon and silicon as a main component and including hydrogen.
    Type: Grant
    Filed: November 29, 2010
    Date of Patent: May 27, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shuichi Kuboi, Masayuki Takata, Tsukasa Nakai, Hiroyuki Fukumizu, Yasuhiro Nojiri, Kenichi Ootsuka
  • Patent number: 8551837
    Abstract: Methods of fabricating semiconductor devices with high-k/metal gate features are disclosed. In some instances, methods of fabricating semiconductor devices with high-k/metal gate features are disclosed that prevent or reduce high-k/metal gate contamination of non-high-k/metal gate wafers and production tools. In some embodiments, the method comprises forming an interfacial layer over a semiconductor substrate on a front side of the substrate; forming a high-k dielectric layer and a capping layer over the interfacial layer; forming a metal layer over the high-k and capping layers; forming a polysilicon layer over the metal layer; and forming a dielectric layer over the semiconductor substrate on a back side of the substrate.
    Type: Grant
    Filed: February 29, 2012
    Date of Patent: October 8, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yih-Ann Lin, Ryan Chia-Jen Chen, Chien-Hao Chen, Kuo-Tai Huang, Yi-Hsing Chen, Jr Jung Lin, Yu Chao Lin
  • Patent number: 8546862
    Abstract: A memory cell (100) comprising a transistor, the transistor comprising a substrate (101), a first source/drain region (102), a second source/drain region (112), a gate (104) and a gate insulating layer (103) positioned between the substrate (101) and the gate (104), wherein the gate insulating layer (103) is in a direct contact with the substrate (101) and comprises charge traps (131) distributed over an entire volume of the gate insulating layer (101).
    Type: Grant
    Filed: April 19, 2010
    Date of Patent: October 1, 2013
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Dusan Golubovic
  • Patent number: 8546928
    Abstract: The present application relates to a multiple component which is to be subsequently individualized by forming components containing active structures, in addition to a corresponding component which can be used in microsystem technology systems. The multiple component and/or component comprises a flat substrate and also a flat cap structure which are bound to each other such that they surround at least one first and one second cavity per component, which are sealed against each other and towards the outside. The first of the two cavities is provided with getter material and due to the getter material has a different internal pressure and/or a different gas composition than the second cavity. The present application also relates to a method for producing the type of component and/or components for which gas mixtures of various types of gas have a different absorption ratio in relation to the getter material.
    Type: Grant
    Filed: April 4, 2007
    Date of Patent: October 1, 2013
    Assignee: Fraunhofer-Gesellschaft zur Foerderung der angewandten Forschung e. V.
    Inventors: Peter Merz, Wolfgang Reinert, Marten Oldsen, Oliver Schwarzelbach
  • Publication number: 20130210210
    Abstract: Disclosed is an improved semiconductor structure (e.g., a silicon germanium (SiGe) hetero-junction bipolar transistor) having a narrow essentially interstitial-free SIC pedestal with minimal overlap of the extrinsic base. Also, disclosed is a method of forming the transistor which uses laser annealing, as opposed to rapid thermal annealing, of the SIC pedestal to produce both a narrow SIC pedestal and an essentially interstitial-free collector. Thus, the resulting SiGe HBT transistor can be produced with narrower base and collector space-charge regions than can be achieved with conventional technology.
    Type: Application
    Filed: March 28, 2013
    Publication date: August 15, 2013
    Applicant: International Business Machines Corporation
    Inventor: International Business Machines Corporation
  • Patent number: 8399280
    Abstract: A method for protecting, against laser attacks, an integrated circuit chip formed inside and on top of a semiconductor substrate and including in the upper portion of the substrate an active portion in which are formed components, this method including the steps of: forming in the substrate a gettering area extending under the active portion, the upper limit of the area being at a depth ranging between 5 and 50 ?m from the upper surface of the substrate; and introducing diffusing metal impurities into the substrate.
    Type: Grant
    Filed: October 4, 2010
    Date of Patent: March 19, 2013
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Pascal Fornara, Fabrice Marinet
  • Patent number: 8382894
    Abstract: Silicon wafers wherein slip dislocations and warpages during device production are suppressed, contain BMDs with an octahedral shape, and of BMDs at a depth greater than 50 ?m from the surface of the wafer, the density of BMDs with diagonal size of 10 nm to 50 nm is ?1×1012/cm3, and the density of BSFs is ?1×108/cm3. The present silicon wafers preferably have an interstitial oxygen concentration of 4×1017 atoms/cm3 to 6×1017 atoms/cm3, and a density of BMDs with diagonal size of ?200 nm of not more than 1×107/cm3.
    Type: Grant
    Filed: October 26, 2009
    Date of Patent: February 26, 2013
    Assignee: Siltronic AG
    Inventors: Katsuhiko Nakai, Masayuki Fukuda
  • Patent number: 8329563
    Abstract: A device and a device manufacturing process. First, a gettering layer is formed on the bottom surface of a silicon substrate. Gates having a MOS structure are then formed on the principal surface of the silicon substrate, and the gettering layer is removed. According to this manufacturing method, the formation of the gates having a MOS structure is performed such that the gettering layer getters dissolved oxygen present in the silicon substrate. This reduces the concentration of dissolved oxygen in the silicon substrate, resulting in improved device characteristics.
    Type: Grant
    Filed: February 24, 2006
    Date of Patent: December 11, 2012
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tadaharu Minato, Hidekazu Yamamoto
  • Patent number: 8293613
    Abstract: An embodiment of a semiconductor device includes a semiconductor substrate, a first insulating layer formed over the semiconductor substrate, and a first semiconductor layer formed over the first insulation layer. At least one gettering region is formed in at least one of the first insulating layer and the first semiconductor layer. The gettering region includes a plurality of gettering sites, and at least one gettering site includes one of a precipitate, a dispersoid, an interface with the dispersoid, a stacking fault and a dislocation.
    Type: Grant
    Filed: November 29, 2010
    Date of Patent: October 23, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Soo Park, Young-Nam Kim, Young-Sam Lim, Gi-Jung Kim, Pil-Kyu Kang
  • Patent number: 8263876
    Abstract: A conductive substrate structure includes a substrate unit, a conductive pad unit, and a conductive layer unit. The substrate unit has a top surface, a bottom surface, two opposite lateral surfaces, and a front surface. The conductive pad unit has at least two first conductive pads separated from each other and disposed on the top surface, and at least two second conductive pads separated from each other and disposed on the bottom surface. The conductive layer unit has at least two first conductive layers formed on the front surface and respectively electrically connected to two front sides of the two first conductive pads, and at least two second conductive layers respectively formed on the two opposite lateral surfaces and respectively electrically connected to two opposite lateral sides of the two second conductive pads. The two first conductive layers are respectively electrically connected with the two second conductive layers.
    Type: Grant
    Filed: December 30, 2009
    Date of Patent: September 11, 2012
    Assignee: Harvatek Corporation
    Inventors: Bily Wang, Sung-Yi Hsiao, Jack Chen
  • Patent number: 8207048
    Abstract: Method for producing nanostructures comprising: a step of providing a substrate (100) having a buried barrier layer (2) and above said barrier layer (2) a crystalline film (5) provided with a network of crystalline defects and/or stress fields (12) in a crystalline zone (13), one or several steps of attacking the substrate (100), of which a preferential attack either of the crystalline defects and/or the stress fields, or the crystalline zone (13) between the crystalline defects and/or the stress fields, said attack steps enabling the barrier layer (2) to be laid bared locally and protrusions (7) to be formed on a nanometric scale, separated from each other by hollows (7.1) having a base located in the barrier layer, the protrusions leading to nanostructures (7, 8).
    Type: Grant
    Filed: December 19, 2006
    Date of Patent: June 26, 2012
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Franck Fournel, Hubert Moriceau, Chrystel Deguet
  • Patent number: 8164096
    Abstract: A flat panel display device, more particularly, an Organic Light Emitting Diode (OLED) display device having uniform electrical characteristics and a method of fabricating the same include: a thin film transistor of which a semiconductor layer including a source, a drain, and a channel region formed in a super grain silicon (SGS) crystallization growth region; a capacitor formed in an SGS crystallization seed region; and an OLED electrically connected to the thin film transistor. Further, a length of the channel region of the silicon layer is parallel with the growth direction in the SGS growth region to improve the electrical properties thereof.
    Type: Grant
    Filed: March 13, 2008
    Date of Patent: April 24, 2012
    Assignee: Samsung Mobile Display Co., Ltd.
    Inventors: Jong-Hyun Choi, Woo-Sik Jun
  • Patent number: 8143910
    Abstract: Provided is a semiconductor integrated circuit including: a first path that includes a first logic circuit; a second path that includes a second logic circuit; and a subsequent-stage circuit that is connected to an output of the first path and is connected to an output of the second path, in which the second path further includes a first internal path that is selected as a propagation path during a normal operation period; and a second internal path that is selected as a propagation path during a test operation period and includes a delay circuit having a delay amount larger than a delay amount of the first internal path.
    Type: Grant
    Filed: June 15, 2009
    Date of Patent: March 27, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Hiroyuki Kobatake
  • Patent number: 8138066
    Abstract: A method for generating patterned strained regions in a semiconductor device is provided. The method includes directing a light-emitting beam locally onto a surface portion of a semiconductor body; and manipulating a plurality of dislocations located proximate to the surface portion of the semiconductor body utilizing the light-emitting beam, the light-emitting beam being characterized as having a scan speed, so as to produce the patterned strained regions.
    Type: Grant
    Filed: October 1, 2008
    Date of Patent: March 20, 2012
    Assignee: International Business Machines Corporation
    Inventors: Chung Woh Lai, Xiao Hu Liu, Anita Madan, Klaus W. Schwarz, J. Campbell Scott
  • Patent number: 8133769
    Abstract: A method for forming gettering sites and gettering impurities in a substrate layer includes producing a first masking layer over the substrate layer and patterning the masking layer to define openings at locations where trenches will be formed in the substrate layer at a later time. Ions are then implanted into the substrate layer to produce gettering sites. The gettering sites are disposed at a depth in the substrate layer such that the sites are removed when the trenches are formed. The first masking layer is removed and impurities driven to the gettering sites by thermally processing the substrate layer. A second masking layer is then produced over the substrate layer and patterned to define openings at locations where the trenches will be formed. The substrate layer is etched to produce the trenches. The gettering sites and gettered impurities are removed when the trenches are etched into the substrate layer.
    Type: Grant
    Filed: December 17, 2010
    Date of Patent: March 13, 2012
    Assignee: Truesense Imaging, Inc.
    Inventor: Cristian A. Tivarus
  • Patent number: 8093089
    Abstract: Method of manufacturing image sensors having a plurality of gettering regions. In the method, a gate electrode may be formed on a semiconductor substrate. A source/drain region may be formed in the semiconductor substrate to be overlapped with the gate electrode. A gettering region may be formed in the semiconductor substrate to be adjacent to the source/drain region.
    Type: Grant
    Filed: April 19, 2010
    Date of Patent: January 10, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Hyun-Pil Noh
  • Patent number: 7799660
    Abstract: The present invention provides a method for manufacturing an SOI substrate by which an oxygen ion is implanted from at least one of main surfaces of a single-crystal silicon substrate to form an oxygen-ion-implanted layer and then an oxide film-forming heat treatment that changes the formed oxygen-ion-implanted layer into a buried oxide film layer is performed with respect to the single-crystal silicon substrate to manufacture the SOI substrate, the method comprising: implanting a neutral element ion having a dose amount of 1×1012 atoms/cm2 or above and less than 1×1015 atoms/cm2 into a back surface to form an ion-implanted damage layer after performing the oxide film-forming heat treatment; and gettering a metal impurity in the ion-implanted damage layer by a subsequent heat treatment to enable reducing a metal impurity concentration on a front surface side.
    Type: Grant
    Filed: April 1, 2008
    Date of Patent: September 21, 2010
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Tohru Ishizuka, Hiroshi Takeno, Nobuhiko Noto
  • Patent number: 7737004
    Abstract: In one embodiment, a multi-layer extrinsic gettering structure includes plurality of polycrystalline semiconductor layers each separated by a dielectric layer.
    Type: Grant
    Filed: July 3, 2006
    Date of Patent: June 15, 2010
    Assignee: Semiconductor Components Industries LLC
    Inventors: David Lysacek, Michal Lorenc, Lukas Valek
  • Patent number: 7573083
    Abstract: A transistor type ferroelectric memory including: a substrate; a gate electrode formed above the substrate; a ferroelectric layer formed above the substrate to cover the gate electrode; a source electrode formed above the ferroelectric layer; a drain electrode formed above the ferroelectric layer and apart from the source electrode; and a channel layer formed above the ferroelectric layer and between the source electrode and the drain electrode.
    Type: Grant
    Filed: December 4, 2006
    Date of Patent: August 11, 2009
    Assignee: Seiko Epson Corporation
    Inventors: Takeshi Kijima, Akio Konishi
  • Patent number: 7569693
    Abstract: Provided are mono- and diimide naphthalene compounds for use in the fabrication of various device structures. In some embodiments, the naphthalene core of these compounds are mono-, di-, or tetra-substituted with cyano group(s) or other electron-withdrawing substituents or moieties. Such mono- and diimide naphthalene compounds also can be optionally N-substituted.
    Type: Grant
    Filed: June 12, 2007
    Date of Patent: August 4, 2009
    Assignee: Northwestern University
    Inventors: Tobin J. Marks, Michael R. Wasielewski, Antonio Facchetti, Brooks A. Jones
  • Patent number: 7498620
    Abstract: According to one exemplary embodiment, a heterojunction bipolar transistor includes a base situated on a substrate. The heterojunction bipolar transistor can be an NPN silicon-germanium heterojunction bipolar transistor, for example. The heterojunction bipolar transistor further includes a cap layer situated on the base, where the cap layer includes a barrier region. The barrier region can comprises carbon and has a thickness, where the thickness of the barrier region determines a depth of an emitter-junction of the heterojunction bipolar transistor. An increase in the thickness of the barrier region can cause a decrease in the depth of the emitter-base junction. According to this exemplary embodiment, the heterojunction bipolar transistor further includes an emitter situated over the cap layer, where the emitter comprises an emitter dopant, which can be phosphorus. A diffusion retardant in the barrier region of the cap layer impedes diffusion of the emitter dopant.
    Type: Grant
    Filed: September 21, 2006
    Date of Patent: March 3, 2009
    Assignee: Newport Fab, LLC
    Inventor: Greg D. U'Ren
  • Patent number: 7422951
    Abstract: The present invention provides a method of fabricating a self-aligned bipolar transistor, by which the fabricating method can be simplified by forming P+ and N+ junctions by self-alignment and by which device reliability can be enhanced. The present invention includes the steps of forming a well in a substrate isolated by a device isolation layer, forming a polysilicon gate on the substrate, forming an insulating layer on the substrate, forming a sidewall spacer on lateral sides of the polysilicon gate by etching the insulating layer, forming a P+ ion implanted region in the substrate, forming an N+ ion implanted region in the substrate, and forming silicide on the P+ and N+ ion implanted regions.
    Type: Grant
    Filed: December 28, 2004
    Date of Patent: September 9, 2008
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Kwang Young Ko
  • Publication number: 20080003782
    Abstract: In one embodiment, a multi-layer extrinsic gettering structure includes plurality of polycrystalline semiconductor layers each separated by a dielectric layer.
    Type: Application
    Filed: July 3, 2006
    Publication date: January 3, 2008
    Inventors: David Lysacek, Michal Lorenc, Lukas Valek
  • Patent number: 7297630
    Abstract: A method of fabricating a via and a trench is disclosed. A disclosed method comprises: forming a via hole and a trench in a interlayer dielectric layer on a semiconductor substrate where a predetermined device is formed; depositing a thin Hf layer on the substrate; performing a thermal treatment of the substrate to getter oxygen and forming a barrier layer; and filling copper into the via hole and the trench.
    Type: Grant
    Filed: December 30, 2004
    Date of Patent: November 20, 2007
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Jung Joo Kim
  • Patent number: 7297992
    Abstract: According to one exemplary embodiment, a heterojunction bipolar transistor includes a base situated on a substrate. The heterojunction bipolar transistor can be an NPN silicon-germanium heterojunction bipolar transistor, for example. The heterojunction bipolar transistor further includes a cap layer situated on the base, where the cap layer includes a barrier region. The barrier region can comprises carbon and has a thickness, where the thickness of the barrier region determines a depth of an emitter-junction of the heterojunction bipolar transistor. An increase in the thickness of the barrier region can cause a decrease in the depth of the emitter-base junction. According to this exemplary embodiment, the heterojunction bipolar transistor further includes an emitter situated over the cap layer, where the emitter comprises an emitter dopant, which can be phosphorus. A diffusion retardant in the barrier region of the cap layer impedes diffusion of the emitter dopant.
    Type: Grant
    Filed: November 23, 2004
    Date of Patent: November 20, 2007
    Assignee: Newport Fab, LLC
    Inventor: Greg D. U'Ren
  • Patent number: 7211482
    Abstract: A memory cell of a semiconductor device and a method for forming the same, wherein the memory cell includes a substrate having active regions and field regions, a gate layer formed over the substrate, the gate layer including a plurality of access gates formed over the active regions of the substrate and a plurality of pass gates formed over the field regions of the substrate, first self-aligned contact regions formed between adjacent pass gates and access gates, and second self-aligned contact regions formed between adjacent access gates, wherein a width of each of the first self-aligned contact regions is larger than a width of each of the second self-aligned contact regions.
    Type: Grant
    Filed: June 1, 2005
    Date of Patent: May 1, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ji-Young Kim, Jin-Jun Park
  • Patent number: 7169664
    Abstract: According to the present invention, a metal and a barrier material, such as copper and a tantalum-based barrier material, are effectively removed from the wafer edge and especially from the bevel by using an etchant that comprises a diluted mixture of hydrofluoric acid and nitric acid. The method is compatible with currently available etch modules for removing metal from the wafer edge, wherein, depending on the hardware specifics, copper, barrier material and dielectric material may be removed in a single etch step, or a first etch step may be performed substantially without any nitric acid so as to avoid the formation of nitric oxides. In this way, the formation of instable layer stacks may be substantially avoided, thereby reducing the risk of material delamination from the substrate edge.
    Type: Grant
    Filed: December 29, 2003
    Date of Patent: January 30, 2007
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Axel Preusse, Markus Nopper, Holger Schührer
  • Patent number: 7169674
    Abstract: A diffusion barrier (and method for forming the diffusion barrier) for a field-effect transistor having a channel region and a gate electrode, includes an insulating material being disposed over the channel region. The insulating material includes nitrogen (N), and is disposed under the gate electrode. The insulating material can be provided either as a layer or distributed within a gate dielectric material disposed under the gate electrode.
    Type: Grant
    Filed: February 28, 2005
    Date of Patent: January 30, 2007
    Assignee: International Business Machines Corporation
    Inventors: Nestor Alexander Bojarczuk, Jr., Kevin Kok Chan, Christopher Peter D'Emic, Evgeni Gousev, Supratik Guha, Paul C. Jamison, Lars-Ake Ragnarsson
  • Patent number: 7135351
    Abstract: The present invention is directed to a single crystal Czochralski-type silicon wafer, and a process for the preparation thereof, which has at least a surface layer of high resistivity, the layer having an interstitial oxygen content which renders it incapable of forming thermal donors in an amount sufficient to affect resistivity upon being subjected to a conventional semiconductor device manufacturing process. The present invention further directed to a silicon on insulator structure derived from such a wafer.
    Type: Grant
    Filed: March 17, 2005
    Date of Patent: November 14, 2006
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Martin J. Binns, Robert J. Falster, Jeffrey L. Libbert
  • Patent number: 6958264
    Abstract: A method of manufacturing a semiconductor device on a silicon-on-insulator wafer including a silicon active layer having at least two die pads formed thereon, the at least two die pads separated by at least one scribe lane, including the steps of forming at least one cavity through the silicon active layer in the at least one scribe lane; forming at least one gettering plug in each said cavity, each said gettering plug comprising doped fill material containing a plurality of gettering sites; and subjecting the wafer to conditions to getter at least one impurity into the plurality of gettering sites.
    Type: Grant
    Filed: April 3, 2001
    Date of Patent: October 25, 2005
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Ming-Ren Lin
  • Patent number: 6897084
    Abstract: The present invention is directed to a single crystal Czochralski-type silicon wafer, and a process for the preparation thereof, which has at least a surface layer of high resistivity, the layer having an interstitial oxygen content which renders it incapable of forming thermal donors in an amount sufficient to affect resistivity upon being subjected to a conventional semiconductor device manufacturing process. The present invention further directed to a silicon on insulator structure derived from such a wafer.
    Type: Grant
    Filed: April 11, 2002
    Date of Patent: May 24, 2005
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Martin Jeffrey Binns, Robert J. Falster, Jeffrey L. Libbert
  • Patent number: 6838321
    Abstract: An N?-type silicon substrate (1) has a bottom surface and an upper surface which are opposed to each other. In the bottom surface of the N?-type silicon substrate (1), a P-type impurity diffusion layer (3) of high concentration is entirely formed by diffusing a P-type impurity. In the upper surface of the N?-type silicon substrate (1), a P-type isolation region (2) is partially formed by diffusing a P-type impurity. The P-type isolation region (2) has a bottom surface reaching an upper surface of the P-type impurity diffusion layer (3). As viewed from the upper surface side of the N?-type silicon substrate (1), the P-type isolation region (2) is formed, surrounding an N? region (1a) which is part of the N?-type silicon substrate (1). The N? region (1a) surrounded by the P-type isolation region (2) is defined as an element formation region of the N?-type silicon substrate (1).
    Type: Grant
    Filed: September 26, 2003
    Date of Patent: January 4, 2005
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Mitsuru Kaneda, Hideki Takahashi
  • Patent number: 6815282
    Abstract: Silicon on insulator (SOI) field effect transistors (FET) with a shared body contact, a SRAM cell and array including the SOI FETs and the method of forming the SOI FETs. The SRAM cell has a hybrid SOI/bulk structure wherein the source/drain diffusions do not penetrate to the underlying insulator layer, resulting in a FET in the surface of an SOI layer with a body or substrate contact formed at a shared contact. FETs are formed on SOI silicon islands located on a BOX layer and isolated by shallow trench isolation (STI). NFET islands in the SRAM cells include a body contact to a P-type diffusion in the NFET island. Each NFET in the SRAM cells include at least one shallow source/drain diffusion that is shallower than the island thickness. A path remains under the shallow diffusions between NFET channels and the body contact. The P-type body contact diffusion is a deep diffusion, the full thickness of the island. Bit line diffusions shared by SRAM cells on adjacent wordlines may be deep diffusions.
    Type: Grant
    Filed: June 12, 2003
    Date of Patent: November 9, 2004
    Assignee: International Business Machines Corp.
    Inventors: William R. Dachtera, Rajiv V. Joshi, Werner A. Rausch
  • Patent number: 6797547
    Abstract: A semiconductor device includes an elongated, blade-shaped semiconductor element isolated from a surrounding region of a semiconductor substrate by buried and side oxide layers. A polysilicon post disposed at one end of the element has a bottom portion extending through the buried oxide to contact the substrate, providing for electrical and thermal coupling between the element and the substrate and for gettering impurities during processing. A device fabrication process employs a selective silicon-on-insulator (SOI) technique including forming trenches in the substrate; passivating the upper portion of the element; and performing a long oxidation to create the buried oxide layer. A second oxidation is used to create an insulating oxide layer on the sidewalls of the semiconductor element, and polysilicon material is used to fill the trenches and to create the post.
    Type: Grant
    Filed: October 3, 2003
    Date of Patent: September 28, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Sheldon D. Haynie, Steven L. Merchant, Sameer P. Pendharkar, Vladimir Bolkhovsky
  • Publication number: 20040180505
    Abstract: The present invention provides an epitaxial wafer wherein a silicon epitaxial layer is formed on a surface of a silicon single crystal wafer in which nitrogen is doped, and a density of oxide precipitates having such a size that a gettering capability can be achieved in a bulk is 108 numbers/cm3 or more. And the present invention also provides a method for producing an epitaxial wafer wherein a silicon single crystal in which nitrogen is doped is pulled by Czochralski method, the silicon single crystal is processed into a wafer to produce a silicon single crystal wafer, and the silicon single crystal wafer is subjected to heat treatment so that a density of oxide precipitates having such a size that a gettering capability can be achieved in a bulk of the wafer may be 108 numbers/cm3 or more, and then the silicon single crystal wafer is subjected to epitaxial growth. A silicon single crystal wafer which surely has a high gettering capability irrespective of a device process can be obtained herewith.
    Type: Application
    Filed: February 18, 2004
    Publication date: September 16, 2004
    Inventor: Satoshi Tobe
  • Patent number: 6784051
    Abstract: The present invention provides a method for fabricating a semiconductor device capable of preventing a pattern at an edge area of a wafer from being lifted and acting as a particle source. The present invention includes the steps of: preparing a wafer having a first area and a second area, wherein the first area has lower topology than the second area; forming a target layer on the wafer; and patterning the target layer through a photolithography process so to form a number of first patterns in a line shape at the second area and to form a number of second patterns in a closed loop shape at the first area.
    Type: Grant
    Filed: December 30, 2002
    Date of Patent: August 31, 2004
    Assignee: Hynix Semiconductor Inc.
    Inventor: Sung-Kwon Lee
  • Patent number: 6777272
    Abstract: A driver circuit integration type (monolithic type) active matrix display device having high performance is formed by using thin film transistors (TFT). While a nickel element is added t an amorphous silicon film 203, a head treatment is carried out to thereby crystallize the amorphous silicon film. Further, by carrying out a heat treatment in an oxidizing atmosphere containing a halogen element, a thermal oxidation film 209 is formed. At this time, cyrstallinity is improved and gettering of the nickel element proceeds. TFTs are formed by using the thus obtained crystalline silicon film, and various circuits are constituted by using the TFTs, so that a data driver circuit capable of driving the active matrix circuit having the dot number of fifty thousands to three millions can be obtained.
    Type: Grant
    Filed: September 26, 2002
    Date of Patent: August 17, 2004
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Yasushi Ogata
  • Publication number: 20040113223
    Abstract: A semiconductor device includes an elongated, blade-shaped semiconductor element isolated from a surrounding region of a semiconductor substrate by buried and side oxide layers. A polysilicon post disposed at one end of the element has a bottom portion extending through the buried oxide to contact the substrate, providing for electrical and thermal coupling between the element and the substrate and for gettering impurities during processing. A device fabrication process employs a selective silicon-on-insulator (SOI) technique including forming trenches in the substrate; passivating the upper portion of the element; and performing a long oxidation to create the buried oxide layer. A second oxidation is used to create an insulating oxide layer on the sidewalls of the semiconductor element, and polysilicon material is used to fill the trenches and to create the post.
    Type: Application
    Filed: December 17, 2002
    Publication date: June 17, 2004
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sheldon D. Haynie, Steven L. Merchant, Sameer P. Pendharkar, Vladimir Bolkhovsky
  • Patent number: 6703281
    Abstract: MOSFETs are fabricated with accurately defined, high and uniformly concentrated source/drain regions and extensions employing plural, sequential pre-amorphizing, implanting and laser thermal annealing steps with intervening spacer removal. Embodiments include forming sidewall spacers on a gate electrode, sequentially pre-amorphizing, ion implanting and laser thermal annealing to form deep source/drain regions, removing the sidewall spacers, and then sequentially pre-amorphizing, ion implanting and laser thermal annealing to form shallow source/drain extensions.
    Type: Grant
    Filed: October 21, 2002
    Date of Patent: March 9, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Bin Yu
  • Patent number: 6693015
    Abstract: A capacitor having improved size for enhanced capacitance and a method of forming the same are disclosed. In one embodiment, the capacitor is a stacked container capacitor used in a dynamic random access memory circuit. The capacitor provides a capacitor that has high storage capacitance which provides an increased efficiency for a cell without an increase in the size of the cell.
    Type: Grant
    Filed: August 14, 2001
    Date of Patent: February 17, 2004
    Assignee: Micron Technology, Inc.
    Inventor: Robert K. Carstensen
  • Patent number: 6670259
    Abstract: The present invention relates to a method of manufacturing a silicon-on-insulator substrate, comprising the steps of (1) providing a silicon-on-insulator semiconductor wafer having at least one surface of a silicon film; (2) implanting an inert atom into the at least one surface to form a damaged surface layer including a gettering site on the silicon film and to leave an undamaged region of the silicon film; (3) subjecting the wafer to conditions to getter at least one impurity from the silicon film into the gettering site; and (4) removing the damaged surface layer.
    Type: Grant
    Filed: February 5, 2002
    Date of Patent: December 30, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Simon Siu-Sing Chan