Abstract: The present invention relates to a method of manufacturing a silicon-on-insulator substrate, comprising the steps of (1) providing a silicon-on-insulator semiconductor wafer having at least one surface of a silicon film; (2) implanting an inert atom into the at least one surface to form a damaged surface layer including a gettering site on the silicon film and to leave an undamaged region of the silicon film; (3) subjecting the wafer to conditions to getter at least one impurity from the silicon film into the gettering site; and (4) removing the damaged surface layer.

Abstract: A semiconductor device comprising organic semiconductor material (14) has one or more barrier layers (16) disposed at least partially thereabout to protect the organic semiconductor material (14) from environment-driven changes that typically lead to inoperability of a corresponding device. If desired, the barrier layer can be comprised of partially permeable material that allows some substances therethrough to thereby effect disabling of the encapsulated organic semiconductor device after a substantially predetermined period of time. Getterers (141) may also be used to protect, at least for a period of time, such organic semiconductor material.

Abstract: An SOI semiconductor device includes at least an SOI substrate including an insulating film and a semiconductor layer formed on the insulating film; and an active semiconductor element formed on the semiconductor layer. The active semiconductor element is formed in an element formation region surrounded by an isolating region for isolating the semiconductor layer in a form of an island. A gettering layer containing a high concentration impurity is formed in a portion of the semiconductor layer excluding the element formation region in which the active semiconductor element is formed, and the gettering layer is not formed in the element formation region in which the active semiconductor element is formed.

Abstract: An electronic device that is sealed under vacuum includes a substrate, a transistor formed on the substrate, and a dielectric layer covering at least a portion of the transistor. The electronic device further includes a layer of non-evaporable getter material disposed on a portion of the dielectric layer; and a vacuum device disposed on a portion of the substrate. Electrical power pulses activate the non-evaporable getter material.

Abstract: A method for producing a multi-layer, micro-mechanical device. The device comprises an internal cavity having a micro-mechanical component therein. The method comprises the steps of forming the micro-mechanical component from a layer of first material, providing a sealing layer on at least one surface of the first material to define the cavity, providing a getter material within the cavity, sealing the first material to the sealing layers by anodic bonding, supplying an inert gas to the cavity to regulate the pressure inside the cavity. A corresponding device produced by the method is also disclosed.

Abstract: A method of manufacturing a semiconductor memory device comprising: a step of forming a storage node in which a conductive layer 7 to be the storage node is formed in the vicinity of single crystalline silicon 3 formed on an insulator 2, a gettering step for conducting heat treatment to the single crystalline silicon 3 after the step of forming the storage node and gettering contaminants contained in the single crystalline silicon 3 by the conductive layer 7 connected to the single crystalline silicon, and a step of forming a gate oxide film 8a on the single crystalline silicon 3 after the step of gettering is provided to thereby obtain a sufficient gettering effect even though the width of an element and/or the thickness of the element is reduced in accordance with microminiaturization of the element.

Abstract: A switching field effect transistor includes a substrate; a Mott-Brinkman-Rice insulator formed on the substrate, the Mott-Brinkman-Rice insulator undergoing abrupt metal-insulator transition when holes added therein; a dielectric layer formed on the Mott-Brinkman-Rice insulator, the dielectric layer adding holes into the Mott-Brinkman-Rice insulator when a predetermined voltage is applied thereto; a gate electrode formed on the dielectric layer, the gate electrode applying the predetermined voltage to the dielectric layer; a source electrode formed to be electrically connected to a first portion of the Mott-Brinkman-Rice insulator; and a drain electrode formed to be electrically connected to a second portion of the Mott-Brinkman-Rice insulator.

Abstract: Methods for forming dielectric layers over polysilicon substrates, useful in the construction of capacitors and other semiconductor circuit components are provided. A self-limiting nitric oxide (NO) anneal of a polysilicon layer such as an HSG polysilicon capacitor electrode, at less than 800° C., is utilized to grow a thin oxide (oxynitride) layer of about 40 angstroms or less over the polysilicon layer. The NO anneal provides a nitrogen layer at the polysilicon-oxide interface that limits further oxidation of the polysilicon layer and growth of the oxide layer. The oxide layer is exposed to a nitrogen-containing gas to nitridize the surface of the oxide layer and reduce the effective dielectric constant of the oxide layer. The process is particularly useful in forming high K dielectric insulating layers such as tantalum pentoxide over polysilicon.

Abstract: In a method of manufacturing matrix electron emitter arrays, each array comprising a plurality of scanning lines formed on a glass substrate and arranged in parallel with each other, a plurality of signal lines formed in a direction to cross the scanning lines and arranged in parallel with each other, and field-emission type electron emitters formed in the pixel areas which are arranged at the intersections of the scanning lines and the signal lines, a pulse voltage with a specific polarity and another pulse voltage with the reverse polarity are applied to any two of the scanning lines and current is caused to flow through electron emitters connected in series-via a signal line, thereby subjecting the conductive thin film constituting an electron emitter to a conductive activation process for forming an electron emitting section.

Abstract: Methods of forming integrated circuit capacitors (e.g., DRAM capacitors) include the steps of forming a first capacitor electrode (e.g., polysilicon electrode) on a substrate and then forming a titanium nitride layer on the first capacitor electrode. A tantalum pentoxide dielectric layer is then formed on an upper surface of the titanium nitride layer. A step is then performed to convert the underlying titanium nitride layer into a titanium oxide layer. A second capacitor electrode is then formed on the tantalum pentoxide layer. The step of converting the titanium nitride layer into a titanium oxide layer is preferably performed by annealing the tantalum pentoxide layer in an oxygen ambient in a range between about 700° C. and 900° C. This oxygen ambient provides free oxygen to fill vacancies within the tantalum oxide layer and also provides free oxygen which diffuses into the underlying titanium nitride layer.

Abstract: A method of production of a semiconductor device able to be miniaturized by preventing the decline of the hfe at a low current caused by an increase of a surface recombination current of a bipolar transistor and forming the external base region by self-alignment with respect to emitter polycrystalline silicon in the BiCMOS process. An intrinsic base region of a first semiconductor element is formed, an insulating film having an opening at an emitter formation region of part of the intrinsic base region is formed, and then an emitter electrode of the first semiconductor element and a protective film are formed on an insulating film having the opening. Next, a sidewall insulating film is left on the gate electrode side portion. Simultaneously, the insulating film is removed while partially leaving the emitter region forming-use insulating film under the emitter electrode.

Abstract: In one implementation, A method of forming semiconductive material active area having a proximity gettering region received therein includes providing a substrate comprising bulk semiconductive material. A proximity gettering region is formed within the bulk semiconductive material within a desired active area by ion implanting at least one impurity into the bulk semiconductive material. After forming the proximity gettering region, thickness of the bulk semiconductive material is increased in a blanket manner at least within the desired active area. In one implementation, a method of processing a monocrystalline silicon substrate includes forming a proximity gettering region within monocrystalline silicon of a monocrystalline silicon substrate. After forming the proximity gettering region, epitaxial monocrystalline silicon is formed on the substrate monocrystalline silicon to blanketly increase its thickness at least over the proximity gettering region.

Abstract: A bipolar transistor and a method of manufacturing the transistor. The transistor includes: (1) a substrate having a base region, an emitter region and a base-emitter junction between said base and emitter regions and (2) a substantial concentration of an isotope of hydrogen located in said biploar transistor.

Abstract: The present invention provides a method for reducing aspect ratio of DRAM peripheral contact so as to achieving a good contact etching and metal deposition by utilizing conventional equipment. Besides, the present invention provides a stop layer formed by a nitride layer to reduce the volcano effect resulted from the misalignment between stacked contacts. Furthermore, the present invention is capable of etching poly layer and oxide layer in a single step, whereby the height of the peripheral contact is substantially the same as, or lower than, the contact of the storage node of a capacitor. Therefore, the aspect ratio of DRAM peripheral contact can be reduced.

Abstract: The invention encompasses DRAM constructions, capacitor constructions, conductive contacts, integrated circuitry, methods of forming DRAM constructions, and methods of forming capacitor constructions.

Abstract: In one aspect, the invention pertains to a method of forming a gettering region within an Si semiconductor wafer, the method including: a) providing a semiconductor material wafer; b) providing a background region within the semiconductor material wafer, the background region being doped with a first-type conductivity enhancing dopant, the first-type conductivity enhancing dopant being either n-type or p-type; c) implanting a second-type conductivity enhancing dopant into the background region to form a second-type implant region entirely contained within the background region, the second-type conductivity enhancing dopant being of an opposite type than the first-type conductivity enhancing dopant of the background region; and d) implanting a neutral-conductivity-type conductivity enhancing dopant into the second-type implant region to form a metals gettering damage region entirely contained within the second-type implant region. The invention also pertains to gettering region structures.

Abstract: A fabrication method of a semiconductor device capable of effective gettering treatment even when electronic elements are further miniaturized and further integrated and a semiconductor substrate or wafer is upsized. First, a single-crystal silicon substrate having a p-type gettering layer in its interior is prepared. Transistors are formed at the main surface of the substrate. An interlayer dielectric layer is formed to cover the transistors. Contact holes are formed in the interlayer dielectric layer to uncover specific positions of the respective transistors. The substrate is rapidly heated to a first temperature of 700.degree. C. to 850.degree. C. at a heating rate. The substrate is gradually cooled from the first temperature to a second temperature of approximately 600.degree. C. at a cooling rate. Metallic wiring lines are formed on the interlayer dielectric layer to electrically connected to the respective transistors through the corresponding contact holes.

Abstract: The tendency of mobile positive ions to be transported into device regions of a bipolar transistor is effectively minimized by surrounding the transistor with a `positive ion`-attracting electric field, preferably by applying a prescribed bias to the fill material of a conductive trench that surrounds the device. The trench which surrounds a respective device to be protected contains dielectric material disposed along sidewalls of the trench. The trench contains material such as undoped polysilicon, which is capable of distributing a voltage, so that the material in the trench is insulated by dielectric material from an adjacent portion of the semiconductor substrate surrounded by the trench. In order to prevent mobile positive ions from moving into a device region in response to temperature bias stress and thereby degrade an operational parameter of the transistor, a predefined (relatively negative) bias voltage is applied to the material in the trench.

Abstract: In one aspect, the invention pertains to a method of forming a gettering region within an Si semiconductor wafer, the method including: a) providing a semiconductor material wafer; b) providing a background region within the semiconductor material wafer, the background region being doped with a first-type conductivity enhancing dopant, the first-type conductivity enhancing dopant being either n-type or p-type; c) implanting a second-type conductivity enhancing dopant into the background region to form a second-type implant region entirely contained within the background region, the second-type conductivity enhancing dopant being of an opposite type than the first-type conductivity enhancing dopant of the background region; and d) implanting a neutral-conductivity-type conductivity enhancing dopant into the second-type implant region to form a metals gettering damage region entirely contained within the second-type implant region. The invention also pertains to gettering region structures.

Abstract: The boundary between the P type silicon base and N.sup.+ buffer layer of an IGBT is intentionally damaged, as by a germanium implant, to create well defined and located damage sites for reducing lifetime in the silicon.

Abstract: Dopant atoms have coefficients of diffusion that vary due to implant damage. Damaged regions are selected and created by implanting silicon atoms into a silicon substrate prior to formation of a gate electrode. The silicon atoms act as a getter for attracting selected dopants that are trapped in the silicon substrate. Dopants are implanted in the vicinity of the damaged regions and diffused by transient-enhanced diffusion (TED) into the damaged regions by thermal cycling to accumulate dopant atoms. Transient-enhanced diffusion improves the doping of a substrate by enhancing the diffusion of dopants at relatively low anneal temperatures. Dopant accumulation sets particular selected electrical properties without placing an excessive amount of dopant in regions adjacent to junctions for purposes including threshold control for a field device, threshold setting for a transistor, and prevention of device punchthrough.

Abstract: A device isolation region and a gate oxide film are formed on a front surface of a silicon substrate, with a gate electrode formed on the gate oxide film. Next, an interlayer insulator film is formed on their entire surfaces. Then, polycrystalline silicon film is grown on the rear surface of the silicon substrate. The polycrystalline silicon film is deposited in such a way as to be in contact with the rear surface of the substrate. Then, to permit the polycrystalline silicon film formed at the rear surface of the silicon substrate to getter a pollution heavy metal, a heat treatment is performed for the substrate at a temperature of 500 to 900.degree. C. After this gettering process, an interconnection line is formed on the interlayer insulator film.

Abstract: A getterer structure for dielectrically isolated wafer structures such as bonded wafers. The getterer is a layer of polysilicon along the sidewalls of semiconductor regions isolated from each other by trenches. The polysilicon may be doped. The polysilicon is oxidized and polysilicon deposited to fill voids in the trenches.

Abstract: In one aspect, the invention pertains to a method of forming a gettering region within an Si semiconductor wafer, the method including: a) providing a semiconductor material wafer; b) providing a background region within the semiconductor material wafer, the background region being doped with a first-type conductivity enhancing dopant, the first-type conductivity enhancing dopant being either n-type or p-type; c) implanting a second-type conductivity enhancing dopant into the background region to form a second-type implant region entirely contained within the background region, the second-type conductivity enhancing dopant being of an opposite type than the first-type conductivity enhancing dopant of the background region; and d) implanting a neutral-conductivity-type conductivity enhancing dopant into the second-type implant region to form a metals gettering damage region entirely contained within the second-type implant region. The invention also pertains to gettering region structures.

Abstract: The removal of particulate contaminants, such as dust particles, from the surface of a semiconductor wafer is achieved by pressing a soft adhesive layer against the wafer surface, leaving it in place for a short time and then removing it. The adhesive is brought to the wafer surface on a flexible medium which serves as a backing layer and to whose other side pressure can be applied. To remove the adhesive, the backing layer is peeled off, either by pulling on one end or by passing a sticky roller over it. The operation may be performed in air or under vacuum.