Abstract: Walkout in high voltage trench isolated semiconductor devices is inhibited by applying a voltage bias signal directly to epitaxial silicon surrounding the device. Voltage applied to the surrounding epitaxial silicon elevates the initial breakdown voltage of the device and eliminates walkout. This is because voltage applied to the surrounding epitaxial silicon reduces the strength of the electric field between the silicon of the device and the surrounding silicon. Specifically, application of a positive voltage bias signal to surrounding epitaxial silicon equal to or more positive than the most positive potential occurring at the collector during normal operation of the device ensures that no walkout will occur.

Abstract: The manufacturing of the emitter-base junction of a bipolar transistor on an active silicon region delimited by an insulator, the assembly being covered with a first insulating layer, including the steps of etching the first insulating layer to expose the active region; etching the active region across a given height; forming very heavily-doped silicon spacers at the internal periphery of the protrusions resulting from the etching of the first insulating layer and from the etching of the active region; depositing by epitaxy a base layer; forming a third insulating spacer at the internal periphery of a protrusion of the base layer corresponding to the first spacer; depositing an emitter layer; and performing a chem-mech polishing, by using the first layer and the third spacer as stops.

Abstract: Disclosed herein are various methods for preventing bending of a patterned SOI layer during trench sidewall oxidation, the methods comprising providing a patterned SOI layer having at least one trench, said patterned SOI layer disposed upon an underlying buried silicon oxide layer; and blocking diffusion of oxygen between said patterned SOI and buried silicon oxide layer.

Abstract: An optical circuit device is manufactured by forming an organic film formed on a substrate, and giving this organic film non-linear optical properties. An optical circuit device is formed containing an organic film formed on a substrate, wherein said film is either selectively formed on a portion of the region on a substrate or said film being formed over the entire region on a substrate, and a portion of a region of that film is either selectively formed to a thickness differing from other regions or selectively having a different structure. This optical circuit device can be manufactured to have various constitutions, and allows the formation of a multilayer optical circuit.

Abstract: An integrated circuit has an isolation structure in the form of a double diode moat. The P substrate has P+ buried layers 8601 and 8602 on opposite sides of N+ buried layer 8605. Analog devices are formed behind one diode moat, digital CMOS devices are formed behind the other moat.

Abstract: A vertically-isolated bipolar transistor occupying reduced surface area is fabricated by circumscribing an expected active device region within a first narrow trench. The first trench is filled with sacrificial material impermeable to diffusion of conductivity-altering dopant, and then isolation dopant of a conductivity type opposite to that of the substrate is introduced into the trench-circumscribed silicon region. The introduced isolation dopant is then thermally driven into the substrate, with lateral diffusion of isolation dopant physically constrained by the existing first narrow trench. Epitaxial silicon is then formed over the substrate, with polysilicon formed in regions overlying the filled narrow trench. A second, wider trench encompassing the first trench is etched to consume epitaxial silicon, polysilicon, and the sacrificial material. The second trench is then filled with dielectric material.

Abstract: A process for forming a silicon-germanium base of a heterojunction bipolar transistor. First, a silicon substrate having a mesa surrounded by a trench is formed. Next, a silicon-germanium layer is deposited on the substrate and the portion of the silicon-germanium layer adjacent the mesa is removed to form the silicon-germanium base. In a second embodiment, the process comprises the steps of forming a silicon substrate having a mesa surrounded by a trench, forming a dielectric layer in the trench adjacent the mesa, and growing a silicon-germanium layer on the mesa top surface using selective epitaxial growth to form the silicon-germanium base.

Abstract: Reduction in the base to collector capacitance of a heterojunction bipolar transistor, and, improved high frequency performance is achieved using existing materials and processes by undercutting the collector (5) under the base (7) along two parallel sides of the base mesa (7—FIG. 4), and providing a sloped collector edge (5—FIG. 6) along the remaining two parallel sides of the base. The foregoing is accomplished by selective etching and with the four sides of the mesa regions oriented as a non-rectangular parallelogram (7, 9—FIG. 4) in which one pair of sides is in parallel with one of the said [0 0 1] and [0 0 {overscore (1)}] planes of the crystalline structure and the other pair of sides in parallel with one of the [0 1 1] and [0 {overscore (1)} {overscore (1)}] planes of the crystalline structure.

Abstract: A bipolar transistor is vertically isolated from underlying silicon by an isolation layer of conductivity type opposite that of the collector. This isolation layer lies beneath the heavily doped buried layer portion of the collector, and is formed either by ion implantation prior to epitaxial growth of well regions, or by high energy ion implantation into the substrate prior to formation of the well and the heavily doped buried collector layer. Utilization of trench lateral isolation extending into the semiconductor material beyond the isolation layer permits blanket implant of the isolation layer, obviating the need for an additional masking step.

Abstract: The present invention relates to a collector pin and a trench in an integrated circuit intended for high speed communication, and to a manufacturing method for these items. The collector pin is achieved by creating an area which is implantation damaged or made amorphous and at least partially doped (139) by means of ion implantation from an upper silicon surface comprised in a semiconductor structure (144) down to a depth lower than the depth of the surrounding field oxide (120), and that the semiconductor structure (144) is then heat treated.

Abstract: A bi-MOS circuit is fabricated on first active regions assigned to the bipolar transistor and on second active regions assigned to the field effect transistors, and the field effect transistors are fabricated after said bipolar transistor, because a high-temperature heat treatment for an emitter diffusion destroys the impurity profiles of the source/drain regions of the field effect transistors, wherein a part of the field oxide layer between the second active regions is covered with an etching stopper layer before deposition of a thick silicon oxide layer in order to widely space the emitter region from the emitter electrode, even though the thick silicon oxide layer is removed from the field oxide layer between the second active regions for fabricating the field effect transistors, the etching stopper layer prevents the field oxide layer from the etchant, and the field oxide layer between the second active regions maintains the original thickness, thereby never allowing a parasitic MOS transistor to turn on

Abstract: A process for forming a self-aligned BJT (bipolar junction transistor) is disclosed. Conventional front end processes are used to form an N+ layer on a substrate. An N-type collector region is then formed followed by formation of isolation regions on the substrate surface. A deep collection connector region is formed by ion implantation into the N-well. Next, a P base region is formed by ion implantation. An undoped polysilicon (polycide) layer is then deposited on the surface of the substrate. Thereafter, a dielectric layer, which preferably cannot be oxidized, is deposited on top of the undoped polysilicon (polycide) layer. The dielectric layer is then patterned to form a dielectric emitter. Nitride spacers are then formed on the sidewalls of the dielectric emitter. The polysilicon (polycide) layer is then heavily doped with P-type impurities except in the area of the dielectric emitter and nitride spacers.

Abstract: A method of fabricating a feature on a substrate is described. In one embodiment, the fabricated feature is the gate electrode of an MOS transistor. A feature layer is formed on the substrate with a patterned edge definition layer then formed on the feature layer. Next, a spacer layer is formed adjacent to an edge of the patterned edge definition layer. Finally, the feature layer is etched, forming the transistor gate electrode from the feature layer that remains under the spacer.

Abstract: A method for forming a capped shallow trench isolation (CaSTI) structure begin by etching a trench opening (210). The opening (210) is filled with an oxide or like trench fill material (216b) via a deposition and chemical mechanical polish (CMP) step. The plug (216b) is reactive ion etched (RIE) to recess a top of the plug (216b) into the trench opening (210) to form a recessed plug region (216c). A silicon nitride or oxynitride capping layer (218b) is then formed over the recessed plug region (216c) via another deposition and polishing step. The nitride cap layer (218b) protects the underlying region (216c) from erosion due to active area preparation, cleaning, and processing.

Abstract: On an n-type semiconductor substrate 41 doped in high density, a p-type semiconductor layer 2, an n-type semiconductor layer 4 doped in high density, which is a collector, a p-type semiconductor layer 6 doped in high density, which is a base, and the n-type semiconductor layer 7, which is an emitter, are sequentially stacked. To the collector layer, a collector electrode 12 is electrically connected, and to the base layer, a base electrode 11 is electrically connected, and to the emitter layer, an emitter electrode 9 is electrically connected, and thus a bipolar transistor is structured. On the bipolar transistor, an insulated isolation area 55 is formed with an opening therein, whose depth reaches the surface of the substrate, and a substrate electrode 48 is formed thereon. On the bipolar transistor and the insulated isolation area 55, an inter-layer dielectric layer 54 is formed having contact holes formed to upper parts of the emitter electrode 49 and to the substrate electrode 48.

Abstract: Highly integrated bipolar junction transistors include a semiconductor region, a collector region of first conductivity type in the semiconductor region and a trench extending adjacent the collector region. A three-dimensional base region of second conductivity type is also provided. The base region extends along a bottom of the trench and forms a P-N junction with the collector region. An emitter region of first conductivity type is also provided in the base region. The emitter region extends along a sidewall of the trench. The base region preferably comprises an extrinsic base region extending opposite the bottom of the trench and an intrinsic base region extending opposite the sidewall of the trench. The conductivity of the extrinsic base region is greater than the conductivity of the intrinsic base region.

Abstract: The present invention relates to a vertical bipolar power transistor primarily intended for radio frequency applications and to a method for manufacturing the bipolar power transistor. The power transistor comprises a substrate (13), a collector layer (15) of a first conductivity type on the substrate, a base (19) of a second conductivity type electrically connected to the collector layer, an emitter (21) of the first conductivity type electrically connected to the base, the base and the emitter each being electrically connected to a metallic interconnecting layer (31,33), the interconnecting layers (31,33) being at least in parts separated from the collector layer (15) by an insulation oxide (17). According to the invention the power transistor substantially comprises a field shield (25) electrically connected to the emitter, and located between the metallic interconnecting layer of the base and the insulation oxide.

Abstract: A method that enables the fabrication of ballast resistors in polysilicon which can be fabricated in a manner so as to not relax the strained layers in the lattice of the silicon germanium transistor wherein the high temperature steps, associated with activating dopants to fabricate resistors with desired resistance values, are performed prior to the deposited epitaxial layers of silicon germanium.

Abstract: The present invention is to provide a semiconductor integrated circuit having bipolar transistor elements with a reduced isolating distance between adjacent transistors and a reduced collector/substrate capacitance. In the surface of a P-type semiconductor substrate, N.sup.+ type regions are formed serving as buried collector regions of bipolar transistors TR1 and TR2. Between the N.sup.+ type regions, a P-type region for element isolation is provided not in contact with the N.sup.+ type regions. A P-type impurity concentration in the peripheral portions of N.sup.+ type regions is equal to that of the semiconductor substrate. The insulating film serving as an element-isolating layer is provided on the P-type region in contact therewith and thus electrically isolates adjacent bipolar transistors.

Abstract: A method of producing a bipolar transistor includes the step of forming an emitter contact layer containing a high concentration of impurity by means of plasma doping or solid-state diffusion without causing diffusion of impurity in a base layer. This makes it possible to realize a thin base layer having a high impurity concentration.The invention also provides a method of producing a semiconductor device including a bipolar transistor and another device element such as a resistor element including a polysilicon layer containing an activated impurity in such a manner that both the bipolar transistor and the device element are disposed on the same single substrate, the method including the steps of: forming a polysilicon layer containing an activated impurity on the surface of a substrate; and then forming a base layer of the bipolar transistor. This method prevents the base layer from being affected by heat treatment on the polysilicon layer.

Abstract: A new method of forming simultaneously both shallow and deep trenches is described. A pad oxide layer is provided over a semiconductor substrate. A silicon nitride layer is deposited overlying the pad oxide layer. A silicon dioxide layer is deposited overlying the silicon nitride layer. A photoresist mask is formed over the silicon dioxide layer wherein the photoresist mask has a first opening having a first width and a second opening having a second width and wherein the second width is larger than the first width. Trench openings are etched through the silicon dioxide, silicon nitride, and pad oxide layers to the underlying semiconductor substrate within the first and second openings. The photoresist mask is removed.

Abstract: A semiconductor device and a method for manufacturing such a device are presented. The type of semiconductor device is one which merges one type of transistor (e.g., bipolar junction transistors) with another type (e.g., CMOS transistors). Specifically, the semiconductor device may comprise a semiconductor substrate and first buried layers of a first conductive and second type buried layers of a second conductive type both formed within the semiconductor substrate. The first buried layers are preferably at a different level within the semiconductor substrate then the level of the second buried layers. First epitaxial layer portions are formed over the first buried layers and second epitaxial layer portions are formed over the second type buried layers. Isolation regions are formed on the first epitaxial layer portions. In forming the semiconductor substrate, photoresists are formed at regular spatial intervals on a substrate.

Abstract: A heterojunction bipolar transistor. An active region is defined on a silicon collector layer. A silicon-germanium base layer characterized by an integral polycrystalline and epitaxial structure is deposited over the collector such that the epitaxial portion of the base covers substantially the entire active region of the collector. In one version, a field oxide region separates the polycrystalline part of the base layer from the remainder of the collector layer. Alternatively, the collector layer is also characterized by an integral polycrystalline and epitaxial structure; in this version the epitaxial part of the base overlies the epitaxial part of the collector.