Self-aligned Patents (Class 438/320)
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Patent number: 12237407Abstract: The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors (HBTs) with a buried trap rich region and methods of manufacture. The structure includes: a heterojunction bipolar transistor comprising a collector region, a base region and an emitter region; and at least one non-single-crystal semiconductor region in the collector region of the heterojunction bipolar transistor.Type: GrantFiled: November 1, 2022Date of Patent: February 25, 2025Assignee: GlobalFoundries U.S. Inc.Inventors: Anupam Dutta, Rajendran Krishnasamy, Vvss Satyasuresh Choppalli, Vibhor Jain, Robert J. Gauthier, Jr.
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Patent number: 12148755Abstract: The invention relates to a front-side imager comprising in succession: —a semiconductor carrier substrate, a first electrically insulating separating layer, and a single-crystal semiconductor layer, called the active layer, comprising a matrix array of photodiodes, wherein the imager further comprises between the carrier substrate and the first electrically insulating layer: —a second electrically insulating separating layer, and —a second semiconductor or electrically conductive layer, called the intermediate layer, arranged between the second separating layer and the first separating layer, the second separating layer being thicker than the first separating layer.Type: GrantFiled: June 21, 2019Date of Patent: November 19, 2024Assignee: SoitecInventors: Walter Schwarzenbach, Manuel Sellier, Ludovic Ecarnot
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Patent number: 11955380Abstract: In one example, a semiconductor device includes a first conductive feature embedded in a first dielectric layer such that a top surface of the first dielectric layer is higher than a top surface of first conductive feature, a contact etch stop layer (CESL) disposed on the first dielectric layer, and a second conductive feature embedded in a second dielectric layer. The second dielectric layer is disposed on the CESL and the second conductive feature extends through the CESL and is in direct contact with the first conductive feature.Type: GrantFiled: November 18, 2022Date of Patent: April 9, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuo-Chiang Tsai, Jyh-Huei Chen
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Patent number: 11916135Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a bipolar transistor and methods of manufacture. The structure includes: a collector region in a semiconductor substrate; a base region adjacent to the collector region; and an emitter extending above the base region and comprising semiconductor material and a hardmask surrounding a lower portion of the semiconductor material.Type: GrantFiled: January 28, 2022Date of Patent: February 27, 2024Assignee: GLOBALFOUNDRIES U.S. Inc.Inventors: Viorel Ontalus, Justin C. Long, Robert K. Baiocco
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Patent number: 11791404Abstract: A bipolar transistor includes a substrate, a sub-collector layer, a collector layer, a base layer, an emitter layer, a passivation layer, and a collector electrode. The sub-collector layer is formed over the substrate. The collector layer is formed over the sub-collector layer. The base layer is formed over the collector layer. The emitter layer is formed over the base layer. The passivation layer is formed over the substrate and covering a sidewall of the collector layer. The collector electrode is connected to the sub-collector layer through an opening in the passivation layer. The opening exposes at least a portion of the sub-collector layer.Type: GrantFiled: September 29, 2021Date of Patent: October 17, 2023Assignee: WIN SEMICONDUCTORS CORP.Inventors: Chien-Rong Yu, Shu-Hsiao Tsai, Jui-Pin Chiu
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Patent number: 11784245Abstract: An electrically conductive sub-collector layer is provided in a surface layer portion of a substrate. A collector layer, a base layer, and an emitter layer are located within the sub-collector layer when viewed in plan. The collector layer is connected to the sub-collector layer. An emitter electrode and a base electrode are long in a first direction when viewed in plan. The emitter electrode overlaps the emitter layer. The base electrode and the emitter electrode are discretely located away from each other in a second direction orthogonal to the first direction. A collector electrode is located on one side in the second direction with respect to the emitter electrode and is not located on the other side when viewed in plan. A base line is connected to the base electrode in a manner so as to adjoin a portion other than longitudinal ends of the base electrode.Type: GrantFiled: August 25, 2020Date of Patent: October 10, 2023Assignee: Murata Manufacturing Co., Ltd.Inventors: Kenji Sasaki, Yasunari Umemoto, Shigeki Koya, Shinnosuke Takahashi, Masao Kondo
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Patent number: 11664473Abstract: Provided are a single-photon avalanche diode (SPAD) pixel structure and a method of manufacturing the same. More particularly, provided are a SPAD pixel structure and a method of manufacturing the same, including an additional PN junction in a vertical or horizontal direction to increase photon detection efficiency and thus improve the sensitivity in an imaging device.Type: GrantFiled: June 10, 2022Date of Patent: May 30, 2023Assignee: DB HiTek, Co., Ltd.Inventors: Ju Hwan Jung, Byoung Soo Choi, Man Lyun Ha
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Patent number: 11626511Abstract: A bipolar transistor including a first collector layer, a second collector layer, a base layer, and an emitter layer is disposed on a substrate. Etching characteristics of the second collector layer are different from etching characteristics of the first collector layer and the base layer. In plan view, an edge of an interface between the first collector layer and the second collector layer is disposed inside an edge of a lower surface of the base layer, and an edge of an upper surface of the second collector layer coincides with the edge of the lower surface of the base layer or is disposed inside the edge of the lower surface of the base layer.Type: GrantFiled: November 30, 2018Date of Patent: April 11, 2023Assignee: Murata Manufacturing Co., Ltd.Inventors: Isao Obu, Yasunari Umemoto, Masahiro Shibata, Shigeki Koya, Masao Kondo, Takayuki Tsutsui
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Patent number: 11417756Abstract: A method of making a bipolar transistor includes forming a stack of a first, second, third and fourth insulating layers on a substrate. An opening is formed in the stack to reach the substrate. An epitaxial process forms the collector of the transistor on the substrate and selectively etches an annular opening in the third layer. The intrinsic part of the base is then formed by epitaxy on the collector, with the intrinsic part being separated from the third layer by the annular opening. The junction between the collector and the intrinsic part of the base is surrounded by the second layer. The emitter is formed on the intrinsic part and the third layer is removed. A selective deposition of a semiconductor layer on the second layer and in direct contact with the intrinsic part forms the extrinsic part of the base.Type: GrantFiled: February 15, 2021Date of Patent: August 16, 2022Assignee: STMicroelectronics (Crolles 2) SASInventors: Edoardo Brezza, Alexis Gauthier, Fabien Deprat, Pascal Chevalier
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Patent number: 11189715Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes first and second epitaxial layers, and first and second semiconductor layers. The second epitaxial layer is disposed on the first epitaxial layer. The first semiconductor layer extends from above the second epitaxial layer to a top surface of the second epitaxial layer. A vertically extending region of the first semiconductor layer has a body portion and an extending portion extending from a bottom end of the body portion to the second epitaxial layer. A width of the body portion is greater than a width of the extending portion. The second semiconductor layer is disposed on the second epitaxial layer, and laterally surrounds the vertically extending region of the first semiconductor layer. A portion of the second semiconductor layer extends between and overlaps with the body portion of the first semiconductor layer and the second epitaxial layer.Type: GrantFiled: April 27, 2020Date of Patent: November 30, 2021Assignee: Powerchip Semiconductor Manufacturing CorporationInventors: Kuo-Sheng Shih, Hung-Kwei Liao, Chen-Chiang Liu
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Publication number: 20150140771Abstract: A method of producing a semiconductor device, comprising a substrate layer made of a semiconductor material of a first conductivity type and having a first insulation region, and a vertical bipolar transistor having a first vertical portion of a collector made of monocrystalline semiconductor material of a second conductivity type and disposed in an opening of the first insulation region, a second insulation region lying partly on the first vertical portion of the collector and partly on the first insulation region and having an opening in the region of the collector, in which opening a second vertical portion of the collector made of monocrystalline material is disposed, the portion including an inner region of the second conductivity type, a base made of monocrystalline semiconductor material of the first conductivity type, a base connection region surrounding the base in the lateral direction, a T-shaped emitter made of semiconductor material of the second conductivity type and overlapping the base connectType: ApplicationFiled: December 1, 2014Publication date: May 21, 2015Inventors: Alexander FOX, Bernd HEINEMANN, Steffen Marschmeyer
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Patent number: 8987099Abstract: The present disclosure provides a method for making an integrated circuit in one embodiment. The method includes providing a semiconductor substrate having an active region and a first gate stack disposed on the semiconductor substrate in the active region; forming in-situ phosphorous-doped silicon carbide (SiCP) features on the semiconductor substrate and disposed on sides of the first gate stack; replacing the first gate stack with a second gate stack having a high k dielectric material layer; and thereafter performing a millisecond annealing (MSA) process with a thermal profile having a first thermal wavelet and a second thermal wavelet.Type: GrantFiled: December 20, 2011Date of Patent: March 24, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun Hsiung Tsai, Su-Hao Liu, Tsan-Chun Wang
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Patent number: 8673707Abstract: A method for forming a metal gate includes providing a substrate, subsequently forming a dummy gate on the substrate, forming spacers on sidewalls of the dummy gate, forming a stop layer on the substrate, the dummy gate and spacers of the dummy gate, and forming a sacrificial dielectric layer on the dummy gate and the stop layer. The method further includes removing a part of the sacrificial dielectric layer and the stop layer until the dummy gate is exposed and, removing a residual sacrificial dielectric layer, depositing an interlayer dielectric layer on the dummy gate and the stop layer, polishing the interlayer dielectric layer until the dummy gate is exposed, removing the dummy gate to form a trench, and forming a metal gate in the trench. The interlayer dielectric layer is flat and substantially flush with the dummy gate, so that no recesses are formed thereon.Type: GrantFiled: August 4, 2011Date of Patent: March 18, 2014Assignee: Semiconductor Manufacturing International (Shanghai) CorporationInventors: Qiyang He, Yiying Zhang
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Patent number: 8648391Abstract: The product of the breakdown voltage (BVCEO) and the cutoff frequency (fT) of a SiGe heterojunction bipolar transistor (HBT) is increased beyond the Johnson limit by utilizing a doped region with a hollow core that extends down from the base to the heavily-doped buried collector region. The doped region and the buried collector region have opposite dopant types.Type: GrantFiled: March 23, 2012Date of Patent: February 11, 2014Assignee: Texas Instruments IncorporatedInventors: Jeffrey A. Babcock, Alexei Sadovnikov
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Patent number: 8613862Abstract: A manufacturing method, for a liquid discharge head substrate that includes a silicon substrate in which a liquid supply port is formed, includes the steps of: preparing the silicon substrate, on one face of which a mask layer, in which an opening has been formed, is deposited; forming a first recessed portion in the silicon substrate, so that the recessed portion is extended through the opening from the one face of the silicon substrate to the other, reverse face of the silicon substrate; forming a second recessed portion by performing wet etching for the substrate, via the first recessed portion, using the mask layer; and performing dry etching for the silicon substrate in a direction from the second recessed portion to the other face.Type: GrantFiled: September 3, 2008Date of Patent: December 24, 2013Assignee: Canon Kabushiki KaishaInventors: Kazuhiro Asai, Hirokazu Komuro, Satoshi Ibe, Takuya Hatsui, Shimpei Otaka, Hiroto Komiyama, Keisuke Kishimoto
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Publication number: 20130313614Abstract: The present invention discloses a metal silicide self-aligned SiGe heterojunction bipolar transistor, which is designed to overcome the shortcomings such as the large base resistance RB of the prior art products. The metal silicide self-aligned SiGe heterojunction bipolar transistor of the present invention mainly comprises an Si collector region, a local dielectric region, a base region, a base-region low-resistance metal silicide layer, a polysilicon emitter region, an emitter-base spacer dielectric region composed of a liner silicon oxide layer and a silicon nitride inner sidewall, a monocrystalline emitter region, a contact hole dielectric layer, an emitter metal electrode and a base metal electrode. The base-region low-resistance metal silicide layer extends all the way to the outside of the emitter-base spacer dielectric region. The present invention discloses a method of forming a metal silicide self-aligned SiGe heterojunction bipolar transistor, which is used to form the aforesaid bipolar transistor.Type: ApplicationFiled: September 24, 2012Publication date: November 28, 2013Applicant: TSINGHUA UNIVERSITYInventors: Jun Fu, Yu-dong Wang, Wei Zhang, Gao-qing Li, Zheng-li Wu, Jie Cui, Yue Zhao, Zhi-hong Liu
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Patent number: 8574994Abstract: A heterojunction bipolar transistor is formed with an emitter electrode that comprises an emitter epitaxy underlying an emitter metal cap and that has horizontal dimensions that are substantially equal to the emitter metal cap.Type: GrantFiled: October 22, 2010Date of Patent: November 5, 2013Assignee: HRL Laboratories, LLCInventor: Charles H. Fields
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Patent number: 8486797Abstract: Bipolar junction transistors are provided in which at least one of an emitter contact, a base contact, or a collector contact thereof is formed by epitaxially growing a doped SixGe1-x layer, wherein x is 0?x?1, at a temperature of less than 500° C. The doped SixGe1-x layer comprises crystalline portions located on exposed surfaces of a crystalline semiconductor substrate and non-crystalline portions that are located on exposed surfaces of a passivation layer which can be formed and patterned on the crystalline semiconductor substrate. The doped SixGe1-x layer of the present disclosure, including the non-crystalline and crystalline portions, contains from 5 atomic percent to 40 atomic percent hydrogen.Type: GrantFiled: May 25, 2012Date of Patent: July 16, 2013Assignee: International Business Machines CorporationInventors: Bahman Hekmatshoartabari, Tak H. Ning, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi
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Publication number: 20130146947Abstract: A self-aligned bipolar transistor and method of fabricating the same are disclosed. In an embodiment, a substrate and an intrinsic base are provided, followed by a first oxide layer, and an extrinsic base over the first oxide layer. A first opening is formed, exposing a portion of a surface of the extrinsic base. Sidewall spacers are formed in the first opening, and a self-aligned oxide mask is selectively formed on the exposed surface of the extrinsic base. The spacers are removed, and using the self-aligned oxide mask, the exposed extrinsic base and the first oxide layer are etched to expose the intrinsic base layer, forming a first and a second slot. A silicon layer stripe is selectively grown on the exposed intrinsic and/or extrinsic base layers in each of the first and second slots, substantially filling the respective slot.Type: ApplicationFiled: December 13, 2011Publication date: June 13, 2013Applicant: International Business Machines CorporationInventors: Kevin K. Chan, David L. Harame, Russell T. Herrin, Qizhi Liu
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Publication number: 20130113020Abstract: A SiGe HBT is disclosed, which includes: a silicon substrate; shallow trench field oxides formed in the silicon substrate; a pseudo buried layer formed at bottom of each shallow trench field oxide; a collector region formed beneath the surface of the silicon substrate, the collector region being sandwiched between the shallow trench field oxides and between the pseudo buried layers; a polysilicon gate formed above each shallow trench field oxide having a thickness of greater than 150 nm; a base region on the polysilicon gates and the collector region; emitter region isolation oxides on the base region; and an emitter region on the emitter region isolation oxides and a part of the base region. The polysilicon gate is formed by gate polysilicon process of a MOSFET in a CMOS process. A method of manufacturing the SiGe HBT is also disclosed.Type: ApplicationFiled: September 13, 2012Publication date: May 9, 2013Applicant: SHANGHAI HUA HONG NEC ELECTRONICS CO., LTD.Inventors: Donghua Liu, Wenting Duan, Wensheng Qian, Jun Hu, Jing Shi
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Publication number: 20130092939Abstract: Disclosed are example bipolar transistors capable of reducing the area of a collector, reducing the distance between a base and a collector, and/or reducing the number of ion implantation processes. A bipolar transistor may includes a trench formed by etching a portion of a semiconductor substrate. A first collector may be formed on the inner wall of the trench. A second collector may be formed inside the semiconductor substrate in the inner wall of the trench. A first isolation film may be formed on the sidewall of the first collector. An intrinsic base may be connected to the third collector. An extrinsic base may be formed on the intrinsic base and inside the first isolation film. A second isolation film may be formed on the inner wall of the extrinsic base. An emitter may be formed by burying a conductive material inside the second isolation film.Type: ApplicationFiled: July 6, 2012Publication date: April 18, 2013Applicant: Dongbu HiTek Co., Ltd.Inventor: Nam Joo KIM
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Publication number: 20120132961Abstract: Disclosed is a method of manufacturing a heterojunction bipolar transistor comprising a substrate, an upper region of said substrate comprising an active region of the bipolar transistor bordered by shallow trench insulation, said active region comprising a buried collector region extending to a depth beyond the depth of the shallow trench insulation, the method comprising forming a trench in the substrate adjacent to said active region, said trench extending through the shallow trench insulation; at least partially filling said trench with an impurity; and forming a collector sinker in the substrate by developing said impurity to extend into the substrate to a depth beyond the depth of the shallow trench insulation. An IC comprising a heterojunction bipolar transistor manufactured by this method is also disclosed.Type: ApplicationFiled: November 18, 2011Publication date: May 31, 2012Applicant: NXP B.V.Inventors: Tony Vanhoucke, Johannes Josephus Theodorus Marinus Donkers, Hans Mertens, Blandine Duriez, Evelyne Gridelet
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Patent number: 8133791Abstract: The invention relates to a method according to the part of the surface of the semiconductor body adjoining the opening and which is to be kept free is provided with a cover layer after which the high-crystalline layer is formed by means of a deposition process. The material of the cover layer can then easily be chosen such that it can be selectively etched relative to the silicon underneath. In addition, the cover layer can easily be selectively deposited on the relevant part of the surface because use can be made of an anisotropic deposition process. In such a process the cover layer is not deposited in the hollow and on the bottom of the hollow. It will be apparent that for the high-crystalline layer also other materials can be chosen such as SiGe having such low Ge contents that the SiGe cannot be etched selectively very well compared to the Silicon.Type: GrantFiled: June 12, 2007Date of Patent: March 13, 2012Assignee: NXP B.V.Inventors: Erwin B. Hijzen, Philippe Meunier-Bellard, Johannes J. T. M. Donkers
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Patent number: 8048734Abstract: One or more embodiments of the invention relate to a method of making a heterojunction bipolar transistor, including: forming a collector layer; forming a stack of at least a second dielectric layer overlying a first dielectric layer, the stack formed over the collector layer; removing a portion of each of the dielectric layers to form an opening through the stack; and forming a base layer within the opening.Type: GrantFiled: October 5, 2009Date of Patent: November 1, 2011Assignee: Infineon Technologies AGInventor: Detlef Wilhelm
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Patent number: 7935606Abstract: A method in which an oxide layer is formed on material defining and surrounding an emitter window. The technique comprises depositing a non-conformal oxide layer on the surrounding material and in the emitter window, whereby the thickness of at least a portion of the oxide layer in the emitter window is smaller than the thickness of the oxide layer on the surrounding material outside the emitter window; and removing at least a portion of the oxide layer in the emitter window so as to reveal at least a portion of the bottom of the emitter window whilst permitting at least a portion of the oxide layer to remain on the surrounding material. The technique can be used in the manufacture of a self-aligned epitaxial base BJT (bipolar junction transistor) or SiGe HBT (hetero junction bipolar transistor).Type: GrantFiled: April 18, 2006Date of Patent: May 3, 2011Assignee: X-Fab Semiconductor Foundries AGInventor: Jun Fu
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Patent number: 7923340Abstract: The invention, in one aspect, provides a method for fabricating a semiconductor device. In one aspect, the method provides for a dual implantation of a tub of a bipolar transistor. The tub in bipolar region is implanted by implanting the tub through separate implant masks that are also used to implant tubs associated with MOS fabricate different voltage devices in a non-bipolar region during the fabrication of MOS transistors.Type: GrantFiled: February 14, 2007Date of Patent: April 12, 2011Assignee: Agere Systems Inc.Inventors: Alan S. Chen, Mark Dyson, Nace M. Rossi, Ranbir Singh, Xiaojun Yuan
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Patent number: 7892943Abstract: A first dielectric plug is formed in a portion of a trench that extends into a substrate of a memory device so that an upper surface of the first dielectric plug is recessed below an upper surface of the substrate. The first dielectric plug has a layer of a first dielectric material and a layer of a second dielectric material formed on the layer of the first dielectric material. A second dielectric plug of a third dielectric material is formed on the upper surface of the first dielectric plug.Type: GrantFiled: December 21, 2007Date of Patent: February 22, 2011Assignee: Micron Technology, Inc.Inventor: Michael Violette
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Patent number: 7875523Abstract: A heterojunction bipolar transistor is formed with an emitter electrode that comprises an emitter epitaxy underlying an emitter metal cap and that has horizontal dimensions that are substantially equal to the emitter metal cap.Type: GrantFiled: June 16, 2005Date of Patent: January 25, 2011Assignee: HRL Laboratories, LLCInventor: Charles H. Fields
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Patent number: 7846806Abstract: A system and method are disclosed for providing a self aligned silicon germanium (SiGe) heterojunction bipolar transistor using a mesa emitter-base architecture. The transistor of the present invention comprises a non-selective epitaxial growth (NSEG) collector, an NSEG base, an NSEG emitter and a raised external base that is formed by the selective epitaxial growth (SEG) of a doped polysilicon layer.Type: GrantFiled: May 25, 2007Date of Patent: December 7, 2010Assignee: National Semiconductor CorporationInventors: Jamal Ramdani, Mingwei Xu
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Patent number: 7838375Abstract: A system and method are disclosed for providing an improved polyemit module for a self aligned heterojunction bipolar transistor architecture. The polyemit module of the transistor of the present invention is formed using a double layer deposition process. In the double layer deposition process, the first layer is a layer of emitter polysilicon and the second layer is a sacrificial layer of silicon germanium (SiGe). The shape and thickness of the emitter polysilicon layer of the polyemit module provides (1) a reduction in the overall resistance of the emitter and (2) an increase in the contact area between the emitter polysilicon layer and a contact structure that is more than three times the contact area that is provided in prior art polyemit modules.Type: GrantFiled: May 25, 2007Date of Patent: November 23, 2010Assignee: National Semiconductor CorporationInventors: Mingwei Xu, Jamal Ramdani
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Patent number: 7732292Abstract: Disclosed is a method of forming a transistor in an integrated circuit structure that begins by forming a collector in a substrate and an intrinsic base above the collector. Then, the invention patterns an emitter pedestal for the lower portion of the emitter on the substrate above the intrinsic base. Before actually forming the emitter or associates spacer, the invention forms an extrinsic base in regions of the substrate not protected by the emitter pedestal. After this, the invention removes the emitter pedestal and eventually forms the emitter where the emitter pedestal was positioned.Type: GrantFiled: August 15, 2007Date of Patent: June 8, 2010Assignee: International Business Machines CorporationInventors: Marwan H. Khater, Francois Pagette
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Publication number: 20100133586Abstract: Provided are a heterojunction bipolar transistor and a method of forming the same.Type: ApplicationFiled: May 8, 2009Publication date: June 3, 2010Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Byoung-Gue MIN, Jong-Min Lee, Seong-II Kim, Kyung-Ho Lee, Hyung-Sup Yoon, Eun-Soo Nam
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Patent number: 7709338Abstract: A method of fabricating an heterojunction bipolar transistor (HBT) structure in a bipolar complementary metal-oxide-semiconductor (BiCMOS) process selectively thickens an oxide layer overlying a base region in areas that are not covered by a temporary emitter and spacers such that the temporary emitter can be removed and the base-emitter junction can be exposed without also completely removing the oxide overlying the areas of the base region that are not covered by the temporary emitter or spacers. As a result, a photomask is not required to remove the temporary emitter and to expose the base-emitter junction.Type: GrantFiled: December 21, 2006Date of Patent: May 4, 2010Assignee: International Business Machines CorporationInventors: Qizhi Liu, Peter B. Gray, Alvin J. Joseph
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Patent number: 7696034Abstract: Methods for fabricating a heterojunction bipolar transistor having a raised extrinsic base is provided in which the base resistance is reduced by forming a silicide atop the raised extrinsic base that extends to the emitter region in a self-aligned manner. The silicide formation is incorporated into a BiCMOS process flow after the raised extrinsic base has been formed. The present invention also provides a heterojunction bipolar transistor having a raised extrinsic base and a silicide located atop the raised extrinsic base. The silicide atop the raised extrinsic base extends to the emitter in a self-aligned manner. The emitter is separated from the silicide by a spacer.Type: GrantFiled: May 28, 2008Date of Patent: April 13, 2010Assignee: International Business Machines CorporationInventors: Peter J. Geiss, Marwan H. Khater, Qizhi Liu, Randy W. Mann, Robert J. Purtell, Beth Ann Rainey, Jae-Sung Rieh, Andreas D. Stricker
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Patent number: 7651919Abstract: A method for fabricating a heterojunction bipolar transistor (HBT) is provided. The method includes providing a substrate including a collector region; forming a compound base region over the collector region; and forming an emitter region over the compound base region including forming a first emitter layer within the emitter region and doping the first emitter layer with a pre-determined percentage of at least one element associated with the compound base region. In one implementation, an emitter region is formed including multiple emitter layers to enhance a surface recombination surface area within the emitter region.Type: GrantFiled: November 4, 2005Date of Patent: January 26, 2010Assignee: Atmel CorporationInventors: Darwin Gene Enicks, Damian Carver
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Patent number: 7615457Abstract: A method is provided for making a bipolar transistor which includes a tapered, i.e. frustum-shaped, collector pedestal having an upper substantially planar surface, a lower surface, and a slanted sidewall extending between the upper surface and the lower surface, the upper surface having substantially less area than the lower surface. The collector pedestal can be formed on a surface of a collector active region exposed within an opening extending through first and second overlying dielectric regions, where the opening defines vertically aligned edges of the first and second dielectric regions.Type: GrantFiled: July 25, 2008Date of Patent: November 10, 2009Assignee: International Business Machines CorporationInventors: Hiroyuki Akatsu, Rama Divakaruni, Gregory G. Freeman, David R. Greenberg, Marwan H. Khater, William R. Tonti
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Patent number: 7615455Abstract: A bipolar transistor having a base region resting by its lower surface on a collector region and surrounded with a first insulating layer, a base contact conductive region in contact with an external upper peripheral region of the base region, a second insulating region in contact with an intermediary upper peripheral region of the base region, an emitter region in contact with the central portion of the base region. The level of the central portion is higher than the level of the intermediary portion.Type: GrantFiled: September 19, 2006Date of Patent: November 10, 2009Assignee: STMicroelectronics S.A.Inventors: Pascal Chevalier, Alain Chantre
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Patent number: 7611955Abstract: A semiconductor component is formed using the following processes: (a) forming a first dielectric layer over the semiconductor substrate; (b) forming a base electrode for the bipolar transistor over the dielectric layer; (c) forming an oxide nitride structure over the base electrode; (d) forming a first spacer adjacent to the oxide nitride structure and the base electrode; (e) removing a top layer of the oxide nitride structure; (f) removing a first portion of the dielectric layer; (g) forming an epitaxial layer over the semiconductor substrate; (h) forming a second spacer over the epitaxial layer; and (i) forming an emitter electrode over the epitaxial layer and adjacent to the second spacer.Type: GrantFiled: June 15, 2006Date of Patent: November 3, 2009Assignee: Freescale Semiconductor, Inc.Inventors: Jay P. John, James A. Kirchgessner, Matthew W. Menner
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Patent number: 7598148Abstract: The present invention refers to a method for preparing a non-self-aligned heterojunction bipolar transistor comprising: preparing a patterned emitter metal on an emitter epi layer of a HBT epi structure on a substrate; preparing an emitter epitaxy below the emitter metal; applying a resist layer on the top surface covering the emitter metal and emitter epitaxy, and the base layer; applying lithography leaving the emitter epitaxy and the emitter metal covered by the resist vertically with a width pD and leaving a pattern according to the mask in the resist; removing the remaining resist and the base metal covering the resist defining a base metal, the base metal being spaced from the emitter epitaxy and the emitter metal by a distance xD. The present invention refers to a non-self-aligned heterojunction bipolar transistor as prepared by this method.Type: GrantFiled: October 15, 2004Date of Patent: October 6, 2009Inventor: Charles H. Fields
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Patent number: 7557010Abstract: The invention, in one aspect, provides a method for fabricating a semiconductor device, which includes conducting an etch through an opening in an emitter layer to form a cavity from an underlying oxide layer that exposes a doped tub. A first silicon/germanium (SiGe) layer, which has a Ge concentration therein, is formed within the cavity and over the doped tub by adjusting a process parameter to induce a strain in the first SiGe layer. A second SiGe layer is formed over the first SiGe layer, and a capping layer is formed over the second SiGe layer.Type: GrantFiled: February 12, 2007Date of Patent: July 7, 2009Assignee: Agere Systems Inc.Inventors: Alan S. Chen, Mark Dyson, Nace M. Rossi, Ranbir Singh
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Patent number: 7521313Abstract: This invention provides a method of fabricating an active matrix of thin film devices through a pattern reversal self aligned imprint lithography (SAIL) process. The method includes providing a substrate and depositing at least one layer of material upon the substrate. A pattern is then established upon the layer of material, the pattern providing at least one exposed area and at least one covered area of the layer of material. The exposed areas are treated to provide etch resistance to the material and reverse the pattern. Subsequent etching removes the etch susceptible material, the etch resistant material remaining. A thin-film stack is then deposited upon the remaining etch resistant material. These deposited thin-films are then processed in accordance with the desired characteristics of the thin film devices.Type: GrantFiled: January 18, 2005Date of Patent: April 21, 2009Assignee: Hewlett-Packard Development Company, L.P.Inventor: Ping Mei
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Publication number: 20090075446Abstract: The invention provides a method for fabricating a heterojunction bipolar transistor with a base connecting region (23), which is formed self-aligned to a base region (7) without applying photolithographic techniques. Further, a collector connecting region (31) and an emitter region (29) are formed simultaneously and self-aligned to the base connecting region (23) without applying photolithographic techniques.Type: ApplicationFiled: April 3, 2006Publication date: March 19, 2009Applicant: NXP B.V.Inventors: Philippe Meunier-Beillard, Johannes J.T.M. Donkers, Hijzen Erwin, Melai Joost
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Patent number: 7498620Abstract: According to one exemplary embodiment, a heterojunction bipolar transistor includes a base situated on a substrate. The heterojunction bipolar transistor can be an NPN silicon-germanium heterojunction bipolar transistor, for example. The heterojunction bipolar transistor further includes a cap layer situated on the base, where the cap layer includes a barrier region. The barrier region can comprises carbon and has a thickness, where the thickness of the barrier region determines a depth of an emitter-junction of the heterojunction bipolar transistor. An increase in the thickness of the barrier region can cause a decrease in the depth of the emitter-base junction. According to this exemplary embodiment, the heterojunction bipolar transistor further includes an emitter situated over the cap layer, where the emitter comprises an emitter dopant, which can be phosphorus. A diffusion retardant in the barrier region of the cap layer impedes diffusion of the emitter dopant.Type: GrantFiled: September 21, 2006Date of Patent: March 3, 2009Assignee: Newport Fab, LLCInventor: Greg D. U'Ren
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Patent number: 7465969Abstract: A bipolar transistor includes a Si single crystalline layer serving as a collector, a single crystalline Si/SiGeC layer and a polycrystalline Si/SiGeC layer which are formed on the Si single crystalline layer, an oxide film having an emitter opening portion, an emitter electrode, and an emitter layer. An intrinsic base layer is formed on the single crystalline Si/SiGeC layer, part of the single crystalline Si/SiGeC layer, the polycrystalline Si/SiGeC layer and the Co silicide layer together form an external base layer. The thickness of the emitter electrode is set so that boron ions implanted into the emitter electrode and diffused therein do not reach an emitter-base junction portion.Type: GrantFiled: June 12, 2006Date of Patent: December 16, 2008Assignee: Panasonic CorporationInventors: Teruhito Ohnishi, Koichiro Yuki, Tsuneichiro Sano, Tohru Saitoh, Ken Idota, Takahiro Kawashima, Shigeki Sawada
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Patent number: 7422951Abstract: The present invention provides a method of fabricating a self-aligned bipolar transistor, by which the fabricating method can be simplified by forming P+ and N+ junctions by self-alignment and by which device reliability can be enhanced. The present invention includes the steps of forming a well in a substrate isolated by a device isolation layer, forming a polysilicon gate on the substrate, forming an insulating layer on the substrate, forming a sidewall spacer on lateral sides of the polysilicon gate by etching the insulating layer, forming a P+ ion implanted region in the substrate, forming an N+ ion implanted region in the substrate, and forming silicide on the P+ and N+ ion implanted regions.Type: GrantFiled: December 28, 2004Date of Patent: September 9, 2008Assignee: Dongbu Electronics Co., Ltd.Inventor: Kwang Young Ko
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Publication number: 20080164495Abstract: A heterojunction bipolar transistor structure with self-aligned sub-lithographic extrinsic base region including a self-aligned metal-semiconductor alloy and self-aligned metal contacts made to the base is disclosed. The lateral dimension of the extrinsic base region is defined by the footprint of a sacrificial spacer, and its thickness is controlled by selective epitaxy. A self-aligned semiconductor-metal alloy and self-aligned metal contacts are made to the extrinsic base using a method compatible with conventional silicon processing.Type: ApplicationFiled: January 10, 2007Publication date: July 10, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Guy M. Cohen, Francois Pagette
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Patent number: 7390721Abstract: Methods for fabricating a heterojunction bipolar transistor having a raised extrinsic base is provided in which the base resistance is reduced by forming a silicide atop the raised extrinsic base that extends to the emitter region in a self-aligned manner. The silicide formation is incorporated into a BiCMOS process flow after the raised extrinsic base has been formed. The present invention also provides a heterojunction bipolar transistor having a raised extrinsic base and a silicide located atop the raised extrinsic base. The silicide atop the raised extrinsic base extends to the emitter in a self-aligned manner. The emitter is separated from the silicide by a spacer.Type: GrantFiled: September 21, 2005Date of Patent: June 24, 2008Assignee: International Business Machines CorporationInventors: Peter J. Geiss, Marwan H. Khater, Qizhi Liu, Randy W. Mann, Robert J. Purtell, BethAnn Rainey, Jae-Sung Rieh, Andreas D. Stricker
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Publication number: 20080116488Abstract: An HBT structure and manufacturing method thereof, in which the HBT structure includes an emitter, an intrinsic base, a collector, an insulating sidewall, and a stress-inducting base formed by selective epitaxial growth to locally induce a stress to the HBT structure. Compressive or tensile stress is additionally induced from outside to modify physical and electric properties of a semiconductor layer, thereby improving the performance of the transistor.Type: ApplicationFiled: February 16, 2007Publication date: May 22, 2008Inventors: Kyu-Hwan Shim, Sang-Sig Choi, A-Ram Choi
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Patent number: 7368764Abstract: A heterojunction bipolar transistor and a method of making a heterojunction bipolar transistor. The heterojunction bipolar transistor includes: a regrown emitter region; an intrinsic base region forming a junction with the regrown emitter region; and an extrinsic base region separated from the regrown emitter region. The thickness of the extrinsic base region is greater than the thickness of the intrinsic base region.Type: GrantFiled: April 18, 2005Date of Patent: May 6, 2008Assignee: HRL Laboratories, LLCInventors: Stephen Thomas, III, Kenneth Robert Elliott, David Chow
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Patent number: 7354820Abstract: A method for fabricating an HBT is disclosed, wherein successive emitter, base, collector and sub-collector epitaxial layers are deposited on a substrate, with the substrate being adjacent to the sub-collector layer. The epitaxial layers are etched to provide locations for contact metals and emitter, base and contact metals are deposited on the emitter, base and sub-collector epitaxial layers, respectively. A self-alignment material is deposited on the surface of the substrate around the epitaxial layers and a planarization material is deposited on and covers the top surface of the HBT. The planarization material is then etched so it has a planar surface about the same level as the surface of the self-alignment material and the contact metals protrude from the planar surface. The planar metals are then deposited over the protruding portions of the contact metals.Type: GrantFiled: September 14, 2005Date of Patent: April 8, 2008Assignee: Teledyne Licensing, LLCInventors: Richard L. Pierson, Jr., James Chingwei Li, Berinder P. S. Brar, John A. Higgins